AVALANCHE TECHNOLOGY INC. Patent applications |
Patent application number | Title | Published |
20160118102 | METHOD AND APPARATUS FOR WRITING TO A MAGNETIC TUNNEL JUNCTION (MTJ) BY APPLYING INCREMENTALLY INCREASING VOLTAGE LEVEL - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ. | 04-28-2016 |
20160078916 | FAST PROGRAMMING OF MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage. | 03-17-2016 |
20160021073 | SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) - A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified. | 01-21-2016 |
20150332748 | VOLTAGE-SWITCHED MAGNETIC RANDOM ACCESS MEMORY (MRAM) AND METHOD FOR USING THE SAME - The present invention is directed to a magnetic random access memory comprising a first magnetic tunnel junction (MTJ) including a first magnetic reference layer and a first magnetic free layer with a first insulating tunnel junction layer interposed therebetween; a second MTJ including a second magnetic reference layer and a second magnetic free layer with a second insulating tunnel junction layer interposed therebetween; and an anti-ferromagnetic coupling layer formed between the first and second variable magnetic free layers. The first and second magnetic free layers have a first and second magnetization directions, respectively, that are perpendicular to the layer planes thereof. The first magnetic reference layer has a first pseudo-fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a second pseudo-fixed magnetization direction that is substantially perpendicular to the layer plane thereof and is substantially opposite to the first pseudo-fixed magnetization direction. | 11-19-2015 |
20150316971 | METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION OF MOBILE AND PORTABLE DEVICES WITH NON-VOLATILE MEMORIES - An unified power management scheme for all the idle subsystems during normal mode of operation and power save mode of operation reduces significant power and time during saving and restoring context of System on a chip (SoC). Power management schemes based on subset of manufacturing tests and high speed non-volatile memory provides transparency and shortest latency of entering and exiting power save mode and as a result providing significant power savings and extending battery life. Due to the shortest logic delays in some phases of logic scan, memory BIST and analog BIST, entry procedure and exit procedures from power save mode consume least amount of time with little overhead due to clock switching and power gating procedures. Any part of SoC that can be tested during manufacture using standard procedures of logic scan, memory BIST, analog BIST and boundary scan will be able to enter and exit power save mode and still retain the state. By enabling power to the functional units only while they are performing a function prolongs the duration of normal operation with a single charging of the battery for mobile and portable devices. | 11-05-2015 |
20150311252 | MAGNETIC RANDOM ACCESS MEMORY WITH ULTRATHIN REFERENCE LAYER - The present invention is directed to an MRAM device comprising a plurality of MTJ memory elements. Each of the memory elements includes a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof. The magnetic fixed layer has a second fixed magnetization direction that is substantially perpendicular to the layer plane thereof and is substantially opposite to the first fixed magnetization direction. | 10-29-2015 |
20150212755 | METHOD OF MANAGING THROUGHPUT OF REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) GROUPS IN A SOLID STATE DISK ARRAY - A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command. | 07-30-2015 |
20150199152 | METHOD OF MANAGING REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) GROUPS IN A SOLID STATE DISK ARRAY - A method of managing redundant array of independent disk (RAID) groups in a storage system includes determining wear of each of the plurality of RAID groups, computing the weight for each of RAID groups based on the wear, and striping data across at least one of the RAID groups based on the weight of each of the RAID groups. | 07-16-2015 |
20150131370 | MULTI-LEVEL CELLS AND METHOD FOR USING THE SAME - The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention. | 05-14-2015 |
20150131369 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 05-14-2015 |
20150104882 | FABRICATION METHOD FOR HIGH-DENSITY MRAM USING THIN HARD MASK - Embodiments of the invention are described that use a thin metallic hard mask, which can be a bi-layer film, to increase the incident IBE angle for MTJ sidewall cleaning without losing the process margin for the subsequent interconnection process. The patterned metallic hard mask pads also serve as the top electrode for the MTJ cells. Using a thin metallic hard mask is possible when the hard mask material acts as a CMP stopper without substantial loss of thickness. In the first embodiment, the single layer hard mask is preferably ruthenium. In the second embodiment, the lower layer of the bi-layer hard mask is preferably ruthenium. The wafer is preferably rotated during the IBE process for uniform etching. A capping layer under the hard mask is preferably used as the etch stopper during hard mask etch process in order not to damage or etch through the upper magnetic layer. | 04-16-2015 |
20150102441 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER AND THIN REFERENCE LAYER - The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto. | 04-16-2015 |
20150102439 | MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR ENHANCEMENT LAYER - The present invention is directed to an MRAM element comprising a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic reference layer structure, which includes a first and a second magnetic reference layers with a tantalum perpendicular enhancement layer interposed therebetween, an insulating tunnel junction layer formed adjacent to the first magnetic reference layer opposite the tantalum perpendicular enhancement layer, and a magnetic free layer formed adjacent to the insulating tunnel junction layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof. | 04-16-2015 |
20150102438 | MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR INTERFACIAL ANISOTROPY - The present invention is directed to an MRAM element comprising a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic free layer structure has a variable magnetization direction substantially perpendicular to the layer plane thereof. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a multilayer structure comprising a first magnetic reference sublayer formed adjacent to the first non-magnetic perpendicular enhancement layer and a second magnetic reference sublayer separated from the first magnetic reference sublayer by an intermediate metallic layer. | 04-16-2015 |
20150095555 | METHOD OF THIN PROVISIONING IN A SOLID STATE DISK ARRAY - A method of thin provisioning in a storage system is disclosed. The method includes communicating to a user a capacity of a virtual storage, the virtual storage capacity being substantially larger than that of a storage pool. Further, the method includes assigning portions of the storage pool to logical unit number (LUN) logical block address (LBA)-groups only when the LUN LBA-groups are being written to and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool. | 04-02-2015 |
20150095554 | STORAGE PROCESSOR MANAGING SOLID STATE DISK ARRAY - A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs. | 04-02-2015 |
20150084140 | LANDING PAD IN PERIPHERAL CIRCUIT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) - The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings. | 03-26-2015 |
20150074347 | SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) - A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified. | 03-12-2015 |
20150032943 | CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories. | 01-29-2015 |
20150026392 | HOST-MANAGED Logical MASS STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance. | 01-22-2015 |
20140289587 | MEMORY WITH ON-CHIP ERROR CORRECTION - A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword. | 09-25-2014 |
20140281825 | Method for Reducing Effective Raw Bit Error Rate in Multi-Level Cell NAND Flash Memory - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 09-18-2014 |
20140281680 | DUAL DATA RATE BRIDGE CONTROLLER WITH ONE-STEP MAJORITY LOGIC DECODABLE CODES FOR MULTIPLE BIT ERROR CORRECTIONS WITH LOW LATENCY - A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components. | 09-18-2014 |
20140281464 | METHOD OF IMPLEMENTING MAGNETIC RANDOM ACCESS MEMORY (MRAM) FOR MOBILE SYSTEM-ON CHIP BOOT - A method of booting a system on chip (SoC) includes using an on-chip MRAM located in the SoC, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory (MRAM) located in and residing on the same semiconductor as the SoC. The method further includes directly executing the boot software from the on-chip MRAM by the SoC and directly accessing the user-personalized information from the MRAM by the SoC. | 09-18-2014 |
20140281142 | Storage System Employing MRAM and Redundant Array of Solid State Disk - A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided. | 09-18-2014 |
20140281069 | MULTI ROOT SHARED PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) END POINT - A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table. | 09-18-2014 |
20140269041 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 09-18-2014 |
20140269040 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 09-18-2014 |
20140258604 | NON-VOLATILE STORAGE MODULE HAVING MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH A BUFFER WINDOW - A block storage system includes a host and comprises a block storage module that is coupled to the host. The block storage module includes a MRAM array and a bridge controller buffer coupled to communicate with the MRAM array. The MRAM array includes a buffer widow that is moveable within the MRAM array to allow contents of the MRAM array to be read by the host through the bridge controller buffer even when the capacity of the bridge controller buffer is less than the size of the data being read from the MRAM array. | 09-11-2014 |
20140254245 | HYBRID NON-VOLATILE MEMORY DEVICE - A hybrid non-volatile memory device includes a non-volatile random access memory (NVRAM) having an array of magnetic memory elements, the NVRAM being bit-accessible. The hybrid non-volatile device further includes a non-volatile page-mode memory (PMM) made of resistive memory and organized into pages, the non-volatile PMM being page-accessible. Further included in the hybrid non-volatile memory device is a direct memory access (DMA) engine that is coupled to the NVRAM and the non-volatile PMM and transfers data between the NVRAM and the non-volatile PMM during a DMA operation. | 09-11-2014 |
20140252356 | DEVICES AND METHODS FOR MEASUREMENT OF MAGNETIC CHARACTERISTICS OF MRAM WAFERS USING MAGNETORESISTIVE TEST STRIPS - Methods for testing magnetoresistance of test devices with layer stacks, such as MTJs, fabricated on a wafer are described. The test devices can be fabricated along with arrays of similarly structured memory cells on a production wafer to allow in-process testing. The test devices with contact pads at opposite ends of the bottom electrode allow resistance across the bottom electrode to be measured as a surrogate for measuring resistance between the top and bottom electrodes. An MTJ test device according to the invention has a measurable magnetoresistance (MR) between the two contact pads that is a function of the magnetic orientation of the free layer and varies with the length and width of the MTJ strip in each test device. The set of test MTJs can include a selected range of lengths to allow the tunnel magnetoresistance (TMR) and resistance area product (RA) to be estimated or predicted. | 09-11-2014 |
20140248719 | MTJ MANUFACTURING METHOD UTILIZING IN-SITU ANNEALING AND ETCH BACK - The present invention is directed to a method for manufacturing spin transfer torque magnetic random access memory (STTMRAM) devices. The method, which utilizes in-situ annealing and etch-back of the magnetic tunnel junction (MTJ) film stack, comprises the steps of depositing a barrier layer on top of a bottom magnetic layer and then depositing an interface magnetic layer on top of the barrier layer to form an MTJ film stack; annealing the MTJ film stack at a first temperature and then cool the MTJ film stack to a second temperature lower than the first temperature; etching away a top portion of the interface magnetic layer; and depositing at least one top layer on top of the etched interface magnetic layer. The method may further include the step of annealing the MTJ film stack at a third temperature between the first and second temperature after the step of depositing at least one top layer. | 09-04-2014 |
20140247653 | ELECTRIC FIELD ASSISTED MRAM AND METHOD FOR USING THE SAME - The present invention is directed to a spin transfer torque magnetic random access memory (STT-MRAM) device having a plurality of memory elements. Each of the plurality of memory elements comprises a magnetic reference layer with a first invariable magnetization direction substantially perpendicular to layer plane thereof; a magnetic free layer separated from the magnetic reference layer by an insulating tunnel junction layer with the magnetic free layer having a variable magnetization direction substantially perpendicular to layer plane thereof; a dielectric layer formed in contact with the magnetic free layer opposite the insulating tunnel junction layer; and a first conductive layer formed in contact with the dielectric layer opposite the magnetic free layer. | 09-04-2014 |
20140219013 | METHOD AND APPARATUS FOR READING A MAGNETIC TUNNEL JUNCTION USING A SEQUENCE OF SHORT PULSES - A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ. | 08-07-2014 |
20140210103 | MRAM with Sidewall Protection and Method of Fabrication - BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. In either the first or second embodiments a single layer or a dual layer etch stop layer structure can be deposited over the wafer after the sidewall protection sleeve has been formed and before the inter-layer dielectric (ILD) is deposited. | 07-31-2014 |
20140204662 | APPARATUS FOR INITIALIZING PERPENDICULAR MRAM DEVICE - The present invention is directed to an apparatus for initializing perpendicular magnetic tunnel junction. The apparatus comprises a permanent magnet for generating a magnetic flux; a flux concentrator made of a soft ferromagnetic material and having a base area in contact with the permanent magnet and an tip area that is smaller than the base area, thereby funneling and concentrating the magnetic flux to the tip area for emitting a magnetic field therefrom; and a means for supporting and conveying a substrate with an arrays of magnetic tunnel junctions formed therein to traverse the magnetic field in close proximity to the tip area. The apparatus may further include at least one of the following: a substrate heater, a flux containment structure coupled to the permanent magnet, and a magnetic imaging plate disposed in proximity to the substrate on the opposite side from the flux concentrator. | 07-24-2014 |
20140201432 | PERSISTENT BLOCK STORAGE ATTACHED TO MEMORY BUS - A method of configuring a computer memory system includes receiving a request from customized software driver or a BIOS extension software or a customized legacy BIOS or a customized UEFI PMM extension software or a customized UEFI BIOS, scanning memory module sockets in response to the request, recognizing memory modules in the memory module sockets, the memory modules being made of, at least in part, persistent memory modules (PMMs), configuring the PMMs to be invisible to the OS, and storing the mapping information to a designated protected persistent memory area, and presenting the PMMs as a persistent block storage to the OS. | 07-17-2014 |
20140197505 | SHIELDS FOR MAGNETIC MEMORY CHIP PACKAGES - Chip packages are described with soft-magnetic shields that are included inside or attached externally to the package containing a MRAM chip. In one group of embodiments a single shield with vias for bonding wires is affixed to the surface of the MRAM chip having the contact pads. The limitation of shield to chip distance due to bonding wire is eliminated by VIA holes according to the invention which achieves minimal spacing between the shield and chip. A second shield without vias can be positioned on the opposite side of the chip from the first shield. In one group of embodiments a hardened ferro-fluid shield can be the only shield or the structure can include a shield with or without vias. One group of embodiments includes an external shield with vias for solder access to the package contact pads affixed to the outer surface of the package. | 07-17-2014 |
20140192591 | HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states. | 07-10-2014 |
20140192590 | MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read. | 07-10-2014 |
20140185372 | MEMORY SENSING CIRCUIT - A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element. | 07-03-2014 |
20140183608 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER AND INTERFACIAL ANISOTROPIC FREE LAYER - The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto. | 07-03-2014 |
20140170776 | MTJ STACK AND BOTTOM ELECTRODE PATTERNING PROCESS WITH ION BEAM ETCHING USING A SINGLE MASK - Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step. | 06-19-2014 |
20140169083 | MAGNETORESISTIVE LAYER STRUCTURE WITH VOLTAGE-INDUCED SWITCHING AND LOGIC CELL APPLICATION - Embodiments of the invention include a voltage-switching MTJ cell structure that includes two sub-MTJs in series. Each free layer can be switched independently from the other. Each sub-MTJ has a high and a low resistance state and the MTJ cell structure can have three or four discrete resistance states. By taking advantage of the electrical field induced anisotropy combining with the spin torque effect, free layer-1 and free layer-2 can be controlled individually by voltage pulses having selected sign (polarity) and amplitude characteristics. The MTJ cell structure can be used as a fully functional logic cell with two input bit values corresponding to the high or low resistance of the two sub-MTJ structures and the output of a logical operation, e.g. an XOR function, determined by the resistance state of each MTJ cell. | 06-19-2014 |
20140169079 | METHOD AND APPARATUS FOR SENSING THE STATE OF A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of measuring the resistance of a magnetic tunnel junction (MTJ) is performed by selecting the MTJ to be measured, the MTJ having a resistance associated therewith and coupled to an access transistor. Further, measuring a voltage at an end of the MTJ that is coupled to the access transistor and measuring voltage, V0, at the coupling of the selected MTJ and the associated access transistor, turning off a decoder that is coupled to the MTJ, and after applying current, measuring the applied current and using the measured applied current to determine the resistance of the MTJ. | 06-19-2014 |
20140151827 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER - The present invention is directed to an STT-MRAM device including a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer, the first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer plane thereof, the magnetic fixed layer has a second invariable magnetization direction that is substantially perpendicular to layer plane thereof and is opposite to the first invariable magnetization direction. | 06-05-2014 |
20140143489 | CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories. | 05-22-2014 |
20140143481 | MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. | 05-22-2014 |
20140143480 | MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. | 05-22-2014 |
20140138609 | HIGH DENSITY RESISTIVE MEMORY HAVING A VERTICAL DUAL CHANNEL TRANSISTOR - Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F | 05-22-2014 |
20140082374 | MOBILE DEVICE USING SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) - A mobile device includes an application processor, an RF modem for connection to cellular networks, wireless device for connection to wireless networks, a display coupled to the application processor, audio devices coupled to the application processor, power management for providing power through a main battery; and charging the battery, a hybrid memory including a magnetic memory, the magnetic memory further including a parameter area configured to store parameters used to authenticate access to certain areas of the main memory, and a parameter memory that maintains a first area, used to store protected zone parameters, and a second area used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with access to the certain areas in the main memory that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified. | 03-20-2014 |
20140082372 | SECURE SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) - A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified. | 03-20-2014 |
20140050009 | MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read. | 02-20-2014 |
20140047166 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140047165 | Storage System Employing MRAM and Physically Addressed Solid State Disk - A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140047164 | Physically Addressed Solid State Disk Employing Magnetic Random Access Memory (MRAM) - A computer system includes a central processing unit (CPU), a system memory coupled to the CPU and including flash tables, and a physically-addressable solid state disk (SSD) coupled to the CPU. The physically-addressable SSD includes a flash subsystem and a non-volatile memory and is addressable using physical addresses. The flash subsystem includes one or more copies of the flash tables and the non-volatile memory includes updates to the copy of the flash tables. The flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressable SSD, wherein the updates to the copy of the flash tables and the one or more copies of the flash tables are used to reconstruct the flash tables upon power interruption. | 02-13-2014 |
20140047161 | System Employing MRAM and Physically Addressed Solid State Disk - A computer system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140042571 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER - The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto. | 02-13-2014 |
20140038314 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer. Cooling down the STTMRAM element to a second temperature that is lower than the first temperature and depositing a third free sub-layer directly on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 02-06-2014 |
20140035069 | FIELD EFFECT TRANSISTOR HAVING A TROUGH CHANNEL - The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure; a gate formed on top of the insulator layer in a second direction perpendicular to the first direction and extending over and into the trough structure with a gate dielectric layer interposed therebetween; a source and a drain of a second conductivity type opposite to the first conductivity type formed in the trough structure on opposite sides of the gate. | 02-06-2014 |
20140027830 | ACCESS TRANSISTOR WITH A BURIED GATE - A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells. | 01-30-2014 |
20140017818 | METHOD FOR MANUFACTURING NON-VOLATILE MAGNETIC MEMORY CELL IN TWO FACILITIES - In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured. | 01-16-2014 |
20140015078 | SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) HAVING GRADED SYNTHETIC FREE LAYER - A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer. | 01-16-2014 |
20140015076 | PERPENDICULAR STTMRAM DEVICE WITH BALANCED REFERENCE LAYER - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, which can be a single layer structure or a synthetic multi-layer structure, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A tuning layer is formed on top of the free layer and a fixed layer is formed on top of the tuning layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field. | 01-16-2014 |
20140011296 | HIGH CAPACITY LOW COST MULTI-STACKED CROSS-LINE MAGNETIC MEMORY - One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ. | 01-09-2014 |
20130339587 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible. | 12-19-2013 |
20130337582 | MRAM ETCHING PROCESSES - Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes. | 12-19-2013 |
20130329488 | METHOD OF SENSING DATA OF A MAGNETIC RANDOM ACCESS MEMORIES (MRAM) - A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state. | 12-12-2013 |
20130314982 | Method for Magnetic Screening of Arrays of Magnetic Memories - A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiments the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells. | 11-28-2013 |
20130258764 | MULTI-STATE SPIN-TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY - A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film. | 10-03-2013 |
20130250667 | METHOD OF READING FROM AND WRITING TO MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A method of writing to a magnetic memory cell that includes selecting a magnetic memory cell having a pair of MTJs, and based on whether the selected magnetic memory cell is an ‘odd’ magnetic memory cell or an ‘even’ magnetic memory cell and a state to which the selected magnetic memory cell is being written, setting a distinct bit line (BL), coupled to a first MTJ of the pair of MTJs or a second MTJ of the pair of MTJs, to a voltage level indicative of a certain state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the first or second MTJs to be in a direction opposite to that of the other one of the first or second MTJs to program the first and second MTJs in opposite states. | 09-26-2013 |
20130229866 | SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) USING A SYNTHETIC FREE LAYER - A spin-torque transfer memory random access memory (STTMRAM) element, employed in a STTMRAM array, receives electric current for storage of digital information, the STTMRAM element has a magnetic tunnel junction (MTJ). The MTJ includes an anti-ferromagnetic (AF) layer, a fixed layer having a magnetization that is substantially fixed in one direction and that comprises a first magnetic layer, an AF coupling layer and a second magnetic layer, a barrier layer formed upon the fixed layer, and a free layer. The free layer is synthetic and has a high-polarization magnetic layer, a low-crystallization magnetic layer, a non-magnetic separation layer, and a magnetic layer, wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer. | 09-05-2013 |
20130223141 | MAGENTIC MEMORY WITH A DOMAIN WALL - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall. | 08-29-2013 |
20130215673 | MAGNETORESISTIVE LOGIC CELL AND METHOD OF USE - A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments. | 08-22-2013 |
20130149797 | Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement - A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer. | 06-13-2013 |
20130119498 | MEMORY SYSTEM HAVING THERMALLY STABLE PERPENDICULAR MAGNETO TUNNEL JUNCTION (MTJ) AND A METHOD OF MANUFACTURING SAME - A spin-torque transfer magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of a seed layer. The STTMRAM element further includes a barrier layer formed on top of the first PFL and a second perpendicular reference layer (PRL) that has a second PEL, the second PRL is formed on top of the barrier layer. The STTMRAM element further includes a capping layer that is formed on top of the second PRL. | 05-16-2013 |
20130114335 | MEMORY SENSING CIRCUIT - A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element. | 05-09-2013 |
20130107615 | MEMORY SENSING CIRCUIT | 05-02-2013 |
20130107614 | MEMORY SENSING CIRCUIT | 05-02-2013 |
20130107613 | MEMORY SENSING CIRCUIT | 05-02-2013 |
20130107612 | Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Device with Shared Transistor and Minimal Written Data Disturbance | 05-02-2013 |
20130088915 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 04-11-2013 |
20130088914 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 04-11-2013 |
20130087872 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 04-11-2013 |
20130087871 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 04-11-2013 |
20130087870 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 04-11-2013 |
20130087869 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 04-11-2013 |
20130080687 | SOLID STATE DISK EMPLOYING FLASH AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A central processing unit (CPU) subsystem is disclosed to include a MRAM used among other things for storing tables used for flash block management. In one embodiment all flash management tables are in MRAM and in an alternate embodiment tables are maintained in DRAM and are near periodically saved in flash and the parts of the tables that are updated since last save are additionally maintained in MRAM. | 03-28-2013 |
20130075840 | METHOD FOR FABRICATION OF A MAGNETIC RANDOM ACCESS MEMORY (MRAM) USING A HIGH SELECTIVITY HARD MASK - A self-aligned via of a MRAM cell that connects a memory element including a top electrode, a memory element stack having a plurality of layers, and a bottom electrode to a bit line running over array of the memory elements. The self-aligned via also serves as a hard mask for memory element etching. The hard mask material has high selectivity in the etching ambient to maintain enough remaining thickness. It is also selectively removed during dual damascene process to form a self-aligned via hole. In one embodiment, Aluminum oxide or Magnesium oxide is adapted as the hard mask. | 03-28-2013 |
20130073926 | MEMORY WITH ON-CHIP ERROR CORRECTION - A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword. | 03-21-2013 |
20130073791 | MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE - A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data. | 03-21-2013 |
20130073790 | MAGNETIC RANDOM ACCESS MEMORY WITH BURST ACCESS - A memory device which includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable write of the data units of the burst of data, the memory device allowing a next burst write or read command to begin before the completion of the burst write operation and while receiving data units of the next burst of data to be written or providing read data. | 03-21-2013 |
20130071954 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 03-21-2013 |
20130021842 | INITIALIZATION METHOD OF A PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE WITH A STABLE REFERENCE CELL - A method of initializing a magnetic random access memory (MRAM) element that is configured to store a state when electric current flows therethrough is disclosed. The MRAM element includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. Each MTJ further includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ for storing reference bit. | 01-24-2013 |
20130021841 | PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE WITH A STABLE REFERENCE CELL - A magnetic random access memory (MRAM) element is configured to store a state when electric current flows and includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ. Further, the MTJ includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ. | 01-24-2013 |
20130017627 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 01-17-2013 |
20130016554 | METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor. | 01-17-2013 |
20130007544 | MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE - A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location. | 01-03-2013 |
20120306033 | VIALESS MEMORY STRUCTURE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a magnetic memory cell, including a magnetic tunnel junction (MTJ), includes using silicon nitride layer and silicon oxide layer to form a trench for depositing copper to be employed for connecting the MTJ to other circuitry without the use of a via. | 12-06-2012 |
20120295370 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A STTMRAM element has a free sub-layer with enhanced internal stiffness. A first free sub-layer is made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, with an amount greater than the amount of B in the first free sub-layer. The STTMRAM element is cooled to a second temperature that is lower than the first temperature and a third free sub-layer is deposited directly on top of the second free layer, with the third free sub-layer being made partially of boron B. The amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 11-22-2012 |
20120282711 | MAGNETIC TUNNEL JUNCTION (MTJ) FORMATION USING MULTIPLE ETCHING PROCESSES - A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting. | 11-08-2012 |
20120280339 | PERPENDICULAR MAGNETIC TUNNEL JUNCTION (pMTJ) WITH IN-PLANE MAGNETO-STATIC SWITCHING-ENHANCING LAYER - A STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current. | 11-08-2012 |
20120275219 | Shared Transistor in a Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Cell - A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ. | 11-01-2012 |
20120264234 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 10-18-2012 |
20120241826 | ACCESS TRANSISTOR WITH A BURIED GATE - A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells. | 09-27-2012 |
20120230101 | METHOD AND APPARATUS FOR WRITING TO A MAGNETIC TUNNEL JUNCTION (MTJ) BY APPLYING INCREMENTALLY INCREASING VOLTAGE LEVEL - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ. | 09-13-2012 |
20120230095 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 09-13-2012 |
20120217595 | MAGNETIC LATCH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer. | 08-30-2012 |
20120212998 | Non-Volatile Perpendicular Magnetic Memory with Low Switching Current and High Thermal Stability - A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer with a perpendicular anisotropy that is formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer, and a top electrode formed on top of the cap layer. | 08-23-2012 |
20120206958 | MAGNETIC RANDOM ACCESS MEMORY WITH FIELD COMPENSATING LAYER AND MULTI-LEVEL CELL - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field. | 08-16-2012 |
20120205763 | NON-VOLATILE MAGNETIC MEMORY WITH LOW SWITCHING CURRENT AND HIGH THERMAL STABILITY - A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer. | 08-16-2012 |
20120205761 | Non-Volatile Magnetic Memory with Low Switching Current and High Thermal Stability - A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer. | 08-16-2012 |
20120205760 | MAGNETIC RANDOM ACCESS MEMORY WITH FIELD COMPENSATING LAYER AND MULTI-LEVEL CELL - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field. | 08-16-2012 |
20120188818 | Low-crystallization temperature MTJ for Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) - A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer. | 07-26-2012 |
20120182795 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 07-19-2012 |
20120170361 | LOW-COST NON-VOLATILE FLASH-RAM MEMORY - A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs. | 07-05-2012 |
20120148735 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer. Cooling down the STTMRAM element to a second temperature that is lower than the first temperature and depositing a third free sub-layer directly on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 06-14-2012 |
20120107964 | LOW-COST NON-VOLATILE FLASH-RAM MEMORY - A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs. | 05-03-2012 |
20120087185 | MAGNETIC LATCH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A spin-transfer torque magnetic random access memory (STTMRAM) element is configured to store a state when electrical current is applied thereto. The STTMRAM element includes first and second free layers, each of which having an associated direction of magnetization defining the state of the STTMRAM element. Prior to the application of electrical current to the STTMRAM element, the direction of the magnetization of the first and second free layers each is in-plane and after the application of electrical current to the STTMRAM element, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer. | 04-12-2012 |
20120069649 | NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current. | 03-22-2012 |
20120069643 | NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current. | 03-22-2012 |
20120068236 | NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current. | 03-22-2012 |
20120063218 | SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR MAGNETIC ANISOTROPY MULTILAYERS - A spin-torque transfer memory random access memory (STTMRAM) element includes a composite fixed layer formed on top of a substrate and a tunnel layer formed upon the fixed layer and a composite free layer formed upon the tunnel barrier layer, the magnetization direction of each of the composite free layer and fixed layer being substantially perpendicular to the plane of the substrate. The composite layers are made of multiple repeats of a bi-layer unit which consists of a non-magnetic insulating layer and magnetic layer with thicknesses adjusted in a range that makes the magnetization have a preferred direction perpendicular to film plane. | 03-15-2012 |
20120026785 | Non-Volatile Magnetic Memory Element with Graded Layer - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 02-02-2012 |
20120025338 | Non-Volatile Magnetic Memory Element with Graded Layer - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 02-02-2012 |
20120018823 | SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) HAVING GRADED SYNTHETIC FREE LAYER - A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a non-magnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer. | 01-26-2012 |
20120003757 | HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states. | 01-05-2012 |
20120002463 | HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states. | 01-05-2012 |
20110305078 | LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer. | 12-15-2011 |
20110303998 | LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer. | 12-15-2011 |
20110249491 | METHOD AND APPARATUS FOR PROGRAMMING A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ. | 10-13-2011 |
20110103143 | LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall. | 05-05-2011 |
20110096593 | LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall. | 04-28-2011 |
20110089511 | Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement - A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer. | 04-21-2011 |
20100315870 | METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor. | 12-16-2010 |
20100240152 | Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) for Magnetic Random Access Memory (MRAM) - One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element. | 09-23-2010 |
20100221848 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 09-02-2010 |