INTEL CORPORATION Patent applications |
Patent application number | Title | Published |
20160143059 | SYSTEMS, APPARATUSES, AND METHODS FOR PROCESSING RANDOM ACCCESS RESPONSE MESSAGES FOR COVERAGE CONSTRAINED DEVICES - Disclosed herein are methods, apparatuses, and systems for establishing lightweight communications between different network components. A messaging process is utilized which includes a random access procedure for a user equipment (UE) and an eNodeB, and a messaging sequence comprising a reduced number of messages (compared to a legacy Radio Resource Control (RRC) Connection messaging sequence) exchanged between different nodes of the network to establish a lightweight connection. These messages can be generated using any combination of pre-configured or pre-determined data specific to either the UE or to lightweight communications. | 05-19-2016 |
20160142816 | AUTHENTICATION THROUGH TISSUE-CONDUCTED SOUND - Systems and methods may provide for sending a sound wave signal and measuring a body conduction characteristic of the sound wave signal. Additionally, a user authentication may be performed based at least in part on the body conduction characteristic. In one example, the body conduction characteristic includes one or more of a timing, a frequency or an amplitude of the sound wave signal after passing through one or more of bone or tissue. | 05-19-2016 |
20160142687 | MEMS OSCILLATOR - A device comprising, a mirror which is configured to oscillate in response to an oscillation signal, wherein the device is configured such that oscillation of the mirror will induce a signal; and a circuit in operable cooperation with the mirror such that an induced signal can be measured by the circuit and wherein the circuit is configured to provide an oscillation signal proportional to the measured induced signal; wherein the device is configured such that the mirror can receive the oscillation signal so that the oscillation signal is filtered due to oscillation limitations of mirror, to provide a filtered signal. | 05-19-2016 |
20160142673 | SYSTEM FOR ENABLING EYE CONTACT IN ELECTRONIC IMAGES - Techniques are disclosed for improving perceived eye-contact in video communications on personal communication devices that have a camera positioned offset slightly away from a display screen, such as found in tablets, mobile phones, laptops, desktops ultrabooks, all-in-ones, and the like. A three-dimensional mesh, such as a point cloud, may be created from an image and depth information that is captured of the user. A viewing direction of is determined by assessing the three-dimensional mesh and the mesh is rotated to minimize the angle between the viewing direction and a line of sight between the user's eyes and the camera. | 05-19-2016 |
20160142212 | TRUSTED PLATFORM MODULE CERTIFICATION AND ATTESTATION UTILIZING AN ANONYMOUS KEY SYSTEM - This application is directed to trusted platform module certification and attestation utilizing an anonymous key system. In general, TPM certification and TPM attestation may be supported in a device utilizing integrated TPM through the use of anonymous key system (AKS) certification. An example device may comprise at least combined AKS and TPM resources that load AKS and TPM firmware (FW) into a runtime environment that may further include at least an operating system (OS) encryption module, an AKS service module and a TPM Certification and Attestation (CA) module. For TPM certification, the CA module may interact with the other modules in the runtime environment to generate a TPM certificate, signed by an AKS certificate, that may be transmitted to a certification platform for validation. For TPM attestation, the CA module may cause TPM credentials to be provided to the attestation platform for validation along with the TPM and/or AKS certificates. | 05-19-2016 |
20160141831 | HEAT REMOVAL FROM PHOTONIC DEVICES - Embodiments of the present description relate to mechanisms for transferring heat through a microelectronic substrate from a photonic device to a heat dissipation device. In one embodiment, the microelectronic substrate may comprise a highly thermally conductive dielectric material. In another embodiment, the microelectronic substrate may comprise a conductive insert within the microelectronic substrate wherein the photonic device is in thermal contact with the conductive insert proximate one surface of the microelectronic substrate and the heat dissipation device is thermal contact with the conductive insert proximate an opposing surface of the microelectronic substrate. In still another embodiment, a stepped heat spreader, having a base portion and a pedestal portion, has the pedestal portion inserted through the microelectronic substrate, wherein the photonic device is in thermal contact with the pedestal portion proximate one surface of the microelectronic substrate and the heat dissipation device is thermal contact with the base portion. | 05-19-2016 |
20160141829 | LASER SUPPORT FOR SEMICONDUCTOR LASER FIXATION AND LASER SUPPORT ELEMENT ASSEMBLY - Method for mounting a semiconductor laser element ( | 05-19-2016 |
20160140686 | EFFICIENT PREEMPTION FOR GRAPHICS PROCESSORS - Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit. | 05-19-2016 |
20160140684 | SORT-FREE THREADING MODEL FOR A MULTI-THREADED GRAPHICS PIPELINE - Methods and apparatus relating to sort-free threading model for a multi-threaded graphics pipeline are described. In an embodiment, draw requests, corresponding to one or more primitives in an image, are stored in entries of a queue (e.g., in the order received). Each entry remains locked until both a front-end and a back-end of a graphics pipeline have completed one or more operations associated with the draw request. Other embodiments are also disclosed and claimed. | 05-19-2016 |
20160140364 | SECURE CONTROL OF SELF-ENCRYPTING STORAGE DEVICES - Generally, this disclosure provides systems, devices, methods and computer readable media for secure control of access control enablement and activation on self-encrypting storage devices. In some embodiments, the device may include a non-volatile memory (NVM) and a secure access control module. The secure access control module may include a command processor module configured to receive a request to enable access controls of the NVM from a user, and to enable the access controls. The secure access control module may also include a verification module configured to verify a physical presence of the user. The secure access control module may further include an encryption module to encrypt at least a portion of the NVM in response to an indication of success from the verification module. | 05-19-2016 |
20160139936 | Method and apparatus for multi-mode mobile computing devices and peripherals - Embodiments of a method and apparatus are described for operating a mobile computing device in different modes using different operating systems. An apparatus may comprise, for example, a memory operative to store multiple operating systems, a processor operative to execute the multiple operating systems, an operating system management module operative to select a first operating system when the mobile computing device is in a first mode or a second operating system when the mobile computing device is in a second mode and the mobile computing device is coupled to one or more external devices. Other embodiments are described and claimed. | 05-19-2016 |
20160139934 | HARDWARE INSTRUCTION SET TO REPLACE A PLURALITY OF ATOMIC OPERATIONS WITH A SINGLE ATOMIC OPERATION - Systems and methods may process a single atomic operation. An instruction set may be generated to replace a plurality of atomic operations with a single atomic operation. The instruction set may include an accumulation instruction to compute a prefix sum for a plurality of initial values associated with a plurality of processing lanes to generate a plurality of accumulated values. The instruction set may also include a broadcast instruction to return a pre-existing value to be added with each of the plurality of accumulated values to generate a plurality of intermediate accumulated values. In one example, a graphics processor may execute the instruction set to process the single atomic operation. | 05-19-2016 |
20160139931 | MORTON COORDINATE ADJUSTMENT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A processor includes a decode unit to decode an instruction that is to indicate a source packed data operand to include Morton coordinates, a dimensionality of a multi-dimensional space having points that the Morton coordinates are to be mapped to, a given dimension of the multi-dimensional space, and a destination. The execution unit is coupled with the decode unit. The execution unit, in response to the decode unit decoding the instruction, stores a result packed data operand in the destination. The result operand is to include Morton coordinates that are each to correspond to a different one of the Morton coordinates of the source operand. The Morton coordinates of the result operand are to be mapped to points in the multi-dimensional space that differ from the points that the corresponding Morton coordinates of the source operand are to be mapped to by a fixed change in the given dimension. | 05-19-2016 |
20160139930 | FOUR-DIMENSIONAL MORTON COORDINATE CONVERSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A processor includes packed data registers, a decode unit, and an execution unit. The decode unit is to decode a four-dimensional (4D) Morton coordinate conversion instruction. The 4D Morton coordinate conversion instruction is to indicate a source packed data operand that is to include a plurality of 4D Morton coordinates, and is to indicate one or more destination storage locations. The execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the decode unit decoding the 4D Morton coordinate conversion instruction, is to store one or more result packed data operands in the one or more destination storage locations. The one or more result packed data operands are to include a plurality of sets of four 4D coordinates. Each of the sets of the four 4D coordinates is to correspond to a different one of the 4D Morton coordinates. | 05-19-2016 |
20160139929 | THREE-DIMENSIONAL MORTON COORDINATE CONVERSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A processor includes a plurality of packed data registers, a decode unit, and an execution unit. The decode unit is to decode a three-dimensional (3D) Morton coordinate conversion instruction. The 3D Morton coordinate conversion instruction to indicate a source packed data operand that is to include a plurality of 3D Morton coordinates, and to indicate one or more destination storage locations. The execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the decode unit decoding the 3D Morton coordinate conversion instruction, is to store one or more result packed data operands in the one or more destination storage locations. The one or more result packed data operands are to include a plurality of sets of three 3D coordinates. Each of the sets of the three 3D coordinates is to correspond to a different one of the 3D Morton coordinates. | 05-19-2016 |
20160139658 | SUPPORTING RUNTIME D3 AND BUFFER FLUSH AND FILL FOR A PERIPHERAL COMPONENT INTERCONNECT DEVICE - Particular embodiments described herein provide for an apparatus that includes a means for determining a power state for a device connected to a system, a means for determining that the device should change power states, and means for sending a signal to the device to put the device in a D3-cold state while the system is a G0/S0 state. In an embodiment, the device is a peripheral component interconnect (PCI) device. Also, the particular example implementation can include means for sending a PCIRST# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the PCIRST# signal is received at a pin on the controller that is different than a designated PCIRST# signal pin. | 05-19-2016 |
20160135698 | ULTRA-LOW POWER CONTINUOUS HEART RATE SENSING IN WEARABLE DEVICES - Systems and methods may provide for a piezoelectric film that generates an excitation signal in response to pressure variations on a surface of the piezoelectric film and an analog front end coupled to the piezoelectric film, wherein the analog front end generates a first measurement signal based on the excitation signal. Additionally, a heart rate monitor may be coupled to the analog front end, wherein the heart rate monitor generates a heart rate measurement based on the first measurement signal. In one example, the analog front end includes a single stage amplifier. | 05-19-2016 |
20160134863 | CALIBRATION FOR EYE TRACKING SYSTEMS - Generally, this disclosure provides systems, devices, methods and computer readable media for calibration of an eye tracking system. In some embodiments, the method may include analyzing a video stream received from a scene facing camera to detect moving objects and estimate angular locations of the moving objects. The method may also include receiving images from an eye tracking camera and estimating gaze angles of a user's eye, based on the images. The method may further include computing, for each of the moving objects, a first distance measure between the object angular locations and the gaze angles; accepting or rejecting each of the moving objects for use in calibration based on a comparison of the first distance measure to a threshold; and estimating an eye tracking calibration angle based on a minimization of a second distance measure computed between the angular locations of the accepted moving objects and the gaze angles. | 05-12-2016 |
20160134803 | PRODUCTION OF FACE IMAGES HAVING PREFERRED PERSPECTIVE ANGLES - Techniques are disclosed for identifying preferred orientations of a face in view of various preference factors and for producing a face image having a preferred orientation. The techniques allow a user to take a so-called selfie or have a video chat and appear as if he/she is looking into the camera with a face orientation that has been determined to be optimal for various factors. Such factors may be associated with face type (e.g., face shape, face color), image capture conditions (e.g., time of day, location, light condition, background), and/or the preferences of a particular user. The factors may also be directly associated with and/or dependent on face orientation (e.g., relative nostril size, facial symmetry, relative eye size, eye height). | 05-12-2016 |
20160134627 | SYSTEM FOR ESTABLISHING OWNERSHIP OF A SECURE WORKSPACE - The present application is directed to establishing ownership of a secure workspace (SW). A client device may provide a SW data structure (SWDS) to a SW configurator. A SWDS may comprise a hash of an original SW and a public key, and may be signed by a private key corresponding to the public key. The SW configurator may cause an execution container (EC) to be generated including a SW initiated using the SWDS. The client device may claim SW ownership using a request (signed by the private key) transmitted along with a copy of the public key. SW ownership may be determined by an ownership determination module that verifies the signature of the request using the public key received with the request, determines a hash of the received public key and compares the hash of the received public key to a hash of the public key in the SWDS. | 05-12-2016 |
20160134609 | USER AUTHENTICATION CONFIDENCE BASED ON MULTIPLE DEVICES - The present application is directed to user authentication confidence based on multiple devices. A user may possess at least one device. The device may determine a device confidence level that the identity of the user is authentic based on at least data collected by a data collection module in the device. For example, a confidence module in the device may receive the data from the data collection module, determine a quality corresponding to the data and determine the device confidence level based on the quality. If the user possesses two or more devices, at least one of the devices may collect device confidence levels from other devices to determine a total confidence level. For example, a device may authenticate the other devices and then receive device confidence levels for use in determining the total confidence level, which may be used to set an operational mode in a device or system. | 05-12-2016 |
20160134602 | SECURE SHARING OF USER ANNOTATED SUBSCRIPTION MEDIA WITH TRUSTED DEVICES - Generally, this disclosure provides systems, methods and computer readable media for secure sharing of user annotated subscription media content with trusted devices. The shared content may include user specified snapshots of the media along with user supplied annotations. The system may include a host processor configured to arrange a secure session with a server and to receive the subscription media content from the server in an encrypted format. The system may also include a trusted execution environment (TEE) comprising a secure processor and secure storage configured to decrypt and store the media content, based on a content encryption key obtained from the server. The system may further be configured to: receive a snapshot frame request and annotations from the user; generate a composite image of the snapshot and an overlay including the annotations; and encrypt the composite image for sharing with other users. | 05-12-2016 |
20160134456 | SYSTEMS FOR COMMUNICATING USING MULTIPLE FREQUENCY BANDS IN A WIRELESS NETWORK - Communication signals using a first and a second frequency band in a wireless network is described herein. The first frequency band may be associated with a first beamwidth while the second frequency band may be associated with a second beamwidth. An apparatus may include receiver circuitry arranged to receive first signals in a first frequency band associated with a first beamwidth and second signals in a second frequency band associated with a second beamwidth, the first signals comprising a frame synchronization parameter and the second signals comprising frame alignment signals. The apparatus may further include processor circuitry coupled to the receiver circuitry, the processor circuitry arranged to activate or deactivate the receiver circuitry to receive the frame alignment signals based on the frame synchronization parameter. Other embodiments may be described and/or claimed. | 05-12-2016 |
20160134149 | WIRELESS CHARGING UNIT AND COUPLER BASED DOCKING COMBO FOR A WIRELESS DEVICE - Described herein are techniques related to one or more systems, apparatuses, methods, etc. for implementing a wireless charging and a wireless connectivity combo in a device. | 05-12-2016 |
20160133596 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 05-12-2016 |
20160133557 | OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES - An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads. | 05-12-2016 |
20160132666 | System And Method For Relicensing Content - A method, computer program product and system for indicating the occurrence of a relicensing trigger event on a client electronic device includes generating a license request for the client electronic device. An expiration indicator is received for a subscription associated with the client electronic device. A device license is created for the client electronic device that includes the license request and the expiration indicator. A secure device license is created by digitally-securing the device license. | 05-12-2016 |
20160132217 | PRESENTATION OF METADATA AND ENHANCED ENTERTAINMENT MEDIA CONTENT - Techniques are disclosed that involve providing enhanced user experiences involving the consumption and management of content. For instance, embodiments provide user interface elements that present information regarding content that overcomes barriers or silos between application and platforms. Examples of such user interface elements include a three dimensional carousel, a preview stack, a favorites button, and a My Channel user interface. Also, embodiments may provide techniques for obtaining contextual content. Such techniques include, but are not limited to, zooming mechanisms and combining (or “mashup”) mechanisms. | 05-12-2016 |
20160132083 | Adaptive graphics subsystem power and performance management - Examples are disclosed for adaptive graphics subsystem power and performance management including adjusting one or more power management or performance attributes for a graphics subsystem for a computing platform based on a comparison of a current quality metric to a target quality metric. The current and target quality metric to be separately determined based on current and target quality of service (QoS) values for power management and performance for at least portions of the computing platform. | 05-12-2016 |
20160127602 | Managing consistent data objects - A method and system for managing consistent data objects are included herein. The method includes detecting an operation to store a consistent data object. Additionally, the method includes detecting an attribute for the consistent data object. Furthermore, the method includes storing the consistent data object based on the attribute. In addition, the method includes determining an additional format of the consistent data object is to be stored. The method also includes generating a second consistent data object based on the additional format and storing the second consistent data object. | 05-05-2016 |
20160127568 | OPERATIONS METHOD FOR PROVIDING WIRELESS COMMUNICATION SERVICES - The present invention is directed to an improved operations method for a wireless communication system. The improved business method, operations method, network and system of the present invention includes the steps of delivering cellular services to the mass market, reducing peak capacity, increasing overall capacity utilization, improving capital utilization, providing an “all-you-can-eat” pricing model, and designing capacity based upon where the users live, work, and play. | 05-05-2016 |
20160127054 | PROXIMATE COMMUNICATION WITH A TARGET DEVICE - Systems and methods may use proximate communication to retrieve information pertaining to a target device. In one example, the method may include detecting the target device within a vicinity of a user device, receiving an information request response communication including information pertaining to the target device, and receiving an operation request response communication including information pertaining to a performed operation. | 05-05-2016 |
20160126730 | CURRENT SENSE TECHNIQUES IN A POWER SUPPLY SYSTEM - Generally, this disclosure describes a system for sensing current in a power supply system. The apparatus includes controller circuitry to select a first power supply of a plurality of power supplies, determine a reference output voltage (Voutr) associated with a reference supply based, at least in part, on a duty cycle (D) and an input voltage (Vin), D and Vin related to the first power supply. The controller circuitry is further to determine an output voltage (Voutx) associated with the first power supply, determine an effective resistance (Reffx) associated with the first power supply based, at least in part, on a present temperature, and determine an output current (Ioutx) associated with the first power supply based, at least in part, on Voutr, Voutx and Reffx. | 05-05-2016 |
20160126452 | BALANCING ENERGY BARRIER BETWEEN STATES IN PERPENDICULAR MAGNETIC TUNNEL JUNCTIONS - Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer. | 05-05-2016 |
20160126311 | STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT - A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same. | 05-05-2016 |
20160125841 | DEVICE, SYSTEM, AND METHOD OF DISPLAY CALIBRATION - Device, system, and method for display calibration. For example, an apparatus includes: one or more color sensors, embedded within a body of a mobile device, to measure one or more color attributes of a visual element displayed by a display unit of the mobile device when a lid of the mobile device is in a closed position; and a color calibrator to calibrate one or more parameters of the display unit based on the one or more color attributes measured by the one or more color sensors. | 05-05-2016 |
20160125720 | SYSTEM FOR DETERMINING SENSOR CONDITION - The present disclosure is directed to a system for determining sensor condition. A sensor signal generated by a sensor to communicate the current condition of an aspect being monitored by the sensor may also be employed to determine the condition of the sensor itself. For example, a device capable of determining if the sensor condition is normal or malfunctioning (e.g., erratic, stuck, etc.) may comprise a monitoring module (MM) to receive the sensor signal. The MM may comprise a sensor condition determination module (SCDM) to determine sensor condition. The SCDM may include a feature extraction engine to determine various characteristics of (e.g., to “extract features” from) the sensor signal and a model to determine sensor condition based on the extracted features. The model may include a support vector machine (SVM) taught to determine sensor condition utilizing sampled sensor signals correlated with annotations of sensor condition. | 05-05-2016 |
20160124766 | COOPERATED INTERRUPT MODERATION FOR A VIRTUALIZATION ENVIRONMENT - Generally, this disclosure describes systems (and methods) of moderating interrupts in a virtualization environment. An overflow interval is defined. The overflow interrupt interval is used to trigger activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment. | 05-05-2016 |
20160124751 | ACCESS ISOLATION FOR MULTI-OPERATING SYSTEM DEVICES - The present application is directed to access isolation for multi-operating system devices. In general, a device may be configured using firmware to accommodate more than one operating system (OS) operating concurrently on the device or to transition from one OS to another. An access isolation module (AIM) in the firmware may determine a device equipment configuration and may partition the equipment for use by multiple operating systems. The AIM may disable OS-based equipment sensing and may allocate at least a portion of the equipment to each OS using customized tables. When transitioning between operating systems, the AIM may help to ensure that information from one OS is not accessible to others. For example, the AIM may detect when a foreground OS is to be replaced by a background OS, and may protect (e.g., lockout or encrypt) the files of the foreground OS prior to the background OS becoming active. | 05-05-2016 |
20160124749 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 05-05-2016 |
20160124571 | MOBILE DEVICE REJECTION OF UNINTENTIONAL TOUCH SENSOR CONTACT - Mobile device rejection of unintentional sensor contact. An embodiment of a mobile device includes a first touch sensor to detect contact by a user of the mobile device for input of gestures by the user, a memory to store indicators of unintentional contact to the first touch sensor, and a processor to evaluate contact to the first touch sensor. The processor compares a contact with the first touch sensor to the indicators of unintentional contact to determine if the contact is unintentional, and the mobile device rejects the contact as an input to the mobile device if the contact is determined to be unintentional and accepts the contact as an input to the mobile device if the contact is determined to be intentional. | 05-05-2016 |
20160124515 | INTERACTION WITH A COMPUTING DEVICE VIA MOVEMENT OF A PORTION OF A USER INTERFACE - Computing devices, computer-readable storage media, and methods associated with human computer interaction. In embodiments, a computing device may include a display, a processor coupled with the display, a user interface engine and one or more applications to be operated on the processor. In embodiments, the user interface engine or the one or more applications may be configured to detect movement of the portable computing device indicating a direction a user of the portable computing device would like a portion of the user interface to move and cause the portion of the user interface to be moved, from a current location on the display to another location on the display, in accordance with the indicated direction. Such movement may facilitate the user to interact with the portion of the user interface via the interaction zone of the display. Other embodiments may be described and/or claimed. | 05-05-2016 |
20160119131 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119130 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119129 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119128 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119127 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119126 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119125 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119124 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119123 | FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. | 04-28-2016 |
20160119122 | ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) - A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass. | 04-28-2016 |
20160119042 | FEEDBACK SCHEME FOR MU-MIMO - Embodiments of a system and method for managing feedback in a MU-MIMO system. An access point can announce one or more of mobile stations that are to receive downlink information in a first frame. The access point can also send a sounding package to the one or more mobile stations and receive feedback from the one or more mobile stations according to the feedback schedule. The feedback may be based on the reception of the sounding package. | 04-28-2016 |
20160118464 | APPARATUS AND METHODS FOR FORMING A MODULATION DOPED NON-PLANAR TRANSISTOR - Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap. | 04-28-2016 |
20160118384 | SELF-ALIGNED CONTACT METALLIZATION FOR REDUCED CONTACT RESISTANCE - Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures. | 04-28-2016 |
20160118354 | MICROELECTRONIC PACKAGE UTILIZING MULTIPLE BUMPLESS BUILD-UP STRUCTURES AND THROUGH-SILICON VIAS - A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes. | 04-28-2016 |
20160117269 | SYSTEM AND METHOD FOR PROVIDING UNIVERSAL SERIAL BUS LINK POWER MANAGEMENT POLICIES IN A PROCESSOR ENVIRONMENT - One particular example implementation may include an apparatus that includes logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state; assign a first latency value to the first device; identify at least one user detectable artifact when a second device exits the selective suspend state; and assign, to the second device, a second latency value that is different from the first value. | 04-28-2016 |
20160117190 | Virtual Processor Direct Interrupt Delivery Mechanism - A method comprising is described. The method includes receiving an interrupt targeting a virtual processor, determining a status of the virtual processor and directly delivering the interrupt to the virtual processor upon determining that the virtual processor is operating in a running state. | 04-28-2016 |
20160117171 | REAL TIME INSTRUCTION TRACE PROCESSORS, METHODS, AND SYSTEMS - A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed. | 04-28-2016 |
20160116959 | DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR FASTER BOOT TIME - Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed. | 04-28-2016 |
20160116647 | ANTI-MOIRE PATTERN DIFFUSER FOR OPTICAL SYSTEMS - Disclosed herein are devices and techniques related to optical diffusers and particularly, diffusers to reduce moire patterns in a projected image. The device may comprise an array of micro-focal elements or reflectors and a light polarization grid. The light polarization grid configured to change a polarization between portions of a light beam and the micro-focal elements of reflectors to diffuse the light beam such that portions of the light beam having a difference in polarization may meet at a point. | 04-28-2016 |
20160112707 | POLICY-BASED IMAGE ENCODING - Techniques for image rendering are described herein. The techniques may include providing image data to an encoder for transmission to a display. An indication of whether at least a portion of the image data is video data or non-video data is provided. A first policy may be implemented for image data that is video data. The first policy prioritizes transmission of the image data over encoding image quality. A second policy may be implemented for image data that is non-video data. The second policy prioritizes encoded image quality over transmission of the encoded images. | 04-21-2016 |
20160112089 | ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING-CODE DIVISION MULTIPLE ACCESS SYSTEM - An orthogonal frequency division multiplexing (OFDM)-code division multiple access (CDMA) system is disclosed. The system includes a transmitter and a receiver. At the transmitter, a spreading and subcarrier mapping unit spreads an input data symbol with a complex quadratic sequence code to generate a plurality of chips and maps each chip to one of a plurality of subcarriers. An inverse discrete Fourier transform is performed on the chips mapped to the subcarriers and a cyclic prefix (CP) is inserted to an OFDM frame. A parallel-to-serial converter converts the time-domain data into a serial data stream for transmission. At the receiver, a serial-to-parallel converter converts received data into multiple received data streams and the CP is removed from the received data. A discrete Fourier transform is performed on the received data streams and equalization is performed. A despreader despreads an output of the equalizer to recover the transmitted data. | 04-21-2016 |
20160111532 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure. | 04-21-2016 |
20160111062 | AMBIENT LIGHT-BASED IMAGE ADJUSTMENT - Techniques for image rendering are described herein. The techniques may include receiving image data comprising a captured image and ambient light data indicating a level and color of ambient light present during capture of the image. The techniques may also include detecting ambient light of an environment in which the captured image is to be displayed, and adjusting spectral content of the captured image based on the detected ambient light and the ambient light present during capture of the captured image. | 04-21-2016 |
20160110546 | COMPUTING DEVICE BOOT SOFTWARE AUTHENTICATION - Various embodiments are generally directed to authenticating a chain of components of boot software of a computing device. An apparatus comprises a processor circuit and storage storing an initial boot software component comprising instructions operative on the processor circuit to select a first set of boot software components of multiple sets of boot software components, each set of boot software components defines a pathway that branches from the initial boot software component and that rejoins at a latter boot software component; authenticate a first boot software component of the first set of boot software components; and execute a sequence of instructions of the first boot software component to authenticate a second boot software component of the first set of boot software components to form a chain of authentication through a first pathway defined by the first set of boot software components. Other embodiments are described and claimed herein. | 04-21-2016 |
20160110540 | INTERFACE BETWEEN A DEVICE AND A SECURE PROCESSING ENVIRONMENT - Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a processor, a device, and an interface plug-in. The processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to create a secure processing environment. The execution unit is to execute an application in the secure processing environment. The device is to execute a workload for the application. The interface plug-in is to provide an interface for the device to enter the secure processing environment to execute the workload. | 04-21-2016 |
20160110309 | DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR FASTER BOOT TIME - Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed. | 04-21-2016 |
20160110223 | MULTI-THREADED QUEUING SYSTEM FOR PATTERN MATCHING - A multi-threaded processor may support efficient pattern matching techniques. An input data buffer may be provided, which may be shared between a fast path and a slow path. The processor may retire the data units in the input data buffer that is not required and thus avoids copying the data unit used by the slow path. The data management and the execution efficiency may be enhanced as multiple threads may be created to verify potential pattern matches in the input data stream. Also, the threads, which may stall may exit the execution units allowing other threads to run. Further, the problem of state explosion may be avoided by allowing the creation of parallel threads, using the fork instruction, in the slow path. | 04-21-2016 |
20160110205 | BOOTING AN OPERATING SYSTEM OF A SYSTEM USING A READ AHEAD TECHNIQUE - In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed. | 04-21-2016 |
20160110204 | BOOTING AN OPERATING SYSTEM OF A SYSTEM USING A READ AHEAD TECHNIQUE - In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed. | 04-21-2016 |
20160110196 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-21-2016 |
20160110106 | MULTI-LEVEL MEMORY WITH DIRECT ACCESS - Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage. | 04-21-2016 |
20160105851 | WIRELESS WAKE-UP DEVICE FOR CELLULAR MODULE - A control device may wake-up a target wireless device through a wired or wireless communications channel. In an implementation, the control device and the wireless device may include a cellular module (e.g., global systems for mobile communications (GSM) capability) to implement an on-demand wake-up call. The on-demand wake-up call may allow the control device to perform at least one task at the wireless device without user intervention at the wireless device. | 04-14-2016 |
20160105726 | WIRELESS ACCESS POINT WITH DIGITAL TELEVISION CAPABILITIES - In some embodiments a wireless access point receives digital television content. The digital television content is transmitted in a wireless manner over a wireless network of the wireless access point. Other embodiments are described and claimed. | 04-14-2016 |
20160105430 | SYSTEMS AND METHODS FOR DISTRIBUTED TRUST COMPUTING AND KEY MANAGEMENT - Devices, systems, and methods for conducting trusted computing tasks on a distributed computer system are described. In some embodiments, a client device initiates a trusted task for execution within a trusted execution environment of a remote service provider. The devices, systems, and methods may permit the client to evaluate the trusted execution capabilities of the service provider via a planning and attestation process, prior to sending data/code associated with the trusted task to the service provider for execution. Execution of the trusted task may be performed while enforcing security and/or compartmentalization context on the data/code. Systems and methods for managing and exchanging encryption keys are also described. Such systems and methods may be used to maintain the security of the data/code before during, and/or after the execution of the trusted task. | 04-14-2016 |
20160105405 | MULTI-KEY GRAPHIC CRYPTOGRAPHY FOR ENCRYPTING FILE SYSTEM ACCELERATION - Embodiments of methods and systems for encrypting and decrypting with encryption attributes are presented. An encryption attribute contains information to identify one or more segments of a file to be encrypted. An encryption process encrypts those one or more segments to generate a partly encrypted file instead of encrypting the entire file. That is, the file includes some data that are encrypted and some data that are not. In one embodiment, at least three encryption keys are used such that the encryption attribute is encrypted with using a third key. | 04-14-2016 |
20160105155 | AUTOMATIC ADJUSTMENTS OF AUDIO ALERT CHARACTERISTICS OF AN ALERT DEVICE USING AMBIENT NOISE LEVELS - The automatic adjustment of audio alert characteristics of an alert device using ambient noise levels is described. In one aspect of the invention, a machine-readable medium has executable instructions to cause a machine to perform a method to receive an audio sample of ambient noise and adjust a characteristic of the audio alert, such as, the volume level of the audio alert, based on the ambient noise level. | 04-14-2016 |
20160104679 | METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES - Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region. | 04-14-2016 |
20160103790 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103789 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103788 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103787 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103786 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160103684 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 04-14-2016 |
20160100365 | METHODS AND ARRANGEMENTS FOR FREQUENCY SELECTIVE TRANSMISSION - Logic may comprise hardware and/or code to select a narrow band from a wider channel bandwidth. Logic of communications between devices may select, e.g., a 1 or 2 MHz sub-channel from a wider channel bandwidth such as 4, 8, and 16 MHz and transmit packets on the selected 1 or 2 MHz channel. For instance, a first device may comprise an access point and a second device may comprise a station such as a low power sensor or a meter that may, e.g., operate on battery power. Logic of the devices may facilitate a frequency selective transmission scheme. Logic of the access point may transmit sounding packets or control frames across the sub-channels of the wide bandwidth channel, facilitating selection by the stations of a sub-channel and subsequent communications on the sub-channel between the access point and the station. | 04-07-2016 |
20160100159 | METHOD AND DEVICE FOR PROJECTING A 30D VIEWABLE IMAGE - According to the present invention there is provided a method for projecting a 3-D viewable image onto a display surface, comprising the steps of, providing two or more projection systems; arranging the two or more projection systems into a first group and second group, wherein the first group and second group each comprise one or more projection systems; arranging the first and second group of projection systems such that each group of project systems can project an image on a display surface, wherein the first group of projection systems is arranged such that the first group of projection systems can project an image to a first position on the display surface and the second group of projection systems is arranged such that the second group of projection systems can project an image to a second position on the display surface, wherein the first and second positions are off-set from one another; configuring the first and second group of projection systems such that the first and second group of projection systems alternately project onto the display surface. There is further provided a corresponding projection system. | 04-07-2016 |
20160100010 | COORDINATION FOR ONE-SIDED MEMORY ACCESS IN A PARTITIONED GLOBAL ADDRESS SPACE - Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a one-sided memory access to a PGAS in a distributed computing environment. The system may include a transceiver module configured to receive a message over a network, the message comprising a data portion and a data size indicator and an offset handler module configured to calculate a destination address from a base address of a memory buffer and an offset counter. The transceiver module may further be configured to write the data portion to the memory buffer at the destination address; and the offset handler module may further be configured to update the offset counter based on the data size indicator. | 04-07-2016 |
20160098920 | TRANSCODER ENABLED CLOUD OF REMOTELY CONTROLLED DEVICES - Various embodiments are directed to one or more transcoder devices in communication with an input device such as a remote control device and multiple destination devices in which the transcoder device(s) facilitate communication between the remote control and the various destination devices in the vicinity. The transcoder device(s) can also provide the user with an environmental awareness of conditions and events surrounding the user. Other embodiments are described and claimed. | 04-07-2016 |
20160095173 | CONTROL MECHANISM AND METHOD USING RGB LIGHT EMITTING DIODES - A control mechanism and method using RGB (red-green-blue) light emitting diodes (LEDs) are disclosed. A particular embodiment includes: a red-green-blue (RGB) light emitting diode (LED) having a plurality of color components, each color component being either active or inactive; and an input controller coupled to each of the plurality of color components to determine a voltage level thereon, the input controller being configured to detect a voltage change in an inactive color component when light from an active color component is reflected off of a proximate object. | 03-31-2016 |
20160095060 | METHOD AND APPARATUS FOR POWER OPTIMIZED IoT COMMUNICATION - The disclosure relates to a method, apparatus and system to provide an integrated HUB for communicating with wearable devices. The exemplary devices include an Offloading engine to communicate directly with the wearable devices at reduced power and with relaxed radio specification requirement. In one embodiment, the disclosure relates to a system having one or more antennas; a platform radio to communicate with the one or more antennas; a platform processor to communicate with the platform radio; and a first logic to combine incoming data from one or more wearable sensors, the first logic configured to fuse incoming data from the one or more wearable sensors and to determine whether to awaken the host platform. | 03-31-2016 |
20160094849 | THERMAL THROTTLING OF WiDi VIDEO STREAM RESOLUTION - Methods and apparatus relating to thermal throttling of WiDi (Wireless Display) video stream resolution are described. In an embodiment, logic generates one or more signals to cause a processor to a change the resolution and/or frame rate of a video stream in response to input from one or more sensors and one or more values. The one or more signals can also cause wireless display logic to modify a compression level of the video stream received from the processor prior to transmission of a compressed version of the video stream to a display device. Other embodiments are also disclosed and claimed. | 03-31-2016 |
20160094272 | SIGNAL ROUTING WITH REDUCED CROSSTALK - Generally, this disclosure provides systems and devices for reduction of crosstalk between routed signals. A system may include a first pair of signal lines and a second pair of signal lines and each of the pairs of signal lines include a positive signal line and a negative signal line to transmit a differential signal. The system may also include an alternating current coupling capacitor (AC cap) associated with each of the positive signal lines and each of the negative signal lines. The system may further include a routing crossover of the positive signal line and the negative signal line of the second pair of signal lines, to decrease signal crosstalk between the first and second pairs of signal lines. The routing crossover may include at least one of the AC caps. | 03-31-2016 |
20160094121 | POWER SUPPLY TOPOLOGIES WITH CAPACITANCE MANAGEMENT - In at least one embodiment there is provided a method for managing bulk capacitance of a power supply system. The method includes precharging first and second bulk capacitors of the power supply system to approximately a first output voltage level and a second output voltage level, respectively; receiving a first command signal to generate, by the power supply, the first output voltage level; coupling the first bulk capacitance to load circuitry coupled to the power supply; receiving a second command signal to generate, by the power supply, the second output voltage level; and coupling the second bulk capacitance to the load circuitry coupled to the power supply. | 03-31-2016 |
20160094054 | WIRELESS LOAD MODULATION - Techniques of load modulation are described herein. A wireless power transmitting unit may include a resonator to periodically transmit a short beacon having a first time period. The wireless power transmitting unit also includes circuitry coupled to the resonator. The circuitry is configured to detect a load change in the resonator when transmitting the short beacon and cause the resonator to transmit a long beacon subsequent to said transmitting the short beacon if said load change is detected. The long beacon has a second time period longer than the first time period. | 03-31-2016 |
20160093979 | PROTECTIVE COVER FOR A CONNECTOR - A protective cover for a connector is described herein. In one example, the protective cover can include an angled outer shell to envelop a connector, and a locking mechanism to prevent the angled outer shell from retracting to expose the connector. The protective cover can also include a plunger assembly coupled to a magnet, the magnet to disengage the locking mechanism to expose the connector, and a set of springs to return the angled outer shell to a locked position. | 03-31-2016 |
20160093960 | Press-Fit Internal Cable - A press-fit cable is described herein. The press-fit cable includes a plurality of cable wires and a plurality of pins. The plurality of pins is coupled with the plurality of cable wires. Additionally, the plurality of pins is to directly mate to a circuit board without a receptacle. | 03-31-2016 |
20160093377 | NONVOLATILE MEMORY MODULE - Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed. | 03-31-2016 |
20160093375 | REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY - The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V | 03-31-2016 |
20160093089 | TECHNIQUES FOR MULTIPLE PASS RENDERING - Techniques for multiple pass rendering include receiving vertex data for one or more objects to be enhanced. Parameters in a display list may be determined using the vertex data. Multiple pixel rendering passes may be run using the parameters in the display list. An enhanced depiction of the one or more objects may be rendered based on the multiple pixel rendering passes. Other embodiments are described and claimed. | 03-31-2016 |
20160092392 | ADAPTIVE TERMINATION SCHEME FOR LOW POWER HIGH SPEED BUS - Methods and apparatus relating to an adaptive termination scheme for a low power, high speed bus are described. In an embodiment, logic at least partially causes termination of a portion (e.g., one or more transmission lines) of an interconnect. The logic adaptively optimizes the number of lines that are to be terminated based on one or more operating conditions of the interconnect. Other embodiments are also disclosed. | 03-31-2016 |
20160092389 | UNIFIED DEVICE INTERFACE FOR A MULTI-BUS SYSTEM - The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances. | 03-31-2016 |
20160092382 | AVOIDING PREMATURE ENABLING OF NONMASKABLE INTERRUPTS WHEN RETURNING FROM EXCEPTIONS - A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed. | 03-31-2016 |
20160092287 | EVIDENCE-BASED REPLACEMENT OF STORAGE NODES - Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive reliability information from at least one component of a storage device coupled to the controller, store the reliability information in a memory communicatively coupled to the controller, generate at least one reliability indicator for the storage device, and forward the reliability indicator to an election module. Other embodiments are also disclosed and claimed. | 03-31-2016 |
20160092223 | PERSISTENT STORE FENCE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed. | 03-31-2016 |
20160092113 | HOST-MANAGED NON-VOLATILE MEMORY - One embodiment provides a computing device. The computing device includes a processor; a chipset; a memory; and indirection logic. The indirection logic is to receive a host logical block address (LBA) associated with a first sector of data, map the host LBA from a host address space to a first device LBA in a device address space, the device address space related to a non-volatile memory (NVM) storage device physical memory address space, and provide the first sector of data and the first device LBA to the NVM storage device. | 03-31-2016 |
20160091982 | MECHANISM TO PROVIDE VISUAL FEEDBACK REGARDING COMPUTING SYSTEM COMMAND GESTURES - A mechanism to provide visual feedback regarding computing system command gestures. An embodiment of an apparatus includes a sensing element to sense a presence or movement of a user of the apparatus, a processor, wherein operation of the processor includes interpretation of command gestures of a user to provide input to the apparatus; and a display screen, the apparatus to display one or more icons on the display screen, the one or more icons being related to the operation of the apparatus. The apparatus is to display visual feedback for a user of the apparatus, visual feedback including a representation of one or both hands of the user while the one or both hands are within a sensing area for the sensing element. | 03-31-2016 |
20160091963 | REMOTE WEARABLE INPUT SOURCES FOR ELECTRONIC DEVICES - In one example an electronic device comprises at least one sensor to detect an input from a remote input source and a controller comprising logic, at least partly including hardware logic, to detect an input on the at least one sensor, generate a signal in response to the input; and forward the signal to an application. Other examples may be described. | 03-31-2016 |
20160091959 | EFFICIENT POWER MANAGEMENT OF UART INTERFACE - Methods and apparatus relating to efficient and/or robust link power management of a UART (Universal Asynchronous Receiver/Transmitter) interface are described. In an embodiment, logic causes a link to enter into a low power consumption state in response to a message exchange over data lines of a UART (Universal Asynchronous Receiver/Transmitter) interface. The message exchange over the data lines of the UART interface is followed by a modification to one or more flow control signals coupled to the UART interface. Other embodiments are also disclosed. | 03-31-2016 |
20160091938 | SYSTEM AND METHOD FOR ADAPTIVE THERMAL AND PERFORMANCE MANAGEMENT IN ELECTRONIC DEVICES - A system and method for adaptive thermal and performance management in electronic devices are disclosed. A particular embodiment includes: providing a processor with a plurality of selectable performance levels and a sensor in an electronic device; receiving sensor information from the sensor, the sensor information including information for determining if the electronic device is positioned proximately to an active airflow; determining a device context from the sensor information; and dynamically modifying the performance level of the processor by implementing one of a plurality of selectable performance levels of the processor based on the device context. | 03-31-2016 |
20160091935 | HINGE CONFIGURATION FOR AN ELECTRONIC DEVICE - Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). The electronic device may also include a hinge assembly to secure a top portion of the electronic device to an accessory. The hinge assembly is to allow a rotation of the top portion in relation to the accessory. The hinge assembly may include a plurality of discs to receive a plurality of segments of the accessory as the hinge assembly engages to secure the top portion of the electronic device to the accessory. | 03-31-2016 |
20160091874 | SYSTEM AND METHOD FOR ELECTRONICALLY TAGGING ITEMS FOR USE IN CONTROLLING ELECTRICAL DEVICES - A system and method for electronically tagging items for use in controlling electrical devices are disclosed. A particular embodiment includes: a controller; a tag reader interface in data communication with the controller, the tag reader interface being configured to receive item information read from an electronically readable tag attached to an item placed in an electrical device; a display device driver in data communication with the controller for driving the display of operational messages for a user/operator of the electrical device, the operational messages being based on the item information; and an appliance interface in data communication with the controller for receiving control commands from the controller and for issuing corresponding control signals for controlling the electrical device, the control commands being based on the item information. | 03-31-2016 |
20160091867 | DIGITAL ANALOG DISPLAY WITH ROTATING BEZEL - A wearable device is described herein. The wearable device includes a display. The display can be a digital display with analog components. The wearable device also includes an input device. The input device is to control the digital display and the analog components correspond to the digital display. In some cases, the input device is a bezel. | 03-31-2016 |
20160091781 | INTEGRATED AND ADJUSTABLE IMAGE PROJECTION WITH AUTO-IMAGE CORRECTION IN ELECTRONIC DEVICES USING AN IN-FACING OR WORLD-FACING IMAGE PROJECTOR - A system and method for implementing integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or world-facing image projector are disclosed. A particular embodiment includes an electronic device including: a lid; a base including a hinge coupling the lid with the base; and an image projection subsystem including an image projector installed in the lid, the image projector being configured to produce a projected image that is projected onto a projection surface, the angle of the projection being adjustable by adjusting the angle of the lid relative to the base. | 03-31-2016 |
20160091336 | LOCATION BASED HAPTIC DIRECTION FINDING - Methods and apparatus relating to location-based haptic direction finding are described. In an embodiment, logic (e.g., included in a mobile computing device) redirects one or more navigational hints to one or more trembler devices instead of a display device and/or speakers of the mobile computing device in response to a request to provide haptic directional cues. Other embodiments are also disclosed and claimed. | 03-31-2016 |
20160091313 | Virtual Gyroscope Using Dual Magnetometers For Electronic Devices - In one example a magnetometer unit comprises logic to receive first magnetic response data from a first magnetic sensor and second magnetic response data from a second magnetic sensor displaced from the first magnetic sensor, generate a composite response surface representation from the first magnetic response data and the second magnetic response data, and store the composite response surface representation in a non-transitory memory. Other examples may be described. | 03-31-2016 |
20160090766 | 360 DEGREE HINGE ASSEMBLY FOR ELECTRONIC DEVICES - In one example a hinge assembly for an electronic device comprises a linkage comprising a first bushing disposed at a first end of the linkage and a second bushing disposed at a second end of the bushing, a first shaft rotatable within the first bushing about a first axis, a second shaft rotatable within the second bushing about a second axis, and at least one compression element disposed on the first shaft, wherein the first shaft and the first bushing are threaded such that rotation of the first shaft within the first bushing induces lateral translation of the first shaft along the first axis. Other examples may be described. | 03-31-2016 |
20160088559 | NETWORK VETTING OF WIRELESS MOBILE DEVICE INITIATED DISCONNECT - Technology is discussed for allowing a wireless mobile device, such as a User Equipment (UE), to coordinate with a Radio Access Network, such as an Evolved-Universal Terrestrial Radio Access Network (E-UTRAN), to tear down a power intensive messaging connection, such as a Radio Resource Control (RRC) connection, to met needs of both the UE and the E-UTRAN. The UE can initiate the tear down process based on information at the UE about the potential need of the UE for the RRC connection and/or the state of the UE's battery charge. The E-UTRAN can then determine whether to grant the request based on the potential overhead involved. The determination can be important to the E-UTRAN because of the large overhead associated with frequent disconnection and re-establishment of the RRC connection. Upon receipt of an affirmative response, the UE can tear down the RRC connection to save battery power. | 03-24-2016 |
20160088531 | HANDOVER AT SPECTRUM RELEASE FOR LICENSED SHARED ACCESS - Embodiments of Evolved Node-B (eNBs), user equipment (UE) and methods for licensed shared access (LSA) handover are generally described herein. An eNB includes hardware processing circuitry to receive a command to release spectrum resources in a LSA band over which the eNB serves an LSA cell; to determine whether user equipment (UEs) served by the eNB are permitted to skip a random access process (RAP) to be handed over to a target cell operating on a band separate from the LSA band; and to transmit a message to a UE served by the eNB instructing the UE that the UE is to be handed over to the target cell, the message including one or more indicators based on the determination. Other apparatuses, systems and methods are also disclosed. | 03-24-2016 |
20160088509 | MACHINE TYPE COMMUNICATION MONITORING FRAMEWORK FOR 3GPP SYSTEMS - A 3GPP monitoring architecture framework provides monitoring event configuration, detection, and reporting for machine-type and other mobile data applications by configuring monitoring on a mobility management entity (MME), a serving general packet radio service support node (SGSN), or a home subscriber service (HSS) node through existing interfaces, such as Tsp, T4, and T5 interfaces. | 03-24-2016 |
20160088220 | CAMERA COMMAND SET HOST COMMAND TRANSLATION - The present disclosure provides techniques for translating input camera commands to device-specific commands. Camera commands may be translated by a translation engine located separately from the camera and then transferred to the camera. The translated commands may be less complex than input commands. By translating the commands, older cameras may be capable of supporting newer commands which are not natively supported. | 03-24-2016 |
20160088143 | METHOD, SYSTEM AND APPARATUS FOR GRACEFUL DISCONNECTION FROM A WIRELESS DOCKING STATION - The disclosed embodiments relate to method, system and apparatus for gracefully disconnecting from a wireless docking station. In one embodiment, the disclosure provides a method and system for proactively predicting an upcoming link loss caused by the mobile device's movement away from the wireless docking system. In an exemplary embodiment, data provided by the mobile device's accelerometer as well as signal quality data are used to indicate an upcoming link loss. Prior link loss patterns including accelerometer output and signal quality can be used to determine intentional link loss events. Once determination is made that the upcoming disconnection is intentional, steps may be taken to gracefully disconnect the mobile device from the docking station before the link loss occurs. The graceful disconnection may be implemented without requiring user intervention or incurring data loss. | 03-24-2016 |
20160087961 | Techniques for Authenticating a Device for Wireless Docking - Examples are disclosed for a first device to wirelessly dock to a second device. In some examples, a first device may receive identification from the second device for wirelessly docking. The first device may determine whether the second device is allowed to wirelessly dock and if allowed an authentication process may be implemented. The first device may then wirelessly dock to the second device based on a successful authentication. Other examples are described and claimed. | 03-24-2016 |
20160087847 | MECHANISM FOR MANAGEMENT CONTROLLERS TO LEARN THE CONTROL PLANE HIERARCHY IN A DATA CENTER ENVIRONMENT - Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy. | 03-24-2016 |
20160087447 | WIRELESS POWER SAFETY COMPONENT - Techniques of providing increased safety for wireless systems are described herein. A wireless power receiving unit includes a first receiving coil to inductively couple to a wireless power transmitting unit having a transmitting coil. A safety component is provided to reduce wireless power received at a second receiving coil from the wireless power transmitting unit. | 03-24-2016 |
20160087376 | SIGNALING LINK GROUNDING - Techniques for signal grounding are described herein. The techniques include a conductive element conductively coupled to an exposed ground pad of a circuit board. The conductive element is to conductively couple to a shield of a signaling link, and thereby conductively coupling the shield to the exposed ground pad. | 03-24-2016 |
20160086905 | SHAPED AND ORIENTED SOLDER JOINTS - The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate. | 03-24-2016 |
20160086871 | INTEGRATED HEAT SPREADER FOR MULTI-CHIP PACKAGES - An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive structures secured within the heat spreader frame openings. The thermally conductive structures can be formed to have various thicknesses which compensate for varying heights between at least two microelectronic devices in a multi-chip package. The thermally conductive structures can be secured in the heat spreader frame by sizing the openings and the thermally conductive structures such that the thermally conductive structures can be secured within the openings without requiring welding or adhesives. | 03-24-2016 |
20160086673 | SENSING WITH BOOST - The present disclosure relates to sensing with boost. An apparatus includes boost logic. Boost logic includes a boost source and a plurality of boost interfaces coupled to the boost source. The boost source is configured to provide a boost clamp voltage to each of the plurality of boost interfaces. Each of the plurality of boost interfaces includes a respective buffer configured to buffer the boost source from a respective load. Each boost interface is configured to provide a boost voltage to the respective load. The boost voltage configured to increase a sense window. The boost voltage related to the boost clamp voltage. | 03-24-2016 |
20160085969 | USING A TRUSTED PLATFORM MODULE FOR BOOT POLICY AND SECURE FIRMWARE - Embodiments of apparatuses and methods for using a trusted platform module for boot policy and secure firmware are disclosed. In one embodiment, a trusted platform module includes a non-volatile memory, a port, and a mapping structure. The port is to receive an input/output transaction from a serial bus. The transaction includes a system memory address in the address space of a processor. The mapping structure is to map the system memory address to a first location in non-volatile memory. | 03-24-2016 |
20160085965 | EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION ON A POINT-TO-POINT INTERCONNECT SYSTEM - Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction. | 03-24-2016 |
20160085959 | PREVENTION OF CABLE-SWAP SECURITY ATTACK ON STORAGE DEVICES - Generally, this disclosure provides systems, devices, methods and computer readable media for prevention of cable swap security attacks on storage devices. A host system may include a provisioning module configured to generate a challenge-response verification key-pair and further to provide the key-pair to the storage device to enable the challenge-response verification. The system may also include a link error detection module to detect a link error between the host system and the storage device. The system may further include a challenge-response protocol module configured to initiate, in response to the link-error detection, a verification challenge from the storage system and to provide a response to the verification challenge based on the key-pair. | 03-24-2016 |
20160085711 | THROTTLING INTEGRATED LINK - Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed. | 03-24-2016 |
20160085692 | ENCRYPTION INTEGRITY CHECK IN MEMORY - Apparatus, systems, and methods for AES integrity check in memory are described. In one embodiment, a controller comprises logic to receive a write request from a host device to write a line of data to the memory device, determine a first plaintext cyclic redundancy check from the line of data, encrypt the line of data, encrypt the first plaintext CRC with a unique value to generate a first encrypted CRC, and store the encrypted line of data and the first encrypted CRC in memory. Other embodiments are also disclosed and claimed. | 03-24-2016 |
20160085668 | TECHNIQUES FOR IMPROVING RELIABILITY AND PERFORMANCE OF PARTIALLY WRITTEN MEMORY BLOCKS IN MODERN FLASH MEMORY SYSTEMS - Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed. | 03-24-2016 |
20160085621 | RECOVERY ALGORITHM IN NON-VOLATILE MEMORY - Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed. | 03-24-2016 |
20160085547 | DATA ELEMENT SELECTION AND CONSOLIDATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A processor includes packed data registers, and a decode unit to decode a data element selection and consolidation instruction. The instruction is to have a first source packed data operand that is to have a plurality of data elements, and a second source operand that is to have a plurality of mask elements. Each mask element corresponds to a different data element in the same relative position. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, is to store a result packed data operand in a destination storage location that is to be indicated by the instruction. The result packed data operand is to include all data elements of the first source packed data operand, which correspond to unmasked mask elements of the second source operand, consolidated together in a portion of the result packed data operand. | 03-24-2016 |
20160085358 | DYNAMIC INPUT MODE SELECTION - The present application is directed to dynamic input mode selection. In general, a system may sense a user's finger approaching a surface of a display (e.g., an imminent user touch input) and, depending on at least one trigger condition, may perform at least one output operation. For example, a first trigger condition may cause a display to enlarge at least a portion of a displayed image based on the imminent user touch input, a second trigger condition may cause the display to present a menu corresponding to an object in the enlarged portion, etc. This functionality may be implemented utilizing either an operating system (OS)-aware configuration or an OS-unaware configuration. In an OS-aware configuration, an intent-to-touch (ITT) module may utilize application program interfaces (APIs) in the OS to facilitate display zooming, menu presentation, coordinate translation, etc. In an OS-unaware configuration, the ITT module may facilitate these actions without OS assistance. | 03-24-2016 |
20160085084 | PROJECTION DEVICE - According to the present invention there is provided a projection device ( | 03-24-2016 |
20160085068 | COMPACT ILLUMINATION SYSTEM - An illumination system includes a light source arranged for emitting non-collimated light towards a reflective surface of a scanning mirror assembly such that the light source occludes a region of the light reflected from the reflective surface. The scanning mirror assembly includes the reflective surface, which is arranged to be rotationally displaced around at least one rotation axis. The illumination system also includes an optical element for changing the propagation direction of the said reflected light so as to illuminate at least a part of the said occluded region. | 03-24-2016 |
20160081029 | TECHNIQUES FOR MANAGING IDLE STATE ACTIVITY IN MOBILE DEVICES - An apparatus may comprise a radio-frequency (RF) transceiver and a message aggregation module arranged to intercept multiple messages from one or more mobile data applications during an idle mode of a device, one or more of the multiple messages operable to trigger a transition of the device from the idle mode to a connected mode by causing a radio resource control message to be sent from the device to a radio access network, the message aggregation module to store the multiple messages in a buffer associated with the one or more mobile data applications in order to maintain the device in the idle mode, and schedule for transmission by the RF transceiver the stored messages at a defined time instance based on a delay tolerance for the one or more mobile data applications when the device is in the connected mode. Other embodiments are disclosed and claimed. | 03-17-2016 |
20160081013 | TECHNIQUES FOR WIRELESS NETWORK DISCOVERY AND SELECTION SUPPORT - Techniques for wireless network discovery and selection support are described. In one embodiment, for example, an evolved packet core (EPC) node may comprise a processor circuit to implement an access network discovery and selection function (ANDSF) according to a management object that includes a branch comprising one or more policies to select a wireless local area network (WLAN), the processing circuitry to receive capabilities information and location information for a user equipment (UE) and determine access network information for the UE based on the capabilities information and the location information. Other embodiments are described and claimed. | 03-17-2016 |
20160080057 | SPATIAL MULTIPLEXING IN A CELLULAR NETWORK - The present invention provides methods and apparatus for implementing spatial multiplexing in conjunction with the one or more multiple access protocols during the broadcast of information in a wireless network. One example includes transmitting a first and a second data signal to a remote unit from a respective first and a second spatially separate antenna of a base station so that the first and second data signals have a first spatial configuration, determining that the first and the second data signals are not spatially separated by the remote unit, reconfiguring the (spatial multiplexing logic | 03-17-2016 |
20160079423 | ENHANCED DISLOCATION STRESS TRANSISTOR - A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. | 03-17-2016 |
20160079141 | METHODS OF FORMING SERPENTINE THERMAL INTERFACE MATERIAL AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal interface material comprising a thermally conductive serpentine foil located between a first and a second interface material. The serpentine foil may be in a parallel position or a rotated position, in embodiments. | 03-17-2016 |
20160078926 | DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) - In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit. | 03-17-2016 |
20160078319 | Method, Apparatus and Computer Readable Recording Medium for Detecting a Location of a Face Feature Point Using an Adaboost Learning Algorithm - The present disclosure relates to detecting the location of a face feature point using an Adaboost learning algorithm. According to some embodiments, a method for detecting a location of a face feature point comprises: (a) a step of classifying a sub-window image into a first recommended feature point candidate image and a first non-recommended feature point candidate image using first feature patterns selected by an Adaboost learning algorithm, and generating first feature point candidate location information on the first recommended feature point candidate image; and (b) a step of re-classifying said sub-window image classified into said first non-recommended feature point candidate image, into a second recommended feature point candidate image and a second non-recommended feature point candidate image using second feature patterns selected by the Adaboost learning algorithm, and generating second feature point candidate location information on the second recommended feature point recommended candidate image. | 03-17-2016 |
20160077864 | PROCESSORS, METHODS, AND SYSTEMS TO ENFORCE BLACKLISTED PAGING STRUCTURE INDICATION VALUES - A method of an aspect includes receiving an indication of an attempt by a virtual machine to modify a paging structure identification storage location to have a given value. It is determined that the given value matches at least one of a set of one or more blacklist values. The attempt by the virtual machine to modify the paging structure identification storage location to have the given value is trapped to a virtual machine monitor. Other methods, apparatus, and systems are also disclosed. | 03-17-2016 |
20160075551 | BACKSIDE BULK SILICON MEMS - An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer. | 03-17-2016 |
20160073221 | THIN CHASSIS NEAR FIELD COMMUNICATION (NFC) ANTENNA INTEGRATION - Described herein are techniques related one or more systems, apparatuses, methods, etc. for integrating a near field communications (NFC) coil antenna in a portable device. For example, the NFC antenna is integrated under a metal chassis of the portable device. The metal chassis and a conductive coating—that is integrated underneath the full metal chassis—are designed to include one or more slots to provide high impedance to Eddy current induced in the conductive coating. | 03-10-2016 |
20160073134 | SIZE BASED TRANSFORM UNIT CONTEXT DERIVATION - Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation. | 03-10-2016 |
20160073126 | TECHNIQUES FOR INTER-LAYER RESIDUAL PREDICTION - Techniques for inter-layer residual prediction are described. In one embodiment, for example, an apparatus may comprise an encoding component to determine whether a predicted motion for an enhancement layer block is consistent with a predicted motion for a collocated lower-layer block, determine whether to apply inter-layer residual prediction to the enhancement layer block based on whether the predicted motion for the enhancement layer block is consistent with the predicted motion for the collocated lower-layer block, and in response to a determination that inter-layer residual prediction is to be applied to the enhancement layer block, generate a predicted residual for the enhancement layer block based on a residual for the collocated lower-layer block and generate a second-order residual for the enhancement layer block by comparing a calculated residual to the predicted residual. Other embodiments are described and claimed. | 03-10-2016 |
20160073000 | METHOD AND SYSTEM FOR CONTROLLING A LASER-BASED LIGHTING SYSTEM - The present invention concerns a method for controlling a laser-based lighting system comprising a scanning mirror arrangement, arranged to be rotatable around two substantially orthogonal axes. The method comprises: (a) a sensor capturing a first image; (b) the sensor sending data representing at least part of the first image to an image generation unit; (c) the image generation unit generating a second image based on the data representing at least part of the first image, wherein the generated second image comprises information representing a feature region in the first image; (d) the image generation unit sending the second image to a projection system controller; and (e) the projection system controller, based on the received second image, controlling the operation of a projection system comprising a laser light source; and a scanning mirror arrangement for receiving the light radiated by the laser light source, and for reflecting the received light to a wavelength conversion element to project the second image. In the method the second image is streamed to the projection controller as an image pixel stream without first saving it in a memory. | 03-10-2016 |
20160072869 | ADAPTIVE VARIABLE FIDELITY MEDIA DISTRIBUTION SYSTEM AND METHOD - An adaptive variable fidelity media provision system and method are provided herein. | 03-10-2016 |
20160071934 | HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS - Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface. | 03-10-2016 |
20160070931 | SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS - A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words A | 03-10-2016 |
20160070910 | PLATFORM BASED VERIFICATION OF CONTENTS OF INPUT-OUTPUT DEVICES - A platform to support verification of the contents of an input-output device. The platform includes a platform hardware, which may verify the contents of the I/O device. The platform hardware may comprise components such as manageability engine and verification engine that are used to verify the contents of the I/O device even before the contents of the I/O device are exposed to an operating system supported by a host. The platform components may delete the infected portions of the contents of I/O device if the verification process indicates that the contents of the I/O device include the infected portions. | 03-10-2016 |
20160070577 | BOOTING AN OPERATING SYSTEM OF A SYSTEM USING A READ AHEAD TECHNIQUE - In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed. | 03-10-2016 |
20160070575 | PROCESSOR TO EXECUTE SHIFT RIGHT MERGE INSTRUCTIONS - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 03-10-2016 |
20160064545 | TECHNIQUES AND CONFIGURATIONS FOR STACKING TRANSISTORS OF AN INTEGRATED CIRCUIT DEVICE - Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed. | 03-03-2016 |
20160064520 | GERMANIUM-BASED QUANTUM WELL DEVICES - A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. | 03-03-2016 |
20160063033 | METHOD, APPARATUS FOR PROVIDING A NOTIFICATION ON A FACE RECOGNITION ENVIRONMENT, AND COMPUTER-READABLE RECORDING MEDIUM FOR EXECUTING THE METHOD - According to a method for providing a notification on a face recognition environment of the present disclosure, the method includes obtaining an input image that is input in a preview state, comparing feature information for a face included in the input image with feature information for a plurality of reference images of people stored in a predetermined database to determine, in real-time, whether the input image satisfies a predetermined effective condition for photographing. The predetermined effective condition for photographing is information regarding a condition necessary for recognizing the face included in the input image at a higher accuracy level than a predetermined accuracy level. The method further includes providing a user with a predetermined feedback for photographing guidance that corresponds to whether the predetermined effective condition for photographing is satisfied. According to the method, a condition of a face image detected for face recognition is checked, and if there is an unsuitable element in recognizing the face, it is notified to a user such that an obstruction environment hindering the face recognition by the user is removed, for enhancing a success rate of the face recognition. | 03-03-2016 |
20160057056 | IN NIC FLOW SWITCHING - Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing. | 02-25-2016 |
20160056960 | SYSTEM AND METHOD FOR EXECUTION OF A SECURED ENVIRONMENT INITIALIZATION INSTRUCTION - A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations. | 02-25-2016 |
20160056592 | CONNECTOR ASSEMBLY FOR AN ELECTRONIC DEVICE - Particular examples described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of hardware, elements, circuitry, etc.). The electronic device may also include a connector assembly that is positioned within at least a portion of a recess of the electronic device, where the connector assembly includes: a first assembly that is to receive a connector; and a second assembly that is to receive an identification module that is to provide an association between a user and the electronic device. | 02-25-2016 |
20160056540 | MODULAR DESIGN OF A HIGH POWER, LOW PASSIVE INTERMODULATION, ACTIVE UNIVERSAL DISTRIBUTED ANTENNA SYSTEM INTERFACE TRAY - A modular high power, low passive intermodulation, active, universal, distributed antenna system interface tray that includes one or more front-end RF frequency duplexers instead of a high power, low passive intermodulation attenuator to achieve superior FIM performance. A cable switch matrix allows for the use of the system among varying power levels and accomplishes the above in a modular architecture. | 02-25-2016 |
20160056384 | HYBRID CARBON-METAL INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed. | 02-25-2016 |
20160056278 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) WITH UNDOPED DRAIN UNDERLAP WRAP-AROUND REGIONS - Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions. | 02-25-2016 |
20160056180 | HETEROGENEOUS SEMICONDUCTOR MATERIAL INTEGRATION TECHNIQUES - Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands. | 02-25-2016 |
20160055612 | ADAPTIVE SCHEDULING FOR TASK ASSIGNMENT AMONG HETEROGENEOUS PROCESSOR CORES - Generally, this disclosure provides systems, devices, methods and computer readable media for adaptive scheduling of task assignment among heterogeneous processor cores. The system may include any number of CPUs, a graphics processing unit (GPU) and memory configured to store a pool of work items to be shared by the CPUs and GPU. The system may also include a GPU proxy profiling module associated with one of the CPUs to profile execution of a first portion of the work items on the GPU. The system may further include profiling modules, each associated with one of the CPUs, to profile execution of a second portion of the work items on each of the CPUs. The measured profiling information from the CPU profiling modules and the GPU proxy profiling module is used to calculate a distribution ratio for execution of a remaining portion of the work items between the CPUs and the GPU. | 02-25-2016 |
20160055415 | AUTOMATED QUALITY ASSESSMENT OF PHYSIOLOGICAL SIGNALS - Methods and systems may provide for receiving a physiological signal from a sensor configuration associated with a mobile device. A qualitative analysis may be conducted for each of a plurality of noise sources in the physiological signal to obtain a corresponding plurality of qualitative ratings. In addition, at least the plurality of qualitative ratings may be used to determine whether to report the physiological signal to a remote location. In one example, a quantitative analysis is conducted for each of the plurality of noise sources to obtain an overall quality level, wherein the overall quality level is also used to determine whether to report the physiological signal to the remote location. | 02-25-2016 |
20160054787 | Method, System, and Apparatus for Dynamic Thermal Management - A method, apparatus, article of manufacture, and system, the method including, in some embodiments, processing a computational load by a first core of a multi-core processor, and dynamically distributing at least a portion of the computational load to a second core of the multi-core processor to reduce a power density of the multi-core processor for the processing of the computational load. | 02-25-2016 |
20160054577 | MICRO-PROJECTION DEVICE WITH ANTI-SPECKLE VIBRATION MODE - A micro-projection system for projecting light on a projection surface, comprising: at least one coherent light source ( | 02-25-2016 |
20160054141 | SKETCH AIDED ROUTE SELECTION FOR NAVIGATION DEVICES AND APPLICATIONS - One particular example includes a system, comprising a processor and a memory to store instructions that when executed by the processor performs operations, comprising displaying a map of a first area on a display; receiving an instruction to designate a second area on the map to be avoided; displaying the second area to be avoided on the map; and generating a route from a first point to a second point, where the route does not go through the second area to be avoided. | 02-25-2016 |
20160053990 | SYSTEM FOR DETERMINING SCALING IN A BOILER - The present disclosure is directed to a system for determining scaling in a boiler. At least one sensor may monitor a boiler during operation and provide sensor data to a boiler monitoring module including a boiler scaling determination module that may determine an amount of scaling in the boiler. Example sensor data may comprise power input, a temperature of liquid in the boiler and an air temperature within an enclosure housing the boiler. The boiler monitoring module may determine thermal energy transfer to the boiler based on the liquid and enclosure temperatures. A machine learning engine may determine a rate of thermal energy transfer to the liquid in view of the power input, the rate of thermal energy transfer being evaluated by the machine learning engine to identify delay in the rate of thermal energy transfer that quantifies an amount of scaling in the boiler. | 02-25-2016 |
20160050703 | NETWORK ASSISTED DEVICE-TO-DEVICE DISCOVERY FOR PEER-TO-PEER APPLICATIONS - The techniques introduced here provide for network assisted device-to-device communication for peer-to-peer applications. The techniques include registering a user's peer-to-peer application identifier with a peer-to-peer application server, registering a user's peer-to-peer application ID with a device-to-device server, sending a peer-to-peer service request to the peer-to-peer application server, and receiving network assistance in discovering a peer with the desired P2P content/service and establishing a device-to-device communication arrangement for exchange of peer-to-peer services. The network assistance is provided over the user plane. | 02-18-2016 |
20160050674 | TECHNIQUES FOR PROVIDING FLEXIBLE CLEAR CHANNEL ASSESSMENT DETECTION THRESHOLDS IN A WIRELESS NETWORK - Examples are disclosed for providing flexible clear channel assessment (CCA) detection thresholds in a wireless local access network (WLAN). In some examples, an apparatus for dynamically setting a clear channel assessment (CCA) threshold in a wireless local area network (WLAN) may comprise a processor component, a radio coupled to the processor component, and logic for execution by the processor component to establish a CCA threshold for a wireless channel of the WLAN, send a first wireless message to one or more wireless station (STA) devices in wireless proximity to the apparatus informing the one or more STA devices of the established CCA threshold and instructing the one or more STA devices to avoid CCA levels exceeding the CCA threshold on the wireless channel and send a second wireless message to a wireless access point (AP) device associated with the apparatus informing the AP device of the established CCA threshold and instructing the AP device to broadcast use of the CCA threshold on the wireless channel. Other examples are described and claimed. | 02-18-2016 |
20160049499 | CAPPING DIELECTRIC STRUCTURES FOR TRANSISTOR GATES - The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process. | 02-18-2016 |
20160048977 | Method and Device for Detecting Face, and Non-Transitory Computer-Readable Recording Medium for Executing the Method - In the present disclosure, a plurality of frames of input images sequentially received for a predetermined time interval is obtained, and a face detecting operation is performed on a first frame if a full detecting mode is implemented. If a face is detected from a specific region of the first frame during the face detecting operation, a face tracking mode is implemented, a second frame is divided to produce the divided input image portions of the second frame, and the face tracking operation is performed on a surrounding region of the specific region of the divided input image portions of the second frame that corresponds to the specific region in the first frame. If the face is not detected in the face tracking mode, a partial detecting mode is implemented, and the face detecting operation is performed on image portions resized on divided input image portions of a third frame to which a specific region of the third frame corresponding to the specific region of the first frame belongs. | 02-18-2016 |
20160048322 | TECHNIQUES FOR DEVICE CONNECTIONS USING TOUCH GESTURES - Techniques for device connections using touch gestures are described. A method may comprise receiving a first gesture input at a first electronic device, receiving, at the first electronic device, a second gesture input from a second computing device in proximity to the first computing device, comparing the first gesture input and the second gesture input, and establishing a wireless connection between the first computing device and the second computing device if a similarity of the first gesture input and the second gesture input meets or exceeds a similarity threshold based on the comparing. Other embodiments are described and claimed. | 02-18-2016 |
20160044005 | MUTUALLY ASSURED DATA SHARING BETWEEN DISTRUSTING PARTIES IN A NETWORK ENVIRONMENT - An apparatus for sharing information between entities includes a processor and a trusted execution module executing on the processor. The trusted execution module is configured to receive first confidential information from a first client device associated with a first entity, seal the first confidential information within a trusted execution environment, receive second confidential information from a second client device associated with a second entity, seal the second confidential information within the trusted execution environment, and execute code within the trusted execution environment. The code is configured to compute a confidential result based upon the first confidential information and the second confidential information. | 02-11-2016 |
20160043572 | RANGE ADAPTATION MECHANISM FOR WIRELESS POWER TRANSFER - In accordance with various aspects of the disclosure, a method and apparatus is disclosed that includes features of a switching mechanism coupled to a wireless power transmitting device, wherein the switching mechanism is configured to selectively control operation of a transmitting coil in the wireless power transmitting device. | 02-11-2016 |
20160043191 | SEMICONDUCTOR DEVICE CONTACTS - Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices. | 02-11-2016 |
20160043056 | DIE ASSEMBLY ON THIN DIELECTRIC SHEET - A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet is over the interconnect areas of the first and the second die. Conductive vias in the dielectric sheet connect with pads of the interconnect areas. A build-up layer over the dielectric sheet includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias. The dies are mounted to a package substrate through the build-up layers, and a package cover is over the dies, the dielectric sheet, and the build-up layer. | 02-11-2016 |
20160042184 | LOGGING IN SECURE ENCLAVES - Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address. | 02-11-2016 |
20160041921 | LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed. | 02-11-2016 |
20160035735 | ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY - Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region. | 02-04-2016 |
20160035725 | TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate. | 02-04-2016 |
20160035724 | TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate. | 02-04-2016 |
20160035073 | Method and Device for Processing Digital Image, and Computer-Readable Recording Medium - There is provided a method of processing a digital image including: (a) obtaining a plurality of images; (b) converting the plurality of images into histograms; (c) setting one of the plurality of images as a reference image and another of the plurality of images as a comparison target image; (d) adjusting a distribution of the histogram of the reference image to match a distribution of the histogram of the comparison target image to produce an adjusted reference image; (e) comparing a difference between the adjusted reference image and the comparison target image to produce a masking image; (f) applying the masking image to the comparison target image to produce an adjusted comparison target image; and (g) combining the reference image and the adjusted comparison target image to produce a high dynamic range (HDR) image. Accordingly, even if there is a complex motion on a subject, a clear image without an image overlap or a ghost effect may be obtained when producing the HDR image. | 02-04-2016 |
20160034345 | MEMORY LATENCY MANAGEMENT - Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed. | 02-04-2016 |
20160034224 | IN-PLACE CHANGE BETWEEN TRANSIENT AND PERSISTENT STATE FOR DATA STRUCTURES ON NON-VOLATILE MEMORY - Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed. | 02-04-2016 |
20160034196 | Techniques to Configure a Solid State Drive to Operate in a Storage Mode or a Memory Mode - Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed. | 02-04-2016 |
20160034020 | STAGED POWER DISTRIBUTION CONTROL - Various embodiments are directed to restrictions in portable computing device electric power to accommodate reductions in the voltage level of a power source. An apparatus comprises a controller caused to receive configuration data from a main processor circuit specifying a voltage level threshold and selected action to take to reduce electric power to a first component in response to the voltage level falling below the first voltage level threshold, recurringly monitor the voltage level; based on the voltage level falling below the first voltage level threshold, take the first selected action and transmit a signal to the main processor circuit indicating that the voltage level has fallen below the first voltage level threshold and that the first selected action has been taken; transmit the voltage level to the main processor circuit; receive a signal from the main processor circuit to undo the first selected action; and so undo. | 02-04-2016 |
20160033444 | DEVICE AND METHOD FOR DETECTING REDOX REACTIONS IN SOLUTION - Described herein is a device comprising a plurality of first reaction electrodes arranged in an array, the plurality of first reaction electrodes configured to be exposed to a solution and having a capacitance; first circuitry configured to controllably connect the plurality of first reaction electrodes to a bias source and controllably disconnect the plurality of first reaction electrodes from the bias source; and second circuitry configured to measure a rate of charging or discharging of the capacitance. Also described herein is a method of using this device to sequence DNA. | 02-04-2016 |
20160029262 | SYSTEMS AND METHODS FOR WIRELESS SIGNAL MEASUREMENT AND REPORTING FOR DEVICE-TO-DEVICE COMMUNICATION - Methods, systems, and devices for configuration and reporting of proximity detection measurements are disclosed herein. User equipment (UE) is configured to receive and store a PD-RS list from an evolved universal terrestrial radio access network (E-UTRAN) node B (eNB). The PD-RS list includes a radio resource configuration for at least a first proximity discovery reference signal (PD-RS). The UE is configured to measure at least the first PD-RS to determine a signal parameter for the first PD-RS. The UE reports the signal parameter for the first PD-RS to the eNB. | 01-28-2016 |
20160029254 | ENABLING ECSFB IN HETNETS - An enhanced Circuit Switch Fallback enabled Heterogeneous Network (HETNET) is provided by the present invention in which the 1×IWS functionality is co-located with LTB eNB. It also tunnels 1×RTT over LTE messages directly to the Convergence Server over SIP, Further, it enables distributed PN-FAP identification determination. A mobile management, entity is configured to maintain multiple 1×CS IWS tunnels. Multiple 1×CS IWS tunnels are established, by using the same S1 tunnel end point used in establishing a Borne evolved Node B Gateway of the HETNET. The HETNET is configured to provide a correct FAP identification to the convergence server so that handover preparation can be done. | 01-28-2016 |
20160029122 | MULTIPLE DEVICE NOISE REDUCTION MICROPHONE ARRAY - Various embodiments are directed to cooperation among communications devices having microphones to employ their microphones in unison to provide voice detection with noise reduction for voice communications. A first communications device comprises a processor circuit; a first microphone; an interface operative to communicatively couple the processor circuit to a network; and a storage communicatively coupled to the processor circuit and arranged to store a sequence of instructions operative on the processor circuit to store a first detected data that represents sounds detected by the first microphone; receive a second detected data via the network that represents sounds detected by a second microphone of a second communications device; subtractively sum the first and second data to create a processed data; and transmit the processed data to a third communications device. Other embodiments are described and claimed herein. | 01-28-2016 |
20160028942 | Method and Apparatus for Supporting Image Processing, and Computer-Readable Recording Medium for Executing the Method - A support for image processing is provided, comprising: (a) detecting respective face regions from images consecutively photographed for a first person at predetermined time intervals by an image pickup unit to display images of the face regions detected in relation to the first person in a first region of a screen, and providing a user interface for indicating that a specific face image is selected from the face images of the first person displayed in the first region; (b) additionally displaying the specific face image through a second region adjacent to the first region; and (c) displaying a synthesized image using the specific face image as a representative face of the first person, when the specific face image displayed through the second region is selected. | 01-28-2016 |
20160028560 | HIGH SPEED RECEIVERS CIRCUITS AND METHODS - The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided. | 01-28-2016 |