Invensas Corporation Patent applications |
Patent application number | Title | Published |
20160068988 | Paddle for Materials Processing - A paddle for a plating system has a housing with a back portion, a front portion, a first side portion, a second side portion, a first end portion, and a second end portion. A first fin is disposed laterally along a first external surface of the first side portion and offset and coupled to the first external surface to define a first passageway between the first external surface of the first side portion and a first internal surface of the first fin for flow of the electrolyte through the first passageway. A second fin is disposed laterally along a second external surface of the second side portion and offset and coupled to the second external surface to define a second passageway between the second external surface of the second side portion and a second internal surface of the second fin for flow of the electrolyte through the second passageway. | 03-10-2016 |
20160049390 | Multiple bond via arrays of different wire heights on a same substrate - An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array. | 02-18-2016 |
20160049361 | MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES - A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond. | 02-18-2016 |
20160035656 | RECONFIGURABLE PoP - A microelectronic package ( | 02-04-2016 |
20160027761 | ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES - Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly. | 01-28-2016 |
20160020188 | SELECTIVE DIE ELECTRICAL INSULATION BY ADDITIVE PROCESS - Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces. | 01-21-2016 |
20150380377 | Multiple bond via arrays of different wire heights on a same substrate - Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires. | 12-31-2015 |
20150371938 | BACK-END-OF-LINE STACK FOR A STACKED DEVICE - Apparatus relating generally to a back-end-of-line (“BEOL”) stack. In this apparatus, the BEOL stack is configured to electrically couple at least one first electrical component to at least one second electrical component. First contacts are provided on a first side of the BEOL stack with a first pitch for providing a bondable surface for connection to the at least one first electrical component. Second contacts are provided on a second side of the BEOL stack with a second pitch for providing another bondable surface for connection to the at least one second electrical component. The second pitch may be larger than the first pitch. | 12-24-2015 |
20150364457 | Wafer Leveled Chip Packaging Structure and Method Thereof - A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias. | 12-17-2015 |
20150348928 | WIRE BOND SUPPORT STRUCTURE AND MICROELECTRONIC PACKAGE INCLUDING WIRE BONDS THEREFROM - A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases. | 12-03-2015 |
20150348873 | LOW CTE COMPONENT WITH WIRE BOND INTERCONNECTS - A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds. | 12-03-2015 |
20150303157 | Bowl-shaped solder structure - An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process. | 10-22-2015 |
20150279823 | BATCH PROCESS FABRICATION OF PACKAGE-ON-PACKAGE MICROELECTRONIC ASSEMBLIES - A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies. | 10-01-2015 |
20150270209 | STACKED DIE INTEGRATED CIRCUIT - An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another. | 09-24-2015 |
20150262910 | VIA STRUCTURE FOR SIGNAL EQUALIZATION - An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure. | 09-17-2015 |
20150262902 | INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTURE | 09-17-2015 |
20150255429 | Thermal Vias Disposed in a Substrate Proximate to a Well Thereof - An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity. | 09-10-2015 |
20150255364 | Thermal Vias Disposed in a Substrate Without a Liner Layer - An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has formed therein a plurality of vias. A liner layer is located on the substrate, including being located in a subset of the plurality of vias. At least one of the plurality of vias does not have the liner layer located therein. A thermally conductive material is disposed in the at least one of the plurality of vias to provide a thermal via structure. | 09-10-2015 |
20150213847 | Retention optimized memory device using predictive data inversion - A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition. | 07-30-2015 |
20150206815 | FINE PITCH BVA USING RECONSTITUTED WAFER WITH AREA ARRAY ACCESSIBLE FOR TESTING - A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly. into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit. | 07-23-2015 |
20150179619 | STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE - A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe. | 06-25-2015 |
20150162216 | TUNABLE COMPOSITE INTERPOSER - A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure. | 06-11-2015 |
20150155230 | CARRIER-LESS SILICON INTERPOSER USING PHOTO PATTERNED POLYMER AS SUBSTRATE - A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component. | 06-04-2015 |
20150146393 | HIGH STRENGTH THROUGH-SUBSTRATE VIAS - A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter. | 05-28-2015 |
20150145141 | Multiple Bond Via Arrays of Different Wire Heights on a Same Substrate - An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array. | 05-28-2015 |
20150145140 | Substrate-to-Carrier Adhesion Without Mechanical Adhesion Between Abutting Surfaces Thereof - Wafer to carrier adhesion without mechanical adhesion for formation of an IC. In such formation, an apparatus has a bottom surface of a substrate abutting a top surface of a support platform without adhesive therebetween. A material is disposed around the substrate and on the top surface of the support platform. The material is in contact with a side surface of the substrate to completely seal an interface as between the bottom surface of the substrate and the top surface of the support platform to retain abutment of the top surface and the bottom surface. | 05-28-2015 |
20150145116 | DIE STACKS WITH ONE OR MORE BOND VIA ARRAYS - An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die. | 05-28-2015 |
20150140815 | VIA IN SUBSTRATE WITH DEPOSITED LAYER - An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties. | 05-21-2015 |
20150132894 | Heat spreading substrate with embedded interconnects - Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another. | 05-14-2015 |
20150129646 | OFF SUBSTRATE KINKING OF BOND WIRE - An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Tensioning the wire using the bonding tool causes the wire to break and define an end. The lead then extends from the metal surface to the end. | 05-14-2015 |
20150123293 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURE THEREOF - A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge. | 05-07-2015 |
20150115472 | CO-SUPPORT FOR XFD PACKAGING - A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements. | 04-30-2015 |
20150097284 | Bowl-shaped solder structure - An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process. | 04-09-2015 |
20150096798 | Interconnections for a substrate associated with a backside reveal - An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member. | 04-09-2015 |
20150096790 | METHOD FOR PREPARING LOW COST SUBSTRATES - A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region. | 04-09-2015 |
20150091120 | REAR-FACE ILLUMINATED SOLID STATE IMAGE SENSORS - A microelectronic unit includes a semiconductor element having a front surface to which a packaging layer is attached, and a rear surface remote from the front surface. The element includes a light detector including a plurality of light detector element arranged in an array disposed adjacent to the front surface and arranged to receive light through the rear surface. The semiconductor element also includes an electrically conductive contact at the front surface connected to the light detector. The conductive contact includes a thin region and a thicker region which is thicker than the thin region. A conductive interconnect extends through the packaging layer to the thin region of the conductive contact, and a portion of the conductive interconnect is exposed at a surface of the microelectronic unit. | 04-02-2015 |
20150076714 | MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later. | 03-19-2015 |
20150069639 | Substrate-Less Stackable Package With Wire-Bond Interconnect - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 03-12-2015 |
20150056753 | Semiconductor Die Having Fine Pitch Electrical Interconnects - A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF | 02-26-2015 |
20150044823 | MICROELECTRONIC PACKAGE WITH INTEGRATED BEARING SURFACES - A method of forming a wire bond having a free end includes joining an end of a metal wire to a conductive element at a surface of a first component, the end of the metal wire being proximate a surface of a bonding tool adjacent an aperture through which the metal wire extends. A predetermined length of the metal wire is drawn out from the aperture. The surface of the bonding tool is used to plastically deform a region of the metal wire between the surface of the bonding tool and a metal element at the surface of the first component. The bonding tool then applies tension to the metal wire to cause a first portion of the metal wire having the end joined to the conductive element to detach from a remaining portion of the metal wire at the plastically deformed region. | 02-12-2015 |
20150043190 | EMBEDDED PACKAGING WITH PREFORMED VIAS - Microelectronic assemblies and methods of making the same are disclosed. In some embodiments, a microelectronic assembly includes a microelectronic element having edge surfaces bounding a front surface and contacts at the front surface; rigid metal posts disposed between at least one edge surface and a corresponding edge of the assembly, each metal post having a sidewall separating first and second end surfaces, the sidewalls have a root mean square (rms) surface roughness of less than about 1 micron; a encapsulation contacting at least the edge surfaces and the sidewalls; an insulation layer overlying the encapsulation; connection elements extending through the insulation layer, wherein at least some connection elements have cross sections smaller than those of the metal posts; a redistribution structure deposited on the insulation layer and electrically connecting first terminals with corresponding metal posts through the first connection elements, some metal posts electrically coupled with contacts of microelectronic element. | 02-12-2015 |
20150041988 | ULTRA HIGH PERFORMANCE INTERPOSER - An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via. | 02-12-2015 |
20150041208 | MICRO MECHANICAL ANCHOR FOR 3D ARCHITECTURE - Components and methods of making the same are disclosed herein. In one embodiment, a method of forming a component comprises forming metal anchoring elements at a first surface of a support element having first and second oppositely facing surfaces, the support element having a thickness extending in a first direction between the first and second surfaces, wherein each anchoring element has a downwardly facing overhang surface; and then forming posts having first ends proximate the first surface and second ends disposed above the respective first ends and above the first surface, wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the respective anchoring element and extends downwardly therefrom, and the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above the anchoring elements. | 02-12-2015 |
20150034371 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element. | 02-05-2015 |
20150017765 | METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly ( | 01-15-2015 |
20150017763 | Microelectronic Assembly With Thermally and Electrically Conductive Underfill - A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer | 01-15-2015 |
20150014688 | Thin Wafer Handling and Known Good Die Test Method - A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. | 01-15-2015 |
20140376200 | RELIABLE DEVICE ASSEMBLY - Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction. | 12-25-2014 |
20140362629 | SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT - A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements. | 12-11-2014 |
20140339702 | METAL PVD-FREE CONDUCTING STRUCTURES - Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd). | 11-20-2014 |
20140332980 | METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES - Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing. | 11-13-2014 |
20140328016 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic assembly | 11-06-2014 |
20140328015 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly ( | 11-06-2014 |
20140315384 | METHOD OF PROCESSING A DEVICE SUBSTRATE - Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate. | 10-23-2014 |
20140313834 | RETENTION OPTIMIZED MEMORY DEVICE USING PREDICTIVE DATA INVERSION - A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition. | 10-23-2014 |
20140268537 | IN-PACKAGE FLY-BY SIGNALING - In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region. | 09-18-2014 |
20140268491 | CAPACITORS USING POROUS ALUMINA STRUCTURES - Capacitors and methods of making the same are disclosed herein. In one embodiment, a capacitor comprises a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from the first surface towards the second surface, and each having pore having insulating material extending along a wall of the pore; a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by the insulating material extending along the walls of the pores. | 09-18-2014 |
20140264794 | LOW CTE INTERPOSER WITHOUT TSV STRUCTURE - A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element. | 09-18-2014 |
20140264730 | MICROELECTRONIC ELEMENTS WITH MASTER/SLAVE CONFIGURABILITY - A semiconductor chip that may be configured to function as either a master chip or a slave chip. The semiconductor chip may be included in a microelectronic assembly including a plurality of vertically stacked semiconductor chips, with each of the chips containing functional circuit blocks that enable each semiconductor chip to function as either a master chip or a slave chip under in accordance with a state input stored on the same chip, or received from another chip in the stacked assembly or from another component of a system in which the stacked assembly is configured to operate. | 09-18-2014 |
20140262457 | POROUS ALUMINA TEMPLATES FOR ELECTRONIC PACKAGES - Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements. | 09-18-2014 |
20140240938 | CARRIER-LESS SILICON INTERPOSER - An interposer can have conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component can include a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. Conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements. | 08-28-2014 |
20140240934 | MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICE - An electronic assembly is disclosed that includes a flexible insulating film, a semiconductor component that has a thickness of less than 50 micrometers, a conductive interconnect extending through the flexible insulating film, a second patterned metal wiring film adjacent, and a third patterned metal wiring film. The second patterned metal wiring film is electrically coupled with the third patterned metal wiring film through the conductive interconnect. The semiconductor component is coupled to the first patterned metal wiring film and at least one of the second patterned metal wiring film or the third patterned metal wiring film. | 08-28-2014 |
20140239514 | MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES - A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate. | 08-28-2014 |
20140239491 | MICROELECTRONIC UNIT AND PACKAGE WITH POSITIONAL REVERSAL - A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip. The reversed connections simplify routing, particularly where corresponding contacts of two chips are to be connected to common terminals on the package substrate. | 08-28-2014 |
20140220744 | METHOD OF MAKING WIRE BOND VIAS AND MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS - Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. | 08-07-2014 |
20140217619 | MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS AND STIFFENING LAYER - Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. | 08-07-2014 |
20140217617 | MULTI-DIE WIREBOND PACKAGES WITH ELONGATED WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening. | 08-07-2014 |
20140217607 | REDUCED STRESS TSV AND INTERPOSER STRUCTURES - A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall. | 08-07-2014 |
20140217587 | Wafer Leveled Chip Packaging Structure and Method Thereof - A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias. | 08-07-2014 |
20140213020 | SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING - A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support. | 07-31-2014 |
20140212996 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metalized vias and traces formed in contact with the second chip contacts. | 07-31-2014 |
20140203440 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURE THEREOF - A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge. | 07-24-2014 |
20140199811 | STACKABLE MICROELECTRONIC PACKAGE STRUCTURES - A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package. | 07-17-2014 |
20140185354 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 07-03-2014 |
20140179099 | METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING - Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects. | 06-26-2014 |
20140179061 | THIN WAFER HANDLING - A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment. | 06-26-2014 |
20140175671 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element. | 06-26-2014 |
20140175654 | SURFACE MODIFIED TSV STRUCTURE AND METHODS THEREOF - Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within the first portion of the opening, a second metal disposed within a second portion of the opening. The second metal may form at least part of a contact of the microelectronic element. | 06-26-2014 |
20140175440 | NON-CRYSTALLINE INORGANIC LIGHT EMITTING DIODE - Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier. | 06-26-2014 |
20140167279 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140167278 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140167267 | METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS - A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer. | 06-19-2014 |
20140159249 | METHOD AND STRUCTURES FOR VIA SUBSTRATE REPAIR AND ASSEMBLY - A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface. | 06-12-2014 |
20140159248 | HIGH PERFORMANCE PACKAGE ON PACKAGE - A microelectronic assembly can include a first package comprising a processor and a second package electrically connected to the first package. The second package can include two or more microelectronic elements each having memory storage array function and contacts at a respective element face, upper and lower opposite package faces, upper and lower terminals at the respective upper and lower package faces, and electrically conductive structure extending through the second package. At least portions of edges of respective microelectronic elements of the two or more microelectronic elements can be spaced apart from one another, so as to define a central region between the edges that does not overlie any of the element faces of the microelectronic elements of the second package. The electrically conductive structure can be aligned with the central region and can electrically connect the lower terminals with at least one of: the upper terminals or the contacts. | 06-12-2014 |
20140153210 | ADVANCED DEVICE ASSEMBLY STRUCTURES AND METHODS - A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. | 06-05-2014 |
20140141597 | CHIPS WITH HIGH FRACTURE TOUGHNESS THROUGH A METAL RING - A method of making an edge-reinforced microelectronic element is disclosed. The steps include mechanically cutting along dicing lanes of a substrate at least partially through a thickness thereof to form a plurality of edge surfaces extending away from a front surface thereof and forming a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces and extends onto the front surface. The front surface may have a plurality of contacts thereat and the substrate may embody a plurality of microelectronic elements. | 05-22-2014 |
20140141568 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-22-2014 |
20140131900 | MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL - A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer | 05-15-2014 |
20140131875 | Z-CONNECTION USING ELECTROLESS PLATING - In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor. | 05-15-2014 |
20140131851 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH TERMINALS ON DIELECTRIC MASS - A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element. | 05-15-2014 |
20140131836 | DIELECTRIC TRENCHES, NICKEL/TANTALUM OXIDE STRUCTURES, AND CHEMICAL MECHANICAL POLISHING TECHNIQUES - A portion of a conductive layer ( | 05-15-2014 |
20140120650 | REAR-FACE ILLUMINATED SOLID STATE IMAGE SENSORS - A microelectronic unit includes a semiconductor element having a front surface to which a packaging layer is attached, and a rear surface remote from the front surface. The element includes a light detector including a plurality of light detector element arranged in an array disposed adjacent to the front surface and arranged to receive light through the rear surface. The semiconductor element also includes an electrically conductive contact at the front surface connected to the light detector. The conductive contact includes a thin region and a thicker region which is thicker than the thin region. A conductive interconnect extends through the packaging layer to the thin region of the conductive contact, and a portion of the conductive interconnect is exposed at a surface of the microelectronic unit. | 05-01-2014 |
20140110832 | CO-SUPPORT CIRCUIT PANEL AND MICROELECTRONIC PACKAGES - A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package. | 04-24-2014 |
20140103535 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-17-2014 |
20140091459 | Chip-size, double side connection package and method for manufacturing the same - A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection. | 04-03-2014 |
20140077395 | INTEGRATED CIRCUIT DEVICE - An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer. | 03-20-2014 |
20140070423 | TUNABLE COMPOSITE INTERPOSER - A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure. | 03-13-2014 |
20140065772 | METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING - A programmable non-volatile device is made with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 03-06-2014 |
20140055970 | CO-SUPPORT COMPONENT AND MICROELECTRONIC ASSEMBLY - A component may be configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component may include a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals. The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate. | 02-27-2014 |
20140055941 | CO-SUPPORT SYSTEM AND MICROELECTRONIC ASSEMBLY - A system may include a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component may include a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate. | 02-27-2014 |
20140054763 | THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD - A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. | 02-27-2014 |
20140045285 | PARALLEL PLATE SLOT EMISSION ARRAY - In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection. | 02-13-2014 |
20140036454 | BVA INTERPOSER - A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds. | 02-06-2014 |
20140035153 | RECONSTITUTED WAFER-LEVEL PACKAGE DRAM - A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements. | 02-06-2014 |
20140027922 | VIA IN SUBSTRATE WITH DEPOSITED LAYER - An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties. | 01-30-2014 |
20140017878 | METHOD OF PROCESSING A DEVICE SUBSTRATE - Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate. | 01-16-2014 |
20140014894 | HIGH PERFORMANCE LIGHT EMITTING DIODE WITH VIAS - High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode. | 01-16-2014 |
20140008676 | OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICES - Optical enhancement of light emitting devices. In accordance with an embodiment of the present invention, an apparatus includes an optical enhancement layer comprising nanoparticles. Each of the nanoparticles includes an electrically conductive core surrounded by an electrically insulating shell. The optical enhancement layer is disposed on a top semiconductor layer in a preferred path of optical emission of a light emitting device. The nanoparticles may enhance the light emission of the light emitting device due to emitter-surface plasmon coupling. | 01-09-2014 |
20140008669 | PARALLEL PLATE SLOT EMISSION ARRAY - Parallel plate slot emission array. In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection. | 01-09-2014 |
20130334698 | MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONIC ELEMENTS THEREIN - A microelectronic assembly tolerant to misplacement of microelectronic elements therein may include a molded structure containing a plurality of microelectronic elements. Each microelectronic element has elements contacts having first and second dimensions in respective first and second directions that are transverse to each other, where the first dimension is at least twice the second dimension. In addition, the assembly may include a conductive redistribution layer including conductive vias extending through a dielectric layer to the element contacts of the respective microelectronic elements, where the conductive vias have a third dimension in a third direction and a fourth dimension in a fourth direction, and where the fourth direction is transverse to the third and first directions and the fourth dimension is greater than the third dimension. | 12-19-2013 |
20130328219 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer. | 12-12-2013 |
20130328186 | REDUCED STRESS TSV AND INTERPOSER STRUCTURES - A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall. | 12-12-2013 |
20130313716 | SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 11-28-2013 |
20130313012 | TSV FABRICATION USING A REMOVABLE HANDLING STRUCTURE - A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element. | 11-28-2013 |
20130288412 | HIGH YIELD SUBSTRATE ASSEMBLY - High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates. | 10-31-2013 |
20130247372 | MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICE - To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an interlayer insulating film allows for interlayer connection between plural wiring films insulated from one another with plural interlayer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the interlayer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 μm or smaller, and the multilayer wiring board itself for the electronic device has the flexibility. | 09-26-2013 |
20130224914 | METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer. | 08-29-2013 |
20130215121 | HEAT SPREADING SUBSTRATE - Heat spreading substrate. In accordance with an embodiment of the present invention, an apparatus includes a thermally conductive, electrically insulating regular solid, a first electrically conductive coating mechanically coupled to a first edge of the regular solid and a second electrically conductive coating mechanically coupled to a second edge of the regular solid. The first and the second electrically conductive coatings are electrically isolated from one another and the faces of the first electrically conductive coating, the second electrically conductive coating and the regular solid are substantially co-planar. The primary and secondary surfaces of the regular solid may be free of electrically conductive materials. | 08-22-2013 |
20130214296 | HEAT SPREADING SUBSTRATE WITH EMBEDDED INTERCONNECTS - Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another. | 08-22-2013 |
20130214295 | HEAT SPREADING SUBSTRATE - Heat spreading substrate. In an embodiment in accordance with the present invention, an apparatus includes a first conductive layer, a first insulating layer disposed in contact with the first conductive layer and a thermally conductive layer disposed in contact with the first insulating layer, opposite the first conductive layer. The faces of the first conductive layer, the first insulating layer and the thermally conductive layer are substantially co-planar; and a sum of widths of faces of the first conductive layer, the first insulating layer and the thermally conductive layer is greater than a height of the faces. The first conductive layer and the first insulating layer may include rolled materials. | 08-22-2013 |
20130207249 | ASSEMBLY HAVING STACKED DIE MOUNTED ON SUBSTRATE - Metal rerouting interconnects at one or more sides of a die or multiple die segments can form edge bonding pads for electrical connection. Insulation can be applied to surfaces of the die or multiple die segments after optional thinning and singulation, and openings can be made in the insulation to the electrical connection pads. After being placed atop one another in a stack, vertically adjacent die or die segments can be electrically interconnected using a flexible bond wire or bond ribbon attached to an electrical connection pad exposed within such opening, the bond wire or ribbon protruding horizontally, and an electrically conductive polymer, or epoxy, filaments or lines can be applied to the stack. | 08-15-2013 |
20130200533 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 08-08-2013 |
20130186944 | MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYER - An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer. | 07-25-2013 |
20130177281 | OPTICAL INTERPOSER - An optical interposer includes grooves ( | 07-11-2013 |
20130177274 | STRUCTURES FORMED USING MONOCRYSTALLINE SILICON AND/OR OTHER MATERIALS FOR OPTICAL AND OTHER APPLICATIONS - An interposer includes grooves ( | 07-11-2013 |
20130175699 | STACKABLE MICROELECTRONIC PACKAGE STRUCTURES - A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package. | 07-11-2013 |
20130168843 | EMBEDDED HEAT SPREADER FOR PACKAGE WITH MULTIPLE MICROELECTRONIC ELEMENTS AND FACE-DOWN CONNECTION - A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate. | 07-04-2013 |
20130134602 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-30-2013 |
20130128674 | METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING RELATED APPLICATION DATA - A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 05-23-2013 |
20130127364 | FRONT FACING PIGGYBACK WAFER ASSEMBLY - Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching. | 05-23-2013 |
20130126921 | INVERTED OPTICAL DEVICE - Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. A flip wafer is attached to the plurality of light emitting diodes, away from the carrier wafer and the carrier wafer is removed. The plurality of light emitting diodes may be singulated to form individual light emitting diode devices. | 05-23-2013 |
20130126867 | HIGH YIELD SUBSTRATE ASSEMBLY - High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates. | 05-23-2013 |
20130122747 | CAVITIES CONTAINING MULTI-WIRING STRUCTURES AND DEVICES - An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another. | 05-16-2013 |
20130120023 | NON-VOLATILE ONE-TIME-PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY CONFIGURATION CIRCUIT - A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications. | 05-16-2013 |
20130119117 | BONDING WEDGE - A bonding wedge particularly suitable for making wire off-die interconnects includes an aperture opening onto a notch or pocket adjacent to the rear of a foot. The foot includes a heel portion and a toe portion. When the bonding wedge is in use, a wire is fed from feedstock through the aperture and the notch or pocket, and passes beneath the foot and extends beyond the toe. The toe is configured to mitigate upward displacement of the free end of the wire during the bonding process. | 05-16-2013 |
20130118784 | HIGH STRENGTH THROUGH-SUBSTRATE VIAS - A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter. | 05-16-2013 |
20130114235 | EMI SHIELD - An EMI shield can be formed directly on a component, e.g., an unpackaged or packaged semiconductor die, by depositing and curing a curable composition which includes electrically conductive particles and a carrier. In examples, the shield can be configured as a grid or net of electrically conductive traces or lines. The curable electrically conductive material may be applied to the component surface in a flowable form and cured or allowed to cure to form the electrically conductive shield. The shield can be electrically coupled to contacts on an underlying circuit panel or support. The coupling material may be a conductive adhesive, and may be or may include a material the same as, or similar to, the shield material. | 05-09-2013 |
20130107635 | COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL | 05-02-2013 |
20130107630 | NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIVE COUPLING | 05-02-2013 |
20130095610 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 04-18-2013 |
20130093088 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds. | 04-18-2013 |
20130093087 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 04-18-2013 |
20130083584 | STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE - A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe. | 04-04-2013 |
20130083583 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements. | 04-04-2013 |
20130083582 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082398 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082397 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region. | 04-04-2013 |
20130082396 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082395 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082394 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package. | 04-04-2013 |
20130082391 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals. | 04-04-2013 |
20130082390 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082389 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082381 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082380 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082375 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082374 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130037312 | HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATION - A method for making a microelectronic substrate includes forming a pattern of a selected metallic layer of an in-process unit using laser ablation such that the pattern corresponds to desired locations for conductive features. Conductive material is than added to the in-process unit by a process that uses the pattern to concentrate application of the conductive material to the in-process unit such that the conductive material forms conductive features of the substrate according to the pattern. The step forming a pattern of a selected metallic layer of an in-process unit using laser ablation can includes the use of a UV laser, a CO2 or an excimer laser. | 02-14-2013 |
20130015591 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, first, second, third, and fourth microelectronic elements, and a plurality of terminals exposed at the second surface. Each microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. The front surfaces of the microelectronic elements can be arranged in a single plane parallel to the first surface. Each microelectronic element can have a column of contacts exposed at the front surface and arranged along respective first, second, third, and fourth axes. The first and third axes can be parallel to one another. The second and fourth axes can be transverse to the first and third axes. The microelectronic package can also include electrical connections extending from at least some of the contacts of each microelectronic element to at least some of the terminals. | 01-17-2013 |
20130015590 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals. | 01-17-2013 |
20120297275 | CIRCUIT AND TECHNIQUE FOR REDUCING PARITY BIT-WIDTHS FOR CHECK BIT AND SYNDROME GENERATION FOR DATA BLOCKS THROUGH THE USE OF ADDITIONAL CHECK BITS TO INCREASE THE NUMBER OF MINIMUM WEIGHTED CODES IN THE HAMMING CODE H-MATRIX - A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry. | 11-22-2012 |
20120140564 | NON-VOLATILE ONE-TIME-PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY CONFIGURATION CIRCUIT - A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications. | 06-07-2012 |