MEDIATEK SINGAPORE PTE. LTD. Patent applications |
Patent application number | Title | Published |
20160112721 | Method of Sub-Prediction Unit Prediction in 3D Video Coding - A method for a three-dimensional encoding or decoding system incorporating restricted sub-PU level prediction is disclosed. In one embodiment, the sub-PU level prediction associated with inter-view motion prediction or view synthesis prediction is restricted to the uni-prediction. In another embodiment, the sub-PU partition associated with inter-view motion prediction or view synthesis prediction is disabled if the sub-PU partition would result in sub-PU size smaller than the minimum PU split size or the PU belongs to a restricted partition group. The minimum PU split size may correspond to 8×8. The restricted partition group may correspond to one or more asymmetric motion partition (AMP) modes. | 04-21-2016 |
20160021393 | Method of Error-Resilient Illumination Compensation for Three- Dimensional Video Coding - A method of illumination compensation for three-dimensional or multi-view encoding and decoding. The method incorporates an illumination compensation flag only if the illumination compensation is enabled and the current coding unit is processed by one 2N×2N prediction unit. The illumination compensation is applied to the current coding unit according to the illumination compensation flag. The illumination compensation flag is incorporated when the current coding unit is coded in Merge mode without checking whether a current reference picture is an inter-view reference picture. | 01-21-2016 |
20160006267 | WIRELESS OR WIRED POWER DELIVERY USING A CONTROLLABLE POWER ADAPTER - Some embodiments relate to a system that includes a first device which is a wireless power transmitter or mobile device and a power adapter external to the first device. The power adapter is configured to receive a control signal and to control a DC output voltage of the power adapter based upon the control signal. The first device is configured to send the control signal to the power adapter. | 01-07-2016 |
20150358181 | CHANNEL ESTIMATION METHOD AND ASSOCIATED DEVICE FOR ESTIMATING DATA CHANNEL OF DATA RESOURCE ELEMENT OF PHYSICAL RESOURCE BLOCK FOR OFDM SYSTEM - A channel estimation method estimates a data channel of a data resource element of a physical resource block in a time-frequency domain. The method includes: utilizing a detection circuit to perform a first physical resource block bundling detection in a first direction of the time-frequency domain to detect if at least one neighboring physical resource block is allowed to be bundled with the physical resource block, and accordingly generating a first physical resource block bundling detection result; determining a physical resource block processing range according to at least the first physical resource block bundling detection result, wherein at least the physical resource block is included in the physical resource block processing range; obtaining a plurality of pilot channels for pilot resource elements in the physical resource block processing range; and estimating the data channel of the data resource element according to the pilot channels. | 12-10-2015 |
20150357827 | MULTI-MODE WIRELESS POWER TRANSMITTER - Some embodiments relate to a multi-mode wireless power transmitter. The transmitter includes an inverter configured to produce at its output a first signal having a first frequency or a second signal having a second frequency. The transmitter also includes a first transmit coil coupled to the output of the inverter and configured to wirelessly transmit power at the first frequency. The transmitter also includes a second transmit coil coupled to the output of the inverter and configured to wirelessly transmit power at the second frequency. The transmitter further includes at least one matching network coupled to the first transmit coil, the second transmit coil, and the output of the inverter. The at least one matching network is configured to provide power to the first transmit coil in response to the first signal and inhibit providing power to the second transmit coil in response to the first signal. | 12-10-2015 |
20150350623 | Method and Apparatus for Efficient Coding of Depth Lookup Table - A method and apparatus for encoding and decoding depth lookup table (DLT) using a constrained table value range are disclosed. For a decoder, a constrained table value range from a minimum table value to a maximum table value of the DLT is decoded from the coded DLT information. Bit map values for depth values in a depth range from (the minimum table value+1) to (the maximum table value−1) are then decoded. The bit map values indicate whether the depth values are in the DLT respectively. The DLT for the current depth map can be reconstructed based on the constrained table value range and the bit map values for the depth values in the depth range. For an encoder, a constrained table value range from a minimum table value to a maximum table value of the DLT is determined and encoded the DLT into coded DLT information. | 12-03-2015 |
20150312804 | METHOD FOR DYNAMICALLY ADJUSTING CHANNEL BANDWIDTH IN WIRELESS COMMUNICATIONS SYSTEMS - A method of reducing the usable channel bandwidth and increasing the channel bandwidth at run time is provided. The method allows a receiving wireless communications device to inform its corresponding transmitting communications device to either increase, reduce, or maintain the number of usable narrow band channels for the succeeding frame exchange. In a wireless communications channel, channel reduction is accomplished by using a usable channel indicator in a response frame responding to the preceding receiving frame. The usable channel indicator is the means for the receiving communications device to inform the transmitting communications device the preferred narrow band channels that it deems having good channel characteristics. | 10-29-2015 |
20150304670 | METHOD AND APPARATUS FOR INTRA MODE DERIVATION AND CODING IN SCALABLE VIDEO CODING - A method and apparatus of Intra mode coding for a scalable video coding system are disclosed. For a current Intra-coded block in the enhancement layer (EL), predictive coding is applied to the current Intra mode based on the base layer (BL) coding mode associated with the co-located block in the BL and neighboring coding modes associated with neighboring blocks of the current block in the EL. The neighboring blocks of the current block in the EL comprise a left block adjacent to a left side of the current block and a top block adjacent to a top side of the current block. One or more most probable modes (MPMs) can be derived from the neighboring coding modes and the BL coding mode, and the MPMs is then used for predictive coding of the current Intra mode. | 10-22-2015 |
20150304662 | METHOD AND APPARATUS FOR BLOCK PARTITION OF CHROMA SUBSAMPLING FORMATS - A method and apparatus for video data processing for video in YUV422 or YUV 444 formats are disclosed. In one embodiment, for a 2N×2N luma coding unit (CU) in YUV422 format, the transform process partitions residue data corresponding to the 2N×2N luma CU and the N×2N chroma CU into square luma and chroma transform units (TUs). The residue data associated with the luma and the chroma CUs are generated by applying prediction process to the luma CU and the chroma CU. The transform process is independent of prediction block size or prediction mode associated with the prediction process. In another embodiment, the prediction process splits the CU into two prediction blocks. Transform process is applied on the chroma residue data corresponding to the chroma CU to form one or more chroma TUs, wherein the transform process is dependent on CU size and prediction block size, or CU size and prediction mode. | 10-22-2015 |
20150264347 | METHOD AND APPARATUS OF MOTION VECTOR DERIVATION 3D VIDEO CODING - A method and apparatus for three-dimensional and multi-view video coding are disclosed, where the motion vector (MV) or disparity vector (DV) candidate list construction process for a block depends on whether the target reference picture corresponds to an inter-view reference picture or whether the inter-view candidate refers to an inter-view reference picture. In one embodiment, an MV or DV candidate list for a block coded in Merge mode is constructed, and an inter-view candidate in the MV or DV candidate list is set lower than the first candidate position if the inter-view candidate refers to an inter-view reference picture. In another embodiment, an MV or DV candidate list for a block coded in advanced motion vector prediction mode is constructed, and an inter-view candidate is set lower than the first candidate position if the inter-view candidate refers to an inter-view reference picture. | 09-17-2015 |
20150256138 | FULLY DIFFERENTIAL CLASS A/AB AMPLIFIER AND METHOD THEREOF - A differential amplifier and a method thereof are described. The method, adopted by a differential amplifier, includes: generating first stage differential output signals based on input differential signals; providing, by a current source, a bias current with a desired quiescent current; biasing first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair which receives first stage differential input signals; mirroring the first and second currents to first and second push transistors which are connected to first and second pull transistors in series, respectively; and biasing the first and second pull transistors with the mirrored first and second currents, respectively; wherein each pair of serial connected push and pull transistors are complimentary and the two pairs of push and pull transistors output second stage differential output signals. | 09-10-2015 |
20150237324 | Method of Depth Based Block Partitioning - A method of simplified depth-based block partitioning (DBBP) for three-dimensional and multi-view video coding is disclosed. In one embodiment, the derivation of a representative value of a corresponding depth block or a reference texture block in a reference view for generating a segmentation mask and selecting a block partition are unified. In another embodiment, the first representative value, the second representative value, or both are calculated from partial samples of the corresponding depth block or the reference texture block. In yet another embodiment, a first representative value for first samples in a first partitioned block of the corresponding depth block or the reference texture block, and a second representative value for second samples in a second partitioned block of the corresponding depth block or the reference texture block for each of block partition candidates are determined. | 08-20-2015 |
20150228256 | IMAGE DATA PROCESSING METHOD OF MULTI-LEVEL SHUFFLES FOR MULTI-FORMAT PIXEL AND ASSOCIATED APPARATUS - Embodiments of the invention disclose an image data processing method and an image data processing apparatus and a method and an apparatus for image data processing. The image data processing method includes the following steps: receiving image data, wherein said image data is in a first pixel format; shuffling said image data according to a relationship between the first pixel format and a second pixel format to generate shuffled data; and compressing said shuffled data by a compression module which is suitable for compressing image data in said second pixel format so as to generate compressed data. | 08-13-2015 |
20150195570 | Method of Texture Dependent Depth Partition - A method of improved texture-partition-dependent depth partition is disclosed. First, the available texture partitions for a collocated texture block are classified into two or more groups, and a set of candidate depth partitions is determined for each group. In one embodiment, at least one set of the candidate depth partitions contain more than one candidate depth partition and less than all candidate depth partitions. In another embodiment, the collocated texture blocks are classified into two groups, and one of the two groups includes the N×N texture partition and at least another texture partition. In yet another embodiment, the collocated texture blocks are classified into three groups or more. A current depth partition for the current depth block is then selected from a corresponding set of candidate depth partitions according to a corresponding group that a current texture partition associated with the collocated texture block belongs. | 07-09-2015 |
20150189323 | Method of Three-Dimensional and Multiview Video Coding Using a Disparity Vector - A method and apparatus for a three-dimensional or multi-view video encoding or decoding system are disclosed, where a three-dimensional coding tool relying on a disparity vector are adaptively applied depending on whether the inter-view reference picture pointed by the disparity vector is in the reference list associated with the current slice. The three-dimensional coding tool may correspond to the Inter-View Motion Prediction (IVMP) or View Synthesis Prediction (VSP). If the inter-view reference picture pointed by the DV is not in the current reference list associated with the current slice, the selected three-dimensional coding tool is disabled for the current block. If the inter-view reference picture pointed by the DV is in the current reference list associated with the current slice, the selected three-dimensional coding tool can be applied to the current block. | 07-02-2015 |
20150131722 | Method and Apparatus of Improved Intra Luma Prediction Mode Coding - A method of video coding using intra prediction for a block of video data is disclosed. The intra prediction modes are ranked according to a priority order associated with the block size. One or more tables are used, where the tables ranks the intra prediction modes according to a first priority order for the block having a first block size and ranks the intra prediction modes according to a second priority order for the block having a second block size. Two or more neighboring intra prediction modes corresponding to two or more neighboring blocks are received, where each neighboring block has a neighboring block size corresponding to the first block size or the second block size. A highest-priority mode among said two or more neighboring intra prediction modes is selected as the most probable mode. The current mode is then encoded or decoded using the most probable mode as a predictor. | 05-14-2015 |
20150131543 | COMMUNICATION DEVICE AND FREQUENCY OFFSET CALIBRATING METHOD - A frequency offset calibrating method for use in a communication device connected to a communication system is provided. The method includes the following steps: determining a discontinuous reception cycle; awakening the communication device to a working mode from a sleep mode every discontinuous reception cycle and keep the communication device in the working mode for a first time period to receive a paging indication channel message from a communication network periodically; and awakening the communication device at a second time period other than the first time period during a first discontinuous reception cycle, thereby estimating an accumulated timing offset of a clock signal of the communication device and calibrating a frequency offset of the clock signal. In the invention, the accumulated timing offset of the clock signal can be calibrated efficiently to increase the reception performance of the page indication channel message with simple implementation and low hardware cost. | 05-14-2015 |
20150121011 | STORAGE SYSTEM HAVING TAG STORAGE DEVICE WITH MULTIPLE TAG ENTRIES ASSOCIATED WITH SAME DATA STORAGE LINE FOR DATA RECYCLING AND RELATED TAG STORAGE DEVICE - A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated. | 04-30-2015 |
20150063510 | COMMUNICATION UNIT AND SLICED RADIO FREQUENCY MODULE THEREFOR - A communication unit includes at least one divider module arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal, and a plurality of sliced RF modules. Each of the plurality of sliced RF modules includes: an input for receiving a clock signal; a timing synchronisation module arranged to receive the divided representation of the RF signal and synchronise the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and at least one logic module operably coupled to the timing synchronisation module and arranged to receive the clock signal and a synchronised output from the timing synchronisation module. A combiner port is arranged to couple a number of synchronised outputs from the plurality of sliced RF modules. | 03-05-2015 |
20150056939 | INTEGRATED CIRCUIT FOR COMMUNICATION - The present invention provides an integrated circuit for communication, e.g., for mobile radio-frequency (RF) telecommunication, including a resonator, a main amplifier, a matching circuit, a blocker detector, a mixer circuit, and a translation filter. The resonator provides conversion from single-end to differential, and filtering function for rejecting blockers at harmonics of local oscillation signal. The blocker detector detects occurrence of blocker; according to whether blocker exists, the main amplifier amplifies differential signal of the resonator by different gains, and the mixer circuit mixes amplified signal with different numbers of mixers. The translation filter contributes to rejection of blockers closed to in-band by providing a first pass band which is translated to a second pass band by the mixer circuit. The matching circuit provides impedance match. | 02-26-2015 |
20150049817 | Method and Apparatus for Compressing Coding Unit in High Efficiency Video Coding - In HEVC (High Efficiency Video Coding), a 2N×2N coding unit can be partitioned into various partition types hierarchically. The coding system uses a criterion to determine the best partition, where RD-rate is often used as the criterion. N×N partition at level k becomes redundant if 2N×2N at level k+1 will be evaluated. In order to eliminate the above redundancy, the allowable partition sizes are constrained according to a method previously disclosed. In the current invention, the complexity is further reduced. According to one embodiment, N×N partition is not allowed for any INTER mode regardless of the coding unit size. Furthermore, flexibility is provided so that either the method and apparatus with further complexity reduction can be selected or an alternative method and apparatus can be selected. Syntaxes to support embodiments according to the present invention are also disclosed. | 02-19-2015 |
20150030067 | METHOD AND APPARATUS FOR CODED BLOCK FLAG CODING IN HIGH EFFICIENCY VIDEO CODING - A method and an apparatus for decoding of a video bitstream are disclosed. In one embodiment, the method comprises: decoding a first coded block flag (cbf) of the color component indicating whether a current coding unit (CU) of the color component has at least one non-zero transform coefficient ( | 01-29-2015 |
20150010049 | METHOD OF DEPTH INTRA PREDICTION USING DEPTH MAP MODELLING - A method of depth map coding for a three-dimensional video coding system incorporating extended reconstructed neighboring depth samples is disclosed. The depth block is partitioned into one or more segments. A prediction value for each segment is derived based on reconstructed neighboring depth samples. The reconstructed neighboring depth samples for at least one segment comprise at least one reconstructed sample from an extended top neighboring row or an extended left neighboring column. The extended top neighboring row includes at least one extended top-row reconstructed depth sample located adjacent to top side of a second depth block adjacent to right side of the current depth block. The extended left neighboring column includes at least one extended left-column reconstructed depth sample located adjacent to left side of a third depth block adjacent to bottom side of the current depth block. | 01-08-2015 |
20140376420 | COMMUNICATIONS APPARATUS USING TRAINING SIGNAL INJECTED TO TRANSMISSION PATH FOR TRANSMISSION NOISE SUPPRESSION/CANCELLATION AND RELATED METHOD THEREOF - A communications apparatus has a transmitter path and a training signal generator. The transmitter path is arranged for transmitting a transmission signal. The training signal generator is arranged for generating a training signal in a receiver band, and injecting the training signal to the transmitter path. The training signal is utilized to obtain an accurate estimation of the channel which helps to suppress transmission noise comprised in at least one received signal of the communications apparatus, and the transmission noise is generated by the transmitter path. Specifically, the communications apparatus further has a receiver path and a transmission noise suppression device. The receiver path is arranged for receiving a received signal. The transmission noise suppression device is arranged for receiving the training signal, and processing the received signal to suppress transmission noise comprised in the received signal according to at least the training signal. | 12-25-2014 |
20140362924 | METHOD AND APPARATUS FOR SIMPLIFIED MOTION VECTOR PREDICTOR DERIVATION - A method and apparatus for deriving a motion vector predictor (MVP) candidate set for motion vector coding of a current block. Embodiments according to the present invention determine a redundancy-removed spatial MVP candidate set by removing any redundant MVP candidate from the spatial MVP candidate set. The redundancy-removal process does not apply to the temporal MVP candidate. In another embodiment of the present invention, a redundancy-removed spatial-temporal MVP candidate set is determined and the number of candidates in the redundancy-removed spatial-temporal MVP candidate set is checked to determine whether it is smaller than a threshold. If the number of candidates is smaller than the threshold, a zero motion vector is added to the redundancy-removed spatial-temporal MVP candidate set. The redundancy-removed spatial-temporal MVP candidate set is then provided for encoding or decoding of the motion vector of the current block. | 12-11-2014 |
20140355667 | METHOD AND APPARATUS OF LUMA-BASED CHROMA INTRA PREDICTION - A method and apparatus for luma-based chroma intra prediction for a current chroma block are disclosed. The chroma intra predictor is derived from reconstructed luma pixels of a current luma block according to the chroma sampling format. Depending on the chroma sampling format, either sub-sampling, down-sampling or no processing is applied to the reconstructed luma pixels in horizontal or vertical direction. The information associated with the chroma sampling format can be incorporated in the sequence parameter set (SPS), the picture parameter set (PPS), the adaptation parameter set (APS) or the slice header of a video bitstream. | 12-04-2014 |
20140355576 | METHOD FOR COORDINATING BEACON TRANSMISSION TIMES IN WIRELESS LOCAL AREA NETWORK AND COMMUNICATIONS SYSTEM UTILIZING THE SAME - A method for coordinating beacon transmission times for a plurality of access points (APs) in a wireless local area network includes generating a first neighboring AP list listing one or more neighboring AP(s) of a first AP, deriving a first beacon transmission time for the first AP according to the first neighboring AP list, and transmitting a beacon message at the first beacon transmission time by the first AP. The first AP and the one or more neighboring AP(s) are arranged to form a Hot Spot that offers network services over the wireless local area network. | 12-04-2014 |
20140350872 | TRANSMIT POWER MEASUREMENT APPARATUS HAVING PROGRAMMABLE FILTER DEVICE THAT IS SET AT LEAST BASED ON FREQUENCY RESPONSE OF TRANSMIT POWER DETECTION PATH AND RELATED TRANSMIT POWER MEASUREMENT METHOD THEREOF - A transmit power measurement apparatus includes a transmit power detection path, a compensation circuit and a tracking circuit. The compensation circuit includes a programmable filter device and a compensation controller. The programmable filter device generates a filter output. The compensation controller sets the programmable filter device at least based on a frequency response of the transmit power detection path. The tracking circuit generates a transmit power tracking result at least based on the filter output. | 11-27-2014 |
20140328396 | METHOD AND APPARATUS FOR CONTEXT ADAPTIVE BINARY ARITHMETIC CODING OF SYNTAX ELEMENTS - A method and apparatus for context-adaptive Start arithmetic coding (CABAC) of a syntax element are disclosed. The bin string corresponding to a syntax element is processed by context-adaptive arithmetic coding with a reduced number of contexts using the bin-level bypass mode, bin-level context sharing, or both. The syntax element belongs to a group comprising merge_idx, ref_idx_lc/ref_idx_10/ref_idx_11, pred_type, and cu_qp_delta. In one embodiment, the syntax element corresponds to merge_idx and three bins of the bin string with bin indices corresponding to 1, 2 and 3 are coded in the bin by-pass mode. In another embodiment, the syntax element corresponds to ref_idx_lc/ref_idx_10/ref_idx_11 and one or more bins of the bin string with bin indices larger than 1 for larger than 2 are coded in the bin bypass mode. | 11-06-2014 |
20140325153 | MULTI-HIERARCHY INTERCONNECT SYSTEM AND METHOD FOR CACHE SYSTEM - A multi-hierarchy interconnect system for a cache system having a tag memory and a data memory includes an address interconnect scheduling device and a data interconnect scheduling device. The address interconnect scheduling device performs a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory. The data interconnect scheduling device performs a data bank arbitration to schedule data requests to a plurality of data banks of the data memory. Besides, a multi-hierarchy interconnect method for a cache system having a tag memory and a data memory includes: performing a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory, and performing a data bank arbitration to schedule data requests to a plurality of data banks of the data memory. | 10-30-2014 |
20140323043 | METHOD FOR CONTROLLING AN ANTENNA NETWORK QUALITY FACTOR OF A NEAR FIELD COMMUNICATION DEVICE WITHOUT CHANGING MATCHING NETWORK, AND ASSOCIATED APPARATUS - A method for controlling an antenna network quality factor of an NFC device includes: determining whether a first data rate or a second data rate should be used for data communication during different time intervals, respectively; and when it is determined that the first data rate should be used during a first time interval of the time intervals, controlling a set of internal resistors positioned within a chip of the NFC device to have a first configuration during the first time interval, in order to adjust the antenna network quality factor. More particularly, the method further includes: when it is determined that the second data rate should be used during a second time interval of the time intervals, controlling the set of internal resistors to have a second configuration during the second time interval, in order to adjust the antenna network quality factor. An associated apparatus is also provided. | 10-30-2014 |
20140323041 | METHOD FOR CONTROLLING A MODULATION INDEX OF A NEAR FIELD COMMUNICATION DEVICE WITH AID OF DYNAMIC CALIBRATION, AND ASSOCIATED APPARATUS - A method for controlling a modulation index of a near field communication (NFC) device includes: in a calibration mode of the NFC device, temporarily coupling a receiver of the NFC device to a transmitter of the NFC device to form a probing path between the receiver and the transmitter; and in the calibration mode of the NFC device, dynamically adjusting at least one portion of a plurality of modulation parameters corresponding to the modulation index according to probed results of outputs of the transmitter, in order to calibrate the modulation index, for use of transmitting through the transmitter in a normal mode of the NFC device. An associated apparatus is also provided. | 10-30-2014 |
20140320177 | CIRCUIT FOR DRIVING HIGH-SIDE TRANSISTOR - A circuit for driving a transistor includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node. | 10-30-2014 |
20140315598 | ELECTRONIC DEVICE - Electronic devices are disclosed. The electronic device includes a circuit board. The circuit board contains a first transceiver module pad configured for soldering a first transceiver module thereon; and a second transceiver module pad configured for soldering a second transceiver module thereon. The first transceiver module is different from the second transceiver module, and layouts of the first and second transceiver module pads are the same. | 10-23-2014 |
20140314128 | Methods for LTE Cell Search with Large Frequency Offset - Methods and devices for LTE cell search with large frequency offset are disclosed. In one embodiment of the invention, a UE divides the received signals into multiple frequency bins and transforms the signals into frequency domain through FFT. The UE performs correlating measures between the received signals and reference signals. The UE then performs an adaptive multi-try based peak selection such that the number of candidate is reduced. In one embodiment of the invention, the multi-try number is adaptively adjusted based on the channel condition. In one embodiment of the invention, the threshold of the peak selection is adaptively adjusted. In other embodiments of the invention, the UE performs non-coherent accumulation and selects a predefined number of coarse bin candidates. The number of non-coherent accumulation is adaptively adjusted. In another embodiment of the invention, the UE performs fractional frequency offset estimation and selects a fine bin candidate. | 10-23-2014 |
20140313947 | WIRELESS COMMUNICATION UNIT, RADIO FREQUENCY MODULE AND METHOD THEREFOR - A wireless communication unit includes at least one antenna port; a transmitter and a receiver operably coupled to the at least one antenna port via a duplexer; wherein the duplexer includes a dynamically reconfigurable phase shift network that includes: at least one tunable radio frequency (RF) component; and at least one switch operably coupled to the tunable RF component and controllable to reconfigure the dynamically reconfigurable phase shift network to selectively support both normal and reverse duplexer modes of operation for RF signals passing there through. | 10-23-2014 |
20140312948 | METHOD AND SYSTEM FOR SYNCHRONIZING THE PHASE OF A PLURALITY OF DIVIDER CIRCUITS IN A LOCAL-OSCILLATOR SIGNAL PATH - A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits. | 10-23-2014 |
20140301655 | IMAGE DECODING METHODS AND IMAGE DECODING DEVICES - Image decoding methods are provided. First, an input bitstream corresponding to an image is acquired and an entropy decoding operation is performed on a block to be decoded in the input bitstream to obtain a decoding result, wherein the decoding result includes at least one coefficient having a corresponding block position information and coefficient value. It is then determined whether the coefficient value of the at least one coefficient is zero. When the coefficient value of the at least one coefficient is not zero, the at least one coefficient is determined as an non-zero coefficient and the block position information and coefficient value corresponding to the non-zero coefficient are stored to an external storage device. When the coefficient value of the at least one coefficient is zero, the block position information and coefficient value corresponding to the at least one coefficient are not stored. | 10-09-2014 |
20140292387 | LOCK DETECTOR BASED ON CHARGE PUMP - A phase lock loop having a lock detector is provided. The lock detector is based on a replica charge pump and includes: a charge pump, a filter and a comparing circuit. The charge pump is arranged for providing an output according to a phase difference between an output signal and a reference signal. The filter is coupled to the charge pump, and is arranged for filtering the output of the charge pump to generate a filtered output voltage. The comparing circuit is coupled to the filter, and is arranged for comparing the filtered output voltage with a threshold setting to generate a lock indication signal to indicate whether the output signal is locked to the reference signal. | 10-02-2014 |
20140292372 | LOW POWER CLOCK GATING CIRCUIT - A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate. | 10-02-2014 |
20140281843 | DECODING APPARATUS WITH ADAPTIVE CONTROL OVER EXTERNAL BUFFER INTERFACE AND TURBO DECODER AND RELATED DECODING METHOD THEREOF - A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified. | 09-18-2014 |
20140281789 | ADAPTIVE MULTI-CORE, MULTI-DIRECTION TURBO DECODER AND RELATED DECODING METHOD THEREOF - A turbo decoder includes a plurality of decoder cores arranged for parallel decoding of a plurality of code segments of a code block in an iteration. Each of the decoder cores is arranged to decode a corresponding code segment according to a sliding window having a window size smaller than a length of the corresponding code segment in most cases, and sequentially generate a plurality of decoded soft outputs each derived from decoding an encoded soft input selected from the corresponding code segment by the sliding window. | 09-18-2014 |
20140273907 | METHOD AND APPARATUS FOR CONFIGURING A FREQUENCY DEPENDENT I/Q IMBALANCE COMPENSATION FILTER - A method of configuring at least one frequency dependent (FD), in-phase/quadrature (I/Q), imbalance compensation filter within a radio frequency (RF) module is described. The method includes applying an input signal to an input of the RF module, receiving a filtered I-path signal for the RF module and deriving at least one I-path filtering estimate value therefrom, receiving a filtered Q-path signal for the RF module and deriving at least one Q-path filtering estimate value therefrom, and configuring the at least one FD I/Q imbalance compensation filter based at least partly on at least one ratio between the derived I-path and Q-path filtering estimate values. | 09-18-2014 |
20140254720 | PA CELL, PA MODULE, WIRELESS COMMUNICATION UNIT, RF TRANSMITTER ARCHITECTURE AND METHOD THEREFOR - A power amplifier cell includes a first input arranged to receive an in-phase control signal, a second input arranged to receive a quadrature control signal, an input stage arranged to output a drive signal based at least partly on the received in-phase and quadrature control signals, and an output stage arranged to receive at an input thereof the drive signal output by the input stage, and to generate an output signal for the power amplifier cell in response to the received drive signal. | 09-11-2014 |
20140253249 | CIRCUIT FOR PROVIDING A FLAT GAIN RESPONSE OVER A SELECTED FREQUENCY RANGE AND METHOD OF USE - An integrated circuit is disclosed. The integrated circuit includes an amplifier and a capacitor array coupled to the amplifier. The capacitor array is configured to be coupled in parallel to an inductor that is external to the integrated circuit, and the capacitor array and the external inductor comprise a tank circuit. The integrated circuit includes a resistor array coupled in parallel with the capacitor array. The resistor array is utilized to provide an overall frequency response of the capacitor array and resistor array that is opposite of a frequency response of the external inductor over a predetermined frequency range. | 09-11-2014 |
20140246923 | OPEN-CIRCUIT IMPEDANCE CONTROL OF A RESONANT WIRELESS POWER RECEIVER FOR VOLTAGE LIMITING - A resonant wireless power (RWP) receiver is provided that includes an inductor element that couples with a resonant wireless power source. A capacitor arrangement is coupled to the inductor element altering the open-circuit impedance of the RWP receiver to reduce the ac voltage under certain defined situations. The capacitor arrangement includes a plurality capacitors tuned to a control ac voltage in the RWP receiver. | 09-04-2014 |
20140223158 | BOOTING DISPLAY CONTROL METHOD AND RELATED PROCESSOR CHIP - A booting display control method and a processor chip are disclosed in the present invention. The processor chip includes at least a first processor, a second processor and a display control module. The second processor is coupled to the first processor. The display control module is coupled to the first processor and the second processor. After the first processor and the second processor are activated, the first processor will load an image file of an operating system and start the operating system, and the second processor will control the display control module to realize a booting display function. The booting display control method and the processor chip can be implemented in the fast display during the booting process. | 08-07-2014 |
20140218316 | CONTROL METHOD AND ELECTRONIC DEVICE - A control method and an electronic device utilizing the same are described. The control method, applied to an electronic device which contains at least one of a battery and a touch panel, including: detecting at least one of a temperature of the battery, a consumption rate of the battery, a display time of the touch panel and a touch frequency of the touch panel; and when at least one of the temperature of the battery, the consumption rate of the battery, the display time of the touch panel and the touch frequency of the touch panel meets at least one trigger condition, initiating a protection mechanism. | 08-07-2014 |
20140218080 | METHOD AND SYSTEM FOR FAST SYNCHRONIZED DYNAMIC SWITCHING OF A RECONFIGURABLE PHASE LOCKED LOOP (PLL) FOR NEAR FIELD COMMUNICATIONS (NFC) PEER TO PEER (P2P) ACTIVE COMMUNICATIONS - A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock. | 08-07-2014 |
20140204898 | Fast Device Discovery for Device to Device Communication - A fast device discovery protocol with a high success rate for device-to-device (D2D) communication in LTE-A networks is proposed. With the proposed protocol, device discovery is done by monitoring a randomly transmitted beacon from other devices within a pre-defined period. In one embodiment, an eNB receives scheduling requests from D2D UEs and in response allocates a distributed uplink resource for random access of beacon transmission by the D2D UEs. The distributed resource is dynamically allocated based on the number of requesting D2D UEs, a discovery period, and a target discovery probability to minimize the required resource. | 07-24-2014 |
20140199951 | TRANSCEIVER AND RELATED SWITCHING METHOD APPLIED THEREIN - A transceiver includes: a power amplifying circuit arranged to generate differential output signals during a transmitting mode of the transceiver; a balance-unbalance circuit arranged to convert the differential output signals into a single-ended output signal; a switchable matching circuit arranged to receive the single-ended output signal on a signal port of the transceiver during the transmitting mode, and to convert a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver; and a low-noise amplifying circuit arranged to convert the single-ended input signal into a low-noise input signal during the receiving mode. The power amplifying circuit, the Balun, the switchable matching circuit, and the low-noise amplifying circuit are configured as a single chip. | 07-17-2014 |
20140194057 | PROXIMITY SENSING METHOD USING LOOPBACK MECHANISM AND WIRELESS COMMUNICATIONS DEVICE THEREOF - A proximity sensing method employed by a wireless communications device includes the steps of: performing a first predetermined operation to detect a presence of at least a transponder in the proximity of the wireless communications device; when the presence of a transponder in the proximity of the wireless communications device is not detected by the first predetermined operation, performing a second predetermined operation to obtain a first characteristic value and after a period of time, performing the second predetermined operation to obtain a second characteristic value sequentially; checking if the first characteristic value and the second characteristic value satisfy a predetermined criteria; and when the predetermined criterion is satisfied, performing the first predetermined operation again to check the presence of the transponder in the proximity of the wireless communications device. | 07-10-2014 |
20140185663 | INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD FOR IMPROVED AMPLITUDE RESOLUTION OF AN RF-DAC - An integrated circuit includes: a digitally-controlled power generation stage for converting an input signal to a radio frequency (RF) carrier, the digitally-controlled power generation stage including a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal according to a fractional word and operably coupleable to the plurality of selectable switching devices of the digitally-controlled power generation stage; wherein the PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope of the RF carrier output from the digitally-controlled power generation stage. | 07-03-2014 |
20140184431 | METHODS FOR SIMPLIFIED MMI VQ BASED HARQ BUFFER REDUCTION FOR LTE - Methods of simplified MMI VQ based HARQ buffer reduction are disclosed. In one embodiment of the invention, the VQ obtains distribution information from source data based on a predefined codebook subset design. The subset design is predefined. Source data is trained within its corresponding subset to generate codebook. In one embodiment of the invention, the predefined subset algorithm is based on the LLR sign value. In another embodiment of the invention, source data is divided into subset based on predefined algorithm. The index to codebook is generated by search through the corresponding subset of the codebook instead of the whole codebook. In one embodiment of the invention, the training method is a modified Lloyd algorithm for MMI VQ. In another embodiment of the invention, the training method is a modified Lloyd algorithm for Euclidean distance VQ. | 07-03-2014 |
20140177755 | RF TRANSMITTER, INTEGRATED CIRCUIT DEVICE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A radio frequency (RF) transmitter includes a power amplifier comprising a plurality of power amplifier cells. At least one digital signal processing module of the RF transmitter is operably coupled to the power amplifier and comprises at least one digital pre-distortion component arranged to apply at least one digital pre-distortion codeword to the plurality of power amplifier cells, wherein the at least one digital pre-distortion codeword is applied to at least one of the plurality of power amplifier cells via a digital filter. A combiner is arranged to combine outputs of the plurality of power amplifier cells thereby generating an analogue RF signal for transmission over an RF interface based at least partly on the digitally filtered at least one digital pre-distortion codeword. | 06-26-2014 |
20140169478 | METHOD AND APPARATUS OF DEBLOCKING FILTER WITH SIMPLIFIED BOUNDARY STRENGTH DECISION - A method and apparatus for deblocking of reconstructed video in a video coding system are disclosed. Embodiments according to the present invention determine boundary strength between two blocks without checking whether the block boundary is a coding unit (CU) boundary. In one embodiment according to the present invention, the method comprises determining whether any of the two blocks is Intra coded. If any of the two blocks is Intra coded, the boundary strength is assigned a first value. Otherwise, additional decision processing is performed to determine the boundary strength. In another embodiment, said determining the boundary strength for the block boundary comprises determining whether the block boundary is a TU boundary and whether any of the two blocks contains coefficients. In yet another embodiment, said determining the boundary strength for the block boundary comprises determining whether the two blocks have different reference pictures or different motion vectors. | 06-19-2014 |
20140169427 | METHOD AND APPARATUS FOR CALIBRATING AN ENVELOPE TRACKING SYSTEM - A method of calibrating an envelope tracking system for a supply voltage for a power amplifier module within a radio frequency (RF) transmitter module. The method includes deriving a mapping function between an instantaneous envelope of a waveform signal to be amplified by the power amplifier module and the power amplifier module supply voltage to achieve a constant power amplifier module gain based on a gain compression factor, setting an envelope tracking path of the transmitter module into an envelope tracking mode in which mapping between the instantaneous envelope of the waveform signal and the power amplifier module supply voltage is performed using the derived mapping function, applying a training signal comprising an envelope that varies with time to the RF transmitter module, measuring a battery current, modifying the gain compression factor based on the measured battery current, and re-deriving the mapping function based on the modified gain compression factor. | 06-19-2014 |
20140167843 | METHOD AND APPARATUS FOR CALIBRATING AN ENVELOPE TRACKING SYSTEM - A method of calibrating an envelope tracking system for a supply voltage for a power amplifier module within a radio frequency (RF) transmitter module of a wireless communication unit. The method includes, within at least one signal processing module of the wireless communication unit, determining combinations of the power amplifier supply voltage and power amplifier input power that provide a power amplifier output power equal to a target output power, obtaining battery current indications for the determined combinations of the power amplifier supply voltage and power amplifier input power, selecting a combination of the power amplifier supply voltage and power amplifier input power that provide a power amplifier output power equal to a target output power based at least partly on the obtained battery current indications therefore, and calibrating the envelope tracking system using the selected combination of the power amplifier supply voltage and power amplifier input power. | 06-19-2014 |
20140159656 | DUAL-MODE WIRELESS POWER RECEIVER - A dual-mode receiver is provided that includes an electromagnetic resonator having one or more inductive elements that are arranged to form a receiver coil and a network of passive components arranged to form a matching network. | 06-12-2014 |
20140152371 | HIGH LINEARITY MIXER USING A 33% DUTY CYCLE CLOCK FOR UNWANTED HARMONIC SUPPRESSION - One mixer circuit includes mixer elements having 3N pairs of differential inputs. There are non-overlapping clock signals provided to the mixer elements which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. Output differential signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. Another mixer circuit includes a first mixer element and a signal combining device. The first mixer element has 3N pairs of differential inputs, wherein there are non-overlapping clock signals provided to the first mixer element which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. The signal combining device combines outputs from the first mixer element wherein an output signal of the signal combining device do not contain third order harmonic content of the non-overlapping clock signals. | 06-05-2014 |
20140119439 | METHOD AND APPARATUS OF INTRA MODE CODING - Method and apparatus for intra prediction mode coding and decoding are disclosed. In one embodiment, the encoding and decoding process assigns individual indices and codewords to DC mode and Planar mode respectively. The flag is set if the current intra prediction mode is equal to any of one or more neighboring intra prediction modes. Variable length codes are designed for a remaining mode set. If the flag is not set, the currently intra prediction mode is encoded using the variable length codes. In another embodiment, multiple most probable modes are used. If the current intra prediction mode is not equal to any of the multiple most probable modes, the current intra prediction mode is encoded using variable length codes designed for the corresponding remaining modes according the ranking order of the remaining modes. | 05-01-2014 |
20140111362 | INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD FOR A DIFFERENTIAL INTERFACE FOR AN ENVELOPE TRACKING SIGNAL - A signal processing circuit has a first circuit, a digital-to-analog converter (DAC) and a second circuit. The first circuit receives a digital input signal with a non-zero direct current (DC) component, and subtracts at least a portion of the DC) component of the received digital input signal from the received digital input signal. The DAC is operably coupled to the first circuit, and arranged to perform a digital-to-analog conversion upon an output of the first circuit. The second circuit is operably coupled to the DAC, and arranged to add a DC component to an analog output signal derived from an output of the DAC. The signal processing circuit may be part of an integrated circuit or a wireless communication unit. | 04-24-2014 |
20140095919 | CLOCK CONTROL METHOD FOR PERFORMANCE THERMAL AND POWER MANAGEMENT SYSTEM - A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period. | 04-03-2014 |
20140092781 | METHODS FOR CONNECTING DEVICES AND DEVICES USING THE SAME - A devices connecting method for connecting wirelessly connecting a first device to a second device. A first connection message transmitted from the second device is received, and the first connection message includes a first connection identifier. A second connection message transmitted from the second device is received, and the second connection message includes a second connection identifier. It is determined whether the second connection identifier is the same as the first connection identifier, and a corresponding determination result is provided. The second connection message is processed according to the determination result to establish the wireless connection between the first device and the second device. | 04-03-2014 |
20140085158 | COMMUNICATION DEVICE AND ANTENNAS WITH HIGH ISOLATION CHARACTERISTICS - A communication device includes a system circuit board, a ground plane, a first antenna, a second antenna, a first metal element, and a second metal element. The ground plane is disposed on the system circuit board. The first metal element is substantially located between the first antenna and the second antenna. The first metal element is coupled to the ground plane such that a system ground plane is formed. The second metal element is adjacent to the first metal element and substantially located between the first antenna and the second antenna. The second metal element is coupled to the system ground plane. The first antenna, the second antenna, and the first metal element are substantially located at an edge of the system circuit board. | 03-27-2014 |
20140084987 | SQUARING CIRCUIT, INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A squaring circuit has current mode triplet metal oxide semiconductor (MOS) devices, including a first MOS device, a second MOS device and a third MOS device each having a source operably coupled to a first current source; and a fourth MOS device, a fifth MOS device and a sixth MOS device each having a source operably coupled to a second current source. The drain of first and fourth MOS device is operably coupled to a first supply, the drain of second and fifth MOS device is operably coupled to a first differential output port and the drain of third and sixth MOS device is operably coupled to a second differential output port. The gate of first, second and sixth MOS device is connected to a first differential input port, and the gate of third, fourth and fifth MOS device is connected to a second differential input port. | 03-27-2014 |
20140073273 | METHOD AND APPARATUS FOR CALIBRATING AN ENVELOPE TRACKING SYSTEM - A method of calibrating an envelope tracking system for a supply voltage for a power amplifier module within a radio frequency (RF) transmitter module of a wireless communication unit. The method includes, within at least one signal processing module of the wireless communication unit: applying training signal having time-variant envelope to input of the RF transmitter module; receiving indication of instantaneous output signal value(s) for the power amplifier module in response to the training signal; and adjusting timing alignment between envelope tracking path of the envelope tracking system and transmit path of the RF transmitter module to align envelope tracking power amplifier module supply voltage to instantaneous envelope(s) of a waveform signal to be amplified by the power amplifier module, based at least partly on the received indication of the instantaneous output signal value(s) for the power amplifier module in response to the training signal. | 03-13-2014 |
20140073272 | METHOD AND APPARATUS FOR CALIBRATING AN ENVELOPE TRACKING SYSTEM - A method of calibrating an envelope tracking system for a supply voltage for a power amplifier module within a radio frequency (RF) transmitter module of a wireless communication unit. The method includes, within at least one signal processing module of the wireless communication unit, applying a training signal having an envelope that varies with time to an input of the RF transmitter module, receiving at least an indication of instantaneous output signal values for the power amplifier module in response to the training signal, calculating instantaneous gain values based at least partly on the received output power values, and adjusting a mapping function between an instantaneous envelope of a waveform signal to be amplified by the power amplifier module and the power amplifier module supply voltage to achieve a constant power amplifier module gain. | 03-13-2014 |
20140071892 | APPARATUS AND METHOD OF DATA COMMUNICATIONS IN MILLIMETER WAVE NETWORK - The method and apparatus of data communications for a transmitter in a millimeter wave network are provided. The method includes: generating a control physical layer (CPHY) preamble; generating a header, wherein the header includes a mode indicator; modulating and encoding a payload according to the mode indicator; generating a packet according to the control physical layer (CPHY) preamble, the header and the payload; and transmitting the packet. | 03-13-2014 |
20140068640 | CD PLAYER AND METHOD FOR EJECTION CONTROL THEREOF - A compact disc (CD) player and method for ejection control thereof is provided. The CD player has: a CD tray, an eject button, a front-end module, a back-end module, and a fast response eject module, wherein the front-end module and the back-end module are coupled to each other and integrated in an integrated circuit (IC). The fast response eject module has a second tray control module for detecting a status of the eject button, and a second ejection detection module for controlling the ejecting/inserting of the CD tray according to the detected status of the eject button after the CD player is powered up and before initialization of the first ejection detection module is completed. Accordingly, the CD player of the invention may quickly respond to the status of the eject button and control ejecting/inserting of the CD tray immediately after the CD player is powered up. | 03-06-2014 |
20140064390 | FREQUENCY DOMAIN EQUALIZER FOR A BEAMFORMED SYSTEM - A method, system, and computer program product for beamforming in a wireless communication system is disclosed. The method, system, and computer program product comprise a plurality of transmit antennas for a transmitter and at least one receive antenna for a receiver. The method, system, and computer program product comprise: initiating beamforming on a communication channel between the plurality of transmit antennas and the at least one receive antenna. The communication channel includes two data streams. A received signal to noise ratio (SNR) on one of the two data streams is weaker than a received SNR of the other data stream. The method, system, and computer program product include reallocating the transmit power between the stronger stream and the weaker stream to provide improved channel performance. | 03-06-2014 |
20140063352 | METHOD FOR CONTROLLING A MULTIMEDIA PLAYER, AND ASSOCIATED APPARATUS - A method for controlling a multimedia player, the method comprising: detecting whether at least one user enters at least one predetermined region near the multimedia player, and further detecting whether the user enters the predetermined region multiple times; and when it is detected that the user enters the predetermined region multiple times, triggering the multimedia player to play a second portion of a program, allowing the user to view the second portion of the program, wherein a first portion of the program is played when the user enters the predetermined region at a previous time, and a second start time index of the second portion is different from a first start time index of the first portion. | 03-06-2014 |
20140036560 | CIRCUIT AND METHOD FOR MEASURING AVAILABLE POWER IN A WIRELESS POWER SYSTEM - A resonant wireless power receiver that includes an electromagnetic resonator having one or more inductive elements that are arranged to form a receiver coil and a network of passive components arranged to form a matching network. A rectifier circuit converts ac power from the electromagnetic resonator to dc power. An available-power indicator measures the rectified power to assess the instantaneous power available to the receiver. | 02-06-2014 |
20140035384 | SYSTEM AND METHOD FOR CONTROLLING RESONANT WIRELESS POWER SOURCE - A resonant wireless power system includes a source circuit having a source coil, an ac driver with a first resistance, representing the equivalent output impedance of the ac driver, and a matching network. A current probe measures the magnitude signal of the instantaneous source coil current. A voltage probe measures the instantaneous ac driver voltage. A phase detector compares the phase of the instantaneous source coil current and the instantaneous ac driver voltage, and produces a first output signal proportional to the phase difference. A first amplifier compares the magnitude signal and a target signal, and produces an error signal proportional to the difference. A first compensation filter produces the control voltage that determines the ac driver supply voltage. A second amplifier amplifies the first output signal. A second compensation filter produces the control voltage that determines the impedance of a variable element in the source circuit. | 02-06-2014 |
20140035383 | DUAL-MODE WIRELESS POWER RECEIVER - A dual-mode receiver is provided that includes an electromagnetic resonator having one or more inductive elements that are arranged to form a receiver coil and a network of passive components arranged to form a matching network. The electromagnetic resonator includes a first selective frequency defined in a low frequency range and a second selective frequency defined in a high frequency range allowing for a rectification circuit to operate in both the high frequency range and low frequency range making maximum use of active circuits. | 02-06-2014 |
20140015701 | METHOD AND APPARATUS FOR PERFORMING MODULATION OF A RADIO FREQUENCY SIGNAL - A method and apparatus for performing modulation of a radio frequency, RF, signal within a digital-to-RF converter. The method includes determining a desired digital control word switching frequency value based at least partly on at least one parameter corresponding to a bandwidth of the RF signal to be modulated and at least one from a group including: at least one parameter corresponding to an RF channel frequency of the RF signal to be modulated; and at least one parameter corresponding to a power level of the RF signal to be modulated. The method further includes dynamically configuring at least one digital control module to output at least one digital control word signal in accordance with the desired digital control word switching frequency value, and performing modulation of the RF signal in accordance with the at least one digital control word signal output by the at least one digital control module. | 01-16-2014 |
20140007015 | ICON DISPLAYING METHOD AND ICON DISPLAY DEVICE | 01-02-2014 |
20130332823 | DEVICES AND METHODS FOR SETTING TEXT-APPEARANCE FORMATION OF MOBILE TERMINALS AND MOBILE TERMINAL - A device for setting text-appearance formation of a mobile terminal is provided. The device includes a command receiver, a text-appearance formation selector, and a text-appearance formation transformer. The command receiver is configured to receive a first operation command and a second operation command used for changing the text-appearance formation. The text-appearance formation selector is configured to provide a plurality of setting items of the text-appearance formation according to the first operation command and select at least one setting item of the text-appearance formation according to the second operation command. The text-appearance formation transformer is coupled to the text-appearance formation selector and configured to change the text-appearance formation according to the at least one selected setting item of the text-appearance formation. | 12-12-2013 |
20130322527 | Method and Apparatus for Quantization Level Clipping - A method and apparatus for clipping a transform coefficient are disclosed. Embodiments according to the present invention avoid overflow of the quantized transform coefficient by clipping the quantization level adaptively after quantization. In one embodiment, the method comprises generating the quantization level for the transform coefficient of a transform unit by quantizing the transform coefficient according to a quantization matrix and quantization parameter. The clipping condition is determined and the quantization level is clipped according to the clipping condition to generate a clipping-processed quantization level. The clipping condition includes a null clipping condition. The quantization level is clipped to fixed-range represented in n bits for the null clipping condition, where n correspond to 8, 16, or 32. The quantization level may also be clipped within a range from −m to m−1 for the null clipping condition, where m may correspond to 128, 32768, or 2147483648. | 12-05-2013 |
20130315325 | Method and Apparatus of Beam Training for MIMO Operation - The disclosed invention provides an efficient method for beam training to enable spatial multiplexing MIMO operation and spatial combining in a wireless network. The invention discloses a simple and efficient beam-training algorithm and protocol for MIMO operation that operates in high SNR condition for reliable MIMO operation. In one novel aspect, the best MIMO beam combinations are determined after TX sector sweeping and RX sector sweeping. In addition, the selection criteria includes not only signal quality, but also considers mutual interference and leakage among multiple MIMO spatial streams to improve overall MIMO performance. | 11-28-2013 |
20130314262 | SWITCH-DRIVING CIRCUIT AND DAC USING THE SAME - A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter. | 11-28-2013 |
20130314141 | SIGNAL PROCESSING CIRCUIT - The present disclosure relates to a signal processing circuit. The signal processing circuit includes a signal selection module, an offset module, and an amplifier module. The signal selection module is configured to select one from a plurality of input signals for outputting at least one first output signal. The voltage offset module is configured to output an offset voltage. The amplifier module, coupled to the signal selection module and the voltage offset module, is configured to ample the first output signal from the signal selection module, and offset the first output signal according to the offset voltage output from the offset voltage module, and perform an amplification gain control and data buffering processes on the offset signal. | 11-28-2013 |
20130311956 | INPUT ERROR-CORRECTION METHODS AND APPARATUSES, AND AUTOMATIC ERROR-CORRECTION METHODS, APPARATUSES AND MOBILE TERMINALS - An input error-correction method for a software keyboard is provided. The method includes: when entering an input key on the software keyboard, detecting if there is a sliding input; if there is a sliding input, obtaining a slide angle and a slide direction from the sliding input; and determining a target key to replace the input key according to the input key, the slide angle, and the slide direction for input error correction. | 11-21-2013 |
20130307930 | STEREOSCOPIC IMAGE PROCESSING APPARATUS AND METHOD THEREOF - A stereoscopic image processing method is provided. The method comprises the following steps of: receiving a stereoscopic image; shifting the received stereoscopic image according to offset information thereof; and scaling the shifted stereoscopic image to generate a resulting stereoscopic image according to the offset information. | 11-21-2013 |
20130294331 | Method for Distributed Relay Discovery and Data Forwarding - A method of discovering relay agent in a wireless communications system is provided. A wireless station first sends a relay solicitation frame to query availability of relay agent. The wireless station then receives one or more relay acknowledgement frames from one or more candidate relay agents in response to the relay solicitation frames. The wireless station determines a selected relay agent, and establishes a wireless link with the selected relay agent. The selected relay agent performs data forwarding between the station and an access point. The method allows a wireless station to initiate the relay agent discovery process by soliciting a specific relay agent or broadcasting a request to all potential relay agents. The selected relay agent can be determined with minimum power and based on link quality associated with the relay agent and specific requirement of the wireless station. | 11-07-2013 |
20130293403 | ADC, IC INCLUDING THE SAME, AND ADC METHOD THEREOF - An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal. | 11-07-2013 |
20130279630 | CIRCUIT AND TRANSMITTER FOR REDUCING TRANSMITTER GAIN ASYMMETRY VARIATION - The present invention provides for a circuit with slicing wherein a gain asymmetry variation is decreased across the plurality of mixer slices. In one or more embodiments, a calibration unit can be provided to determine the characteristics of gain asymmetry variation; and a digital compensation unit can be provided to adjust the gain of the circuit over frequency. | 10-24-2013 |
20130266223 | REGION GROWING METHOD FOR DEPTH MAP/COLOR IMAGE - An exemplary region growing method include at least the following steps: selecting a seed point of a current frame as an initial growing point of a region in the current frame; determining a background confidence value at a neighboring pixel around the seed point; and utilizing a processing unit for checking if the neighboring pixel is allowed to be included in the region according to at least the background confidence value. | 10-10-2013 |
20130266064 | Method and Apparatus for Intra Mode Coding in HEVC - A method and apparatus for Intra prediction mode encoding or decoding based on multi-level most probable modes (MPMs) are disclosed. In one embodiment according to the present invention, the method and apparatus for encoding or decoding Intra prediction mode for 4×4 prediction unit (PU) use 19 Intra mode candidates to have full directional coverage or 35 Intra mode candidates as used by 8×8, 16×16 and 32×32 PUs. In another embodiment of the present invention, three MPMs are used to code the Intra modes. Various methods to derive the three MPMs based on the Intra modes of neighboring blocks are disclosed. In yet another embodiment of the present invention, the coding method for the remaining modes comprises fixed length coding. In addition, variable length coding for the remaining modes are also disclosed. | 10-10-2013 |
20130265114 | METHOD AND APPARATUS FOR MEASURING/COMPENSATING MISMATCHES IN DIGITALLY-CONTROLLED OSCILLATOR - A method for measuring mismatches in a digitally-controlled oscillator (DCO) includes: in a first settling phase, controlling a first capacitor array of the DCO to have a first capacitive value consistently, and controlling a second capacitor array of the DCO in a closed loop to make a frequency of the DCO locked to a target value; in a second settling phase, controlling the first capacitor array to consistently have a second capacitive value different from the first capacitive value, and controlling the second capacitor array in the closed loop to make the frequency of the DCO locked to the target value; and deriving an estimation from a difference value between a first characteristic value and a second characteristic value, wherein the first and second characteristic values are derived from the digital control word; and estimating the mismatches according to at least the estimation value. | 10-10-2013 |
20130265104 | METHOD AND APPARATUS FOR CURRENT CONTROL IN A CIRCUIT - A circuit includes an output node; a first current source coupled via at least one first switch to at least the output node and a calibration node, wherein the first switch alternately operably couples the first current source to the output node or the calibration node; a second current source of opposing polarity to the first current source and operably coupled via at least one second switch to at least the output node and the calibration node, wherein the second switch alternately operably couples the second current source to the output node or the calibration node; and a current control circuit having an adjustment circuit operably coupled to the calibration node, wherein the current control circuit couples both the first and second current sources to the calibration node when a current from the first/second current source is not to be used as an output from the output node. | 10-10-2013 |
20130257508 | HIGH LINEARITY MIXER USING A 33% DUTY CYCLE CLOCK FOR UNWANTED HARMONIC SUPPRESSION - A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33 ⅓ percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the 1-0 image and even order harmonics. | 10-03-2013 |
20130257484 | VOLTAGE-TO-CURRENT CONVERTER - A voltage-to-current converter is described. In one embodiment, the voltage-to-current converter includes an operational amplifier, where a first input of the operational amplifier is coupled to a first node and a second input of the operational amplifier is coupled to a reference voltage. The input voltage is connected to the first node through a resistor which generates the input current. The voltage-to-current converter also includes a first transistor coupled to a first node and to an output of the operational amplifier, where the input current flows through the first transistor. The voltage-to-current converter also includes a second transistor coupled to the first transistor, to the output of the operational amplifier, and to an output node, where an output current flows through the second transistor. The first and second transistors constitute a current mirror to provide additional current gain for the output current. | 10-03-2013 |
20130251074 | DEMODULATING DATA STREAMS - Embodiments for demodulating data streams are disclosed. In one embodiment, a method includes receiving, at a multiple-input device, a plurality of data streams. The method also includes determining a degree of correlation among the plurality of data streams. The method also includes selecting a demodulator based on the degree of correlation. | 09-26-2013 |
20130243064 | EXPERT ANTENNA CONTROL SYSTEM - A method and system for actively selecting antenna sets for a client are disclosed. In a first aspect, the method comprises sending a first channel packet from a transmitter to a receiver and sending a second channel packet corresponding to the received first channel packet from the receiver to the transmitter. The method includes collecting statistics of an antenna set related to the sending of the first and the second channel packets. The method includes comparing the collected statistics to previously collected statistics of another antenna set to select one of the antenna set and the another antenna set. In a second aspect, the system comprises a processor and a memory device coupled to the processor, wherein the memory device stores an application which, when executed by the processor, causes the processor to carry out the steps of the method. | 09-19-2013 |
20130234800 | CALIBRATION DEVICE FOR OSCILLATOR AND METHOD THEREOF - A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator. | 09-12-2013 |
20130229216 | SIGNAL DUTY CYCLE DETECTOR AND CALIBRATION SYSTEM - A duty cycle detector and calibration system is disclosed. In some embodiments, a duty cycle calibration system includes a first tuning circuit operative to receive an input signal, tune a duty cycle of the input signal to within a first error range, and provide a first output signal. A second tuning circuit tunes a duty cycle of the first output signal to within a second error range and provides a second output signal, where the second error range has more precision than the first error range. A duty cycle detector provides a duty cycle detection signal indicative of a duty cycle of the second output signal, and logic controls the first and second tuning circuits based upon the duty cycle detection signal. | 09-05-2013 |
20130225239 | COMMUNICATION APPARATUS AND METHOD FOR DISPLAYING MMI - A communication apparatus and a method for providing a predetermined subscriber identification module (SIM) card are provided. The communication apparatus provides different man-machine interfaces (MMIs) according to a number of the inserted SIM cards. The communication apparatus includes a detector arranged to detect an amount of the inserted SIM cards on the communication apparatus, and a processor arranged to provide different MMIs according to the amount of inserted SIM cards. | 08-29-2013 |
20130219201 | ELECTRONIC DEVICE SYSTEMS AND METHODS FOR MAINTAINING LOW POWER CONSUMPTION WHILE PROVIDING POSITIONING FUNCTION IN ELECTRONIC DEVICE SYSTEM - An electronic device system includes a first device and a second device. The first device controls system operations and operates in at least a normal mode and a sleep mode having lower power consumption. After issuing a condition setting signal carrying at least a wake up condition, the first device switches from the normal mode to the sleep mode. After receiving an interrupt indication signal, the first device switches from the sleep mode to the normal mode. The second device is coupled to the first device and continuously receives and processes multiple satellite signals to obtain position information. The second device receives the condition setting signal from the first device and determines whether the wake up condition has been met according to the position information. When the wake up condition has been met, the second device issues the interrupt indication signal. | 08-22-2013 |
20130219087 | HIGH-DEFINITION MULTIMEDIA INTERFACE (HDMI) RECEIVER APPARATUSES, HDMI SYSTEMS USING THE SAME, AND CONTROL METHODS THEREFOR - A high-definition multimedia interface (HDMI) receiver apparatus is provided. The HDMI receiver apparatus includes a pin, a control module, and an extended display identification data (EDID) module. The pin is used to receive an HDMI cable connection voltage in a first operation state and output a hot plug detection signal in a second operation state. The control module is connected with the pin. When the pin receives the HDMI cable connection voltage in the first operation state, the control module switches the pin to the second operation state from the first operation state and outputs the hot plug detection signal to an HDMI transmitter apparatus through the pin, such that the HDMI transmitter apparatus reads EDID information according to the hot plug detection signal. The EDID module is used to store the EDID information. | 08-22-2013 |
20130217343 | WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD THEREFOR - A wireless communication unit is described that includes a transceiver; at least one antenna port operably coupled to the transceiver via at least one antenna switch; a radio frequency part of the transceiver that includes at least one tuneable radio frequency (RF) component; and a test signal generator for generating an RF test signal for receiver calibration. The radio frequency part includes a coupler located between the at least one tuneable RF component and the at least one antenna switch for coupling the RF test signal to or from the radio frequency part for calibration. | 08-22-2013 |
20130214827 | METHOD AND SYSTEM FOR SYNCHRONIZING THE PHASE OF A PLURALITY OF DIVIDER CIRCUITS IN A LOCAL-OSCILLATOR SIGNAL PATH - A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits. | 08-22-2013 |
20130205089 | Cache Device and Methods Thereof - A cache device, coupled to a processing device, a plurality of system components and an external memory control module, capable of exchanging all types of traffic streams from the processing device and the plurality of system components to the external memory control module. The cache device includes a plurality of cache units, comprising a plurality of cache lines and corresponding to a plurality of cache sets; a data accessing unit, coupled to the processing device, the plurality of system components, the plurality of cache units and the external memory control module, capable of exchanging data of the processing device, the plurality of cache units and an external memory device coupled to the external memory control module according to at least one request signal from the processing device and the plurality of system components. | 08-08-2013 |
20130169543 | Rendering Apparatuses, Display System and Methods for Rendering Multimedia Data Objects with a Function to Avoid Eye Fatigue - A rendering apparatus is provided. A storage device stores at least one multimedia data object to be displayed. A processor obtains the multimedia data object from the storage device, determines an object type of the multimedia data object, renders the multimedia data object based on a display mode, determines whether eye fatigue of a viewer viewing the multimedia data object has occurred or is about to occur according to the object type, and adjusts the display mode for rendering the multimedia data object according to the object type when eye fatigue of a viewer has occurred or is about to occur. | 07-04-2013 |
20130156085 | PHASED ARRAY DEVICE AND CALIBRATION METHOD THEREFOR - The calibration method, performed on a phased array device including channel elements coupled in parallel by a transmission line, has the steps of: obtaining channel responses corresponding to the channel elements through the transmission line, and each of the channel responses is obtained when one of the channel elements is turned on, and the rest of the channel elements are turned off; calculating a characteristic value corresponding to the transmission line based on the obtained channel responses of the channel elements; and adjusting a channel parameter of one of the channel elements based on the characteristic value of the transmission line. | 06-20-2013 |
20130154723 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 06-20-2013 |
20130133193 | SURFACE MOUNT TECHNOLOGY PROCESS FOR ADVANCED QUAD FLAT NO-LEAD PACKAGE PROCESS AND STENCIL USED THEREWITH - The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad. | 05-30-2013 |
20130117295 | METHOD FOR SEARCHING FOR FLASH VIDEO TAG IN BITSTREAM AND SEARCHING APPARATUS THEREOF - A method for searching for a flash video (FLV) tag in a bitstream includes the following steps: setting a first start position and a first search length related to a first search process, wherein the first search length indicates a bitstream length of the first search process performed upon the bitstream; starting the first search process upon the bitstream from the first start position to search for the FLV tag; when the FLV tag is not found in the first search length, setting a second start position related to a second search process immediately following the first search process, wherein the first start position and the second start position are separated by a time period equaling a sum of the first search length and a first skip length corresponding to the first search process; and starting the second search process upon the bitstream from the second start position to search for the FLV tag. | 05-09-2013 |
20130113989 | VIDEO PROCESSING APPARATUS AND METHOD FOR SIMULTANEOUSLY DISPLAYING A PLURALITY OF VIDEO SIGNALS ON DISPLAY DEVICE - A video processing apparatus includes decoding circuit, setting circuit, processing circuit, first buffer, second buffer, and display unit. The decoding circuit generates a plurality of decoded video signals. The setting circuit selects a main decoded video signal and at least one sub-decoded video signal from the decoded video signals. The processing circuit processes main decoded video signal and sub-decoded video signal(s) to generate a processed video signal. Each of these two buffers serves as on-screen buffer for storing the processed video signal being displayed or to be displayed and serves as on-process buffer for storing the processed video signal being mixed or to be mixed, cyclically. The first and second buffers do not serve as on-screen buffer simultaneously, and the first and second buffers do not serve as on-process buffer simultaneously. The display unit cyclically displays the processed video signal read from first buffer and second buffer. | 05-09-2013 |
20130107916 | Methods for Inter-User Interference Indication Feedback and Usage in MU-MIMO Wireless Systems | 05-02-2013 |
20130107483 | PRINTED CIRCUIT BOARD AND ELECTRONIC APPARATUS THEREOF | 05-02-2013 |
20130100943 | DETECTING THE PRESENCE OF A PREAMBLE IN A RECEIVED WIRELESS SIGNAL - Embodiments for processing signals are disclosed. In one embodiment, a method includes providing a plurality of cyclically shifted versions of a known sequence. The method also includes receiving a plurality of delayed versions of a received sequence of a packet. The method also includes correlating the plurality of the delayed versions of the received sequence with the plurality of cyclically shifted versions of the known sequence. The method also includes detecting a preamble of the packet based on the outcome of a described decision statistic computed using the received and known sequences. | 04-25-2013 |
20130095761 | SYSTEMS AND METHODS FOR SEAMLESS SWITCHING BETWEEN A PLURALITY OF WIRELESS CONNECTIONS FOR WIRELESS TRANSMISSIONS - A wireless communications system is provided with a first wireless communications module, a second wireless communications module, and a connection management module. The first wireless communications module operates in compliance with a first wireless communication protocol, and transmits data by wireless transceiving via a first wireless connection. The second wireless communications module operates in compliance with a second wireless communication protocol. The connection management module requests the second wireless communications module to establish a second wireless connection in response to a signal indicator of the first wireless connection having a value within a predetermined range, and transfers the data to the second wireless communications module to be transmitted via the second wireless connection. | 04-18-2013 |
20130093533 | M-WAY COUPLER - An M-way coupler having a first port, M second ports, M transmission line sections, M isolation resistors and a phase shifting network is disclosed, where M is an integer number greater than 1. The M transmission line sections couple the first port to the M second ports, respectively. Each of the M isolation resistors has a first terminal and a second terminal. The first terminals of the M isolation resistors are coupled to the M second ports, respectively. The phase shifting network has M I/O terminals coupled to the second terminals of the M isolation resistors, respectively. The phase shifting network is arranged to provide a phase shift within a predetermined tolerance margin between arbitrary two I/O terminals of the M I/O terminals of the phase shifting network. | 04-18-2013 |
20130084006 | Method and Apparatus for Foreground Object Detection - The present invention utilizes depth images captured by a depth camera to detect foreground/background. In one embodiment, the method comprises establishing a single background distribution model, updating the background distribution model if a new depth value for the pixel can be represented by the background distribution model, skipping update of the background distribution model if the pixel is before the background, and replacing the background distribution model if the pixel is behind the background. In case that the background distribution model does not exist initially, a new background distribution model is created. In one embodiment of the present invention, the non-meaningful pixels are handled. In another embodiment, fluctuation of the depth value due to noise is handled by using a candidate background distribution model. In yet another embodiment, the noise for pixels around object edges is handled by using a mixture of two background distribution models. | 04-04-2013 |
20130076325 | VOLTAGE REGULATOR - A voltage regulator includes a pass transistor, an operational amplifier and a voltage divider circuit. The pass transistor receives a supply voltage to generate a regulated output voltage according to a control signal. The operational amplifier generates the control signal according to a feedback voltage. The voltage divider circuit generates the feedback voltage at a feedback node according to the regulated output voltage, and includes a string of resistors and a stabilization element. The string of resistors is coupled to the pass transistor and includes multiple resistors. The stabilization element is coupled to the resistors and receives the regulated output voltage. | 03-28-2013 |
20130064472 | Method and Apparatus of High-Resolution Image Reconstruction Based on Multi-Frame Low-Resolution Images - A method and apparatus for reconstructing a high-resolution image based on multiple low-resolution images are disclosed. The method and apparatus incorporating an embodiment according to the present invention reconstructs the high-resolution image based on a kernel regression method using a modified kernel function. The kernel function takes into consideration of registration reliability of regression residue and rotational motion within the multiple low-resolution images. The registration reliability adjusts weighting on the regression residues according to local gradient estimated between neighboring values. Furthermore, multi-scale regression residue is used to alleviate impact of noise. | 03-14-2013 |
20130059586 | NETWORK SEARCHING METHODS AND APPARATUSES FOR MULTI-MODE USER EQUIPMENT - A network searching method for a multi-mode user equipment having a first radio access technology module and a second radio access technology module includes camping on a current cell by the user equipment via the first radio access technology module; obtaining information broadcast by a system of the second radio access technology module via the first radio access technology module when network environment corresponding to the first radio access technology module changes; and instructing the second radio access technology module to perform a network searching. | 03-07-2013 |
20130055073 | APPARATUS CAPABLE OF PROVIDING PAGE RECOMMENDATION AND PAGE RECOMMENDATION METHOD - The invention provides an apparatus capable of providing page recommendation. In one embodiment, the apparatus is coupled to a screen capable of showing a plurality of pages, and comprises a determination module, a classification module, and a displaying module. The determination module determines whether a current page displayed on the screen has enough space for containing a target item to be added to the current page. The classification module classifies the pages into available pages having enough space for the target item and unavailable pages having no enough space for the target item. The displaying module displays a page selector indicating the available pages and the unavailable pages on the screen, and adds the target item to a target page selected from the available pages. | 02-28-2013 |
20130043958 | DIGITALLY CONTROLLED OSCILLATOR - A digitally controlled oscillator is provided. The digitally controlled oscillator includes a pair of transistors cross-coupled to each other, a switched capacitor array coupled to the pair of transistors and a plurality of frequency tracking units coupled to the pair of transistors. The pair of transistors provides an output signal. The switched capacitor array tunes a frequency of the output signal. The frequency tracking units tune the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance. A tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances. | 02-21-2013 |
20130038483 | ANALOG-TO-DIGITAL CONVERTERS AND PIPELINE ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter is provided. The analog-to-digital converter includes a sampling-voltage providing circuit, a first comparison circuit, a second comparison circuit, and an encoder circuit. The sampling-voltage providing circuit provides a group of first comparison voltages and a group of second comparison voltages. The first comparison circuit performs a first comparison operation to an analog-signal input quantity according to the group of first comparison voltages to generate a first comparison digital quantity. The second comparison circuit selects second comparison voltages among the group of second comparison voltages according to the first comparison digital quantity and performs a second comparison operation to the analog-signal input quantity according to the selected second comparison voltages to generate a second comparison digital quantity. The encoder circuit encodes the first comparison digital quantity and the second comparison digital quantity and generates a digital quantity corresponding to the analog-signal input quantity. | 02-14-2013 |
20130038297 | BATTERY CHARGING CONTROL DEVICE AND METHOD OF IMPLEMENTING THE SAME - The invention discloses a charging control method for adjusting a charging current of a charging device, including monitoring a working voltage of the charging device, wherein the working voltage includes a voltage difference between a charging voltage and a battery voltage; adjusting the charging current of the charging device dynamically according to the working voltage of the charging device to maintain a working power of the charging device within a predetermined power range. | 02-14-2013 |
20130034190 | WIRELESS RECEIVER - Wireless receiver for receiving a plurality of co-existing wireless signals respectively from different positioning systems, includes an analog frontend and an analog-to-digital converting unit. The analog frontend is arranged to convert bands of the co-existing wireless signals into a plurality of corresponding intermediate bands by a local frequency and to provide an intermediate signal including the intermediate bands. The analog-to-digital converting unit is coupled to the analog frontend, and is arranged to convert the intermediate signal to a digital signal, wherein an operation band of the analog-to-digital converting unit covers the plurality of intermediate bands. | 02-07-2013 |
20130033391 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A multiplying digital-to-analog converter (MDAC) is provided. The MDAC includes a sub DAC decoding circuit, a capacitor-switch circuit, and an operation amplifier circuit. The capacitor-switch circuit includes at least two sampling capacitor sets which are coupled in parallel. The number of sampling capacitors in one of the sampling capacitor sets is larger than or equal to two. Each sampling capacitor set is coupled to an analog-signal input quantity through a sampling switch and to a corresponding output terminal of the sub DAC decoding circuit through a decoding switch. The sub DAC decoding circuit decodes a digital quantity and outputs a corresponding analog signal at each output terminal, such that the corresponding analog signals are applied to the respective sampling capacitor sets through the decoding switches and summed by the respective sampling capacitor sets to obtain an analog-signal quantity corresponding to the digital quantity. | 02-07-2013 |
20130033245 | BANDGAP CIRCUIT FOR PROVIDING STABLE REFERENCE VOLTAGE - The invention provides a bandgap circuit for providing stable reference voltages. The bandgap circuit comprises a core circuit and an output branch. The core circuit comprises: a first transistor, coupled between a supplied working voltage and a first node, and having a gate coupled to the first node; a second transistor, coupled between the supplied working voltage and a second node, and having a gate coupled to the first node; a third transistor, coupled between the first node and a ground voltage, and having a gate coupled to a third node; a fourth transistor, coupled between the third node and the ground voltage, and having a gate coupled to the second node; and a first resistor, coupled between the second and third nodes. The output branch is coupled to the core circuit to receive an output of the core circuit, and arranged to output a reference voltage at an output node. | 02-07-2013 |
20130029627 | AMPLIFIER AND ASSOCIATED RECEIVER - An amplifier receives an input signal with an input node, provides an output signal in response, and includes a main branch and an auxiliary branch. The auxiliary branch is coupled between the input node and a splitting node for input matching of the input node. The main branch, also coupled to the splitting node, has an output node of current mode, and is arranged to output the output signal at the output node. An associated receiver is also disclosed. | 01-31-2013 |
20130028062 | OPTICAL DISC DRIVE AND METHOD OF ACCESSING OPTICAL DISC - An optical disc drive and a method of reading an optical disc are disclosed. The drive includes an I/O port, an optical pickup module and a format conversion unit. The I/O port couples a host to receive a read command of a host terminal file system format. The optical pickup module accesses the optical disc which contains data of a first file system format. The format conversion unit coupled between the I/O port and the optical pickup module includes a mapping information generation module, a memory module and a read-command processing module. The mapping information generation module controls the optical pickup module to access data and thereby to generate mapping information. The memory module stores the mapping information. The read-command processing module controls the optical pickup module to access the optical disc according to the read command by referring to the mapping information. | 01-31-2013 |
20130027232 | ANALOG-TO-DIGITAL CONVERTERS AND ANALOG-TO-DIGITAL CONVERSION METHODS - An analog-to-digital converter is provided and comprises a most significant bit (MSB) conversion module, a successive approximation register analog-to-digital converter (SAR ADC) module, and an operation module. The MSB conversion module receives an analog signal to be converted, and converts the analog signal to an MSB with M bits, and obtains a redundancy signal. The SAR ADC module is coupled to the MSB conversion module. The SAR ADC receives the redundancy signal and processes the redundancy signal to be a least significant bit (LSB) with N bits. The operation module is coupled to the MSB conversion module and the SAR ADC module. The operation module receives the MSB with the M bits and the LSB with the N bits and generates a first digital signal with (M+N) bits. Each of M and N is positive, and (M+N) is a positive integer. | 01-31-2013 |
20130022129 | Method and Apparatus for Compressing Coding Unit in High Efficiency Video Coding - In HEVC (High Efficiency Video Coding), a 2N×2N coding unit can be partitioned into various partition types hierarchically. The coding system uses a criterion to determine the best partition, where RD-rate is often used as the criterion. N×N partition at level k becomes redundant if 2N×2N at level k+1 will be evaluated. In order to eliminate the above redundancy, the allowable partition sizes are constrained according to a method previously disclosed. In the current invention, the complexity is further reduced. According to one embodiment, N×N partition is not allowed for any INTER mode regardless of the coding unit size. Furthermore, flexibility is provided so that either the method and apparatus with further complexity reduction can be selected or an alternative method and apparatus can be selected. Syntaxes to support embodiments according to the present invention are also disclosed. | 01-24-2013 |
20130016013 | MOBILE COMMUNICATION DEVICE AND ANTENNA DEVICEAANM Wong; Kin-LuAACI Kaohsiung CityAACO TWAAGP Wong; Kin-Lu Kaohsiung City TWAANM Kang; Ting-WeiAACI Kaohsiung CityAACO TWAAGP Kang; Ting-Wei Kaohsiung City TWAANM Hsieh; Shih-WeiAACI Taipei CityAACO TWAAGP Hsieh; Shih-Wei Taipei City TWAANM Chen; Wei YuAACI New Taipei CityAACO TWAAGP Chen; Wei Yu New Taipei City TW - A mobile communication device for operating in LTE and WWAN bands is provided in the invention. The mobile communication device includes a system circuit board and an antenna. The system circuit board includes a system ground plane. The antenna includes: an antenna substrate, substantially parallel to the system ground plane; a first radiation element, disposed on the antenna substrate; a second radiation element, disposed on the antenna substrate; an antenna ground plane, disposed on the antenna substrate, and coupled to the system ground plane; and a transmission line, disposed on the antenna substrate, coupled to the first and second radiation elements, and having a feed point. The mobile communication device is further configured to accommodate a data transmission component. | 01-17-2013 |
20130003843 | Motion Prediction Method - The invention provides a motion prediction method First, a coding unit (CU) of a current picture is processed, wherein the CU comprises at least a first prediction unit (PU) and a second PU. A second candidate set comprising a plurality of motion parameter candidates for the second PU is then determined, wherein at least a motion parameter candidate in the second candidate set is derive from a motion parameter predictor for a previously coded PU of the current picture, and the second candidate set is different from a first candidate set comprising a plurality of motion parameter candidates for the first PU. A motion parameter candidate is then selected from the second candidate set as a motion parameter predictor for the second PU. Finally, predicted samples are then generated from the motion parameter predictor of the second PU partition. | 01-03-2013 |
20120324516 | METHOD AND SYSTEM TO PROVIDE A CONSUMER ELECTRONICS SYSTEM WITH IMPROVED FUNCTIONALITY - A method and system to provide networking related features and other features to a consumer electronics system. The system implementation described herein shows one option to implement the method for a DTV system. The system includes a router and a DTV System-on-a-Chip. The router provides features to the DTV when the DTV system can be in any mode including on and stand-by, features like Access Point, WiFi Direct, Network Storage, Ethernet Switch and Network Pre-fetch. | 12-20-2012 |
20120319883 | TIME-TO-DIGITAL CONVERTER - Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time. | 12-20-2012 |
20120314594 | MEASURING AND IMPROVING MULTIUSER DOWNLINK RECEPTION QUALITY IN WIRELESS LOCAL AREA NETWORKS - Embodiments for improving multi-user downlink reception quality in WLANS are disclosed. In one embodiment, a method includes receiving, at a station, at least one multi-user sounding packet from an access point. The method also includes determining a sum of desired signal strengths from the at least one received sounding packet. The method also includes determining a sum of interference signal strengths from the at least one received sounding packet. The method also includes generating link quality metrics based on a ratio of the sum of desired signal strengths to the sum of interference signal strengths. | 12-13-2012 |
20120263055 | Fast Link Adaptation and Transmit Power Control in Wireless Networks - An open-loop fast link adaptation scheme is proposed in an OFDM system. An access point first transmits a downlink packet comprising an open-loop link metric to a wireless station. The open-loop link metric contains a transmit power of the downlink packet plus a receiver sensitivity of the access point. The wireless station measures a received signal strength indication (RSSI) value of the downlink packet. The wireless station then applies open-loop link adaptation and determines a modulation and coding scheme (MCS) based on the open-loop link metric and the RSSI value. The open-loop link adaptation scheme is especially suitable for smart meter/sensor networks as it reduces overhead and increases link capacity. | 10-18-2012 |
20120205978 | REGULATOR PROVIDING VARIOUS OUTPUT VOLTAGES - A regulator for providing a plurality of output voltages is provided. The regulator includes a basic unit and a plurality of replica units. The basic unit amplifies an input voltage to obtain a core voltage according to a first control signal. Each of the replica units outputs one of the output voltages according to the input voltage and one of a plurality of second control signals, wherein at least two of the output voltages have different voltage levels. The first control signal is set according to the second control signals, to make the voltage level of the core voltage substantially equal to or less than a maximum voltage level of the output voltages and substantially equal to or greater than a minimum voltage level of the output voltages. | 08-16-2012 |
20120177112 | Method and Apparatus of Improved Intra Prediction Mode Coding - A method and apparatus for improved intra chroma prediction mode coding are disclosed. Intra prediction exploits the spatial correlation within a picture or within a picture region. In practice, a picture is divided into blocks and the intra mode prediction is performed on a block basis. In newer coding systems, multiple intra coding modes such as Vertical mode, Horizontal mode, DC mode and Diagonal mode, have been used to improve the coding efficiency of intra coding. Furthermore, a Luma_mode has also been used in intra prediction of chroma component to further improve the performance in the High Efficiency Video Coding (HEVC) standard being developed. However, the mode selection information for intra prediction has to be conveyed to the decoder for proper operation. Spatial features in a picture often exist in both luma and chroma components. The intra luma prediction mode and intra chroma prediction mode will have high probability to be the same. Accordingly, an embodiment according to the present invention adaptively assigns variable length codes to a set of mode symbols associated with intra chroma prediction by assigning a shortest code to the Luma_mode. Luma_mode not only can be the best luma mode of the corresponding luma block but also can be selected from several corresponding luma modes. The maximum length of chroma prediction codes is decreased by one bit when Luma_mode is equal to one of frequent modes. The coding efficiency of arithmetic coding of chroma prediction codes is further improved by selecting the context upon neighboring blocks. | 07-12-2012 |
20120146595 | REGULATOR WITH HIGH PSRR - A regulator for providing a low dropout voltage at an output node of the regulator is provided. An amplifier has a non-inverting input terminal for receiving an input voltage, an inverting input terminal and an output terminal. A first resistor is coupled between a ground and the inverting input terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. A first transistor is coupled between a voltage source and the second resistor. A current source coupled between the voltage source and a gate of the first transistor provides a bias current. A second transistor coupled between the first transistor and a current mirror has a gate coupled to the output terminal of the amplifier. The first and second transistors are different type MOS transistors. The replica unit generates the low dropout voltage according to a voltage of the output terminal of the amplifier. | 06-14-2012 |
20120128067 | Apparatus and Method of Constrained Partition Size for High Efficiency Video Coding - An apparatus and method for video coding and decoding with constrained PU partition are disclosed. In the High Efficient Video Coding (HEVC) system, rate-distortion function or other performance criterion usually is evaluated for various CU partition and PU partition during the encoding process in order to select a configuration with best possible performance. The PU design in the current HEVC development results in some redundancy that causes rate-distortion function or other performance criterion repeatedly evaluated for same PU configuration. Accordingly, constrained PU partition is developed to eliminate or reduce the redundancy in processing. Furthermore, necessary syntax to convey the information related to constrained PU partition between an encoder and a decoder is developed. Systems embodying the present invention has been shown to result in sizeable reduction in encoding and decoding time while the performance in terms of RD-rate remains approximately the same or slightly higher than a conventional HEVC system. | 05-24-2012 |
20110239098 | Detecting Data Error - A method includes segmenting a first portion of a data block into a plurality of segments that includes a first segment. The data block includes a second portion, different from the first portion, which stores cyclic redundancy check data calculated from data stored in the first portion of the data block. The method also includes calculating cyclic redundancy check data from the first segment, and, translating the calculated cyclic redundancy check data to a location associated with the data block. The method also includes combining the cyclic redundancy check data associated with the first segment and cyclic redundancy check data associated with at least one other segment included in the plurality of segments. The method also includes using the combined cyclic redundancy check data for error detection. | 09-29-2011 |
20110105175 | Method and System for Managing Transmitting Power of Communications Devices Equipped with a Plurality of Antennas - A communications system and method for managing transmitting power of communications devices equipped with multiple antennas. A first communications device enables a first antenna configuration in accordance with a first pre-determined rule. A second communications device activates a second antenna configuration in accordance with a second predetermined rule. First and second messages are exchanged between the first and second communications devices. The first message includes the power management profile of the first communications device and the second message includes information pertinent to a power management profile of the second communications device, and signal integrity information determined by the second communications device from the received first message. The first communications device enables a third antenna configuration in accordance with the first pre-determined rule and the second communications device activates a fourth antenna in accordance with the second pre-determined rule configuration after the first and second messages have been exchanged. | 05-05-2011 |
20110007912 | DOUBLE INTEGRAL METHOD OF POWERING UP OR DOWN A SPEAKER - An audio subsystem having a waveform generation circuit that generates a power-up signal for controlling an electric signal used to drive a speaker during a power-up period in which the power-up signal has a positive second derivative during a first sub-period of the power-up period and has a negative second derivative during a second sub-period of the power-up period. The first sub-period spans at least one-fourth of the power-up period, and the second sub-period spans at least one-fourth of the power-up period. | 01-13-2011 |
20110002386 | VIDEO ENCODER AND METHOD FOR PERFORMING INTRA-PREDICTION AND VIDEO DATA COMPRESSION - The invention provides a method for performing intra-prediction. A target pixel is selected from a plurality of pixels of a current block. A first intra-prediction mode of a left block, a second intra-prediction mode of an up block, and a third intra-prediction mode of the current block are then determined. A first prediction value of the target pixel is calculated according to the first intra-prediction mode. A second prediction value of the target pixel is calculated according to the second intra-prediction mode. A third prediction value of the target pixel is calculated according to the third intra-prediction mode. The first prediction value, the second prediction value, and the third prediction value are then averaged to obtain a weighted-average prediction value as an intra-prediction value of the target pixel. | 01-06-2011 |
20100328124 | CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER - A digital to analog converter (DAC) module receives an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency. The DAC module includes an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal. | 12-30-2010 |
20100310065 | SYSTEM AND APPARATUS FOR INTEGRATED VIDEO/IMAGE ENCODING/DECODING AND ENCRYPTION/DECRYPTION - An encryption-enabled entropy coder for a multimedia codec is disclosed. The entropy coder implements a randomized Huffman coding scheme without storing multiple sets of Huffman tables in a ROM. The entropy coder includes a ROM storing a single set of code tables, a table lookup section coupled to the ROM which converts symbols to original codewords and vice versa by performing table lookup, and a table randomizer section for converting original Huffman codewords to randomized Huffman codewords and vice versa using an isomorphic code generator algorithm. The table randomizer section performs the conversion based on a key hopping sequence generated by a pseudorandom bit generator using an encryption/decryption key. | 12-09-2010 |
20100278338 | CODING DEVICE AND METHOD WITH RECONFIGURABLE AND SCALABLE ENCRYPTION/DECRYPTION MODULES - A reconfigurable and scalable cryptography (encryption/decryption) system architecture and related method are described. The system utilizes a multiple-pass approach, each pass applying one cryptography algorithm with its own cryptography keys. The encrypted data can only be fully and correctly decrypted with the correct algorithms in the correct sequence (as determined by one or more security level parameters) and the correct cryptography keys. The system includes a multiple cryptography algorithm set section which is reconfigurable to perform multiple cryptography algorithms sequentially, and a cryptography controller which receives an input key set and a security level parameter. The cryptography controller reconfigures the multiple cryptography algorithm set section based on the security level parameter to perform multiple selected cryptography algorithms in a selected sequence. The cryptography controller also generates cryptography keys based on the input key set and provide the cryptography keys to the multiple cryptography algorithm set section. | 11-04-2010 |
20100254466 | METHOD FOR BEAMFORMING TRAINING AND COMMUNICATIONS APPARATUSES UTILIZING THE SAME - A communication system includes a trainee communications device and one or more trainer communications devices. The trainee communications device announces a first period of time for beamforming training, switches a receiving antenna pattern to a sector and stays in the sector for a second period of time. The trainer communications devices transmit one or more predetermined bit sequences in the first period of time. The predetermined bit sequences are transmitted in at least one sector. Each of the predetermined bit sequences carries an identifier identifying the transmitting trainer communications device. The trainee communications device further estimates channel characteristics and computes receiving antenna weighting vectors of the trainer communications devices by using the received predetermined bit sequences, respectively, and the trainer communications devices obtain pertinent information including the estimated channel characteristics and receiving time of the predetermined bit sequences about beamforming training from the trainee communications device. | 10-07-2010 |
20100222997 | ROAD SELECTION METHOD - A road selection method is provided, whereby obstructed routes are avoided. First, an off road point is input on a map. Based on the off road point, an on road point is selected, having a shortest straight line distance from the off road point where no obstacle lies therebetween. Thereafter, route planning is performed based on the on road point. When defining the map, the obstacles may comprise rivers, buildings and un-traversable objects on the map. | 09-02-2010 |
20100052803 | VOLTAGE CONTROLLED OSCILLATOR - An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency. | 03-04-2010 |
20090256635 | LINEAR-IN-DB VARIABLE GAIN AMPLIFIER - A variable gain amplifier (VGA) with a gain thereof exponential to a control voltage thereof. The variable gain amplifier (VGA) comprises an exponential DC converter, and a linear voltage multiplier. The exponential DC converter receives the control voltage and generates an exponential voltage which is exponential to the control voltage. The linear voltage multiplier is coupled to the exponential DC converter and has a gain proportional to the exponential voltage of the exponential DC converter. | 10-15-2009 |
20090033428 | VOLTAGE CONTROLLED OSCILLATOR - An integrated circuit is provided. The integrated circuit comprises a voltage controlled oscillator and a first compensation capacitor. The voltage controlled oscillator generates an oscillation signal. The first compensation capacitor, coupled in parallel to the voltage controlled oscillator, receives a control voltage to generate a negative temperature coefficient capacitance to compensate for frequency drift of the oscillation signal. The control voltage is temperature dependent. | 02-05-2009 |
20080303579 | MIXER WITH CARRIER LEAKAGE CALIBRATION - A mixer circuit. The mixer circuit comprises a double-balanced mixer and a carrier-leakage calibration cell. The double-balanced mixer has first and second input pairs whereby the first input pair receives the first differential input signal. The carrier-leakage calibration cell receives the second differential input signal and a differential calibration current and generates first and second output voltages to the second input pair of the double-balanced mixer. | 12-11-2008 |
20080284489 | TRANSCONDUCTOR AND MIXER WITH HIGH LINEARITY - A transconductor. The transconductor comprises first and second active device networks. The first active device network has a first node and a second node and comprises a first MOS transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. The second active device network has a first node and a second node respectively connected to the first and second nodes of the first active device network and comprises a second MOS transistor and a voltage drop generator. The second MOS transistor has a gate and a source respectively connected to the gate and the source of the first MOS transistor. The voltage drop generator is coupled between a drain of the second MOS transistor and the second nodes of the first and second active device networks and generates a voltage drop across the same. | 11-20-2008 |