MoSys, Inc. Patent applications |
Patent application number | Title | Published |
20160019029 | Method and Apparatus for Randomizer - A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output. | 01-21-2016 |
20150263737 | DELAY-LOCKED LOOP WITH INDEPENDENT PHASE ADJUSTMENT OF DELAYED CLOCK OUTPUT PAIRS - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 09-17-2015 |
20150244381 | DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 08-27-2015 |
20150019803 | PARTITIONED MEMORY WITH SHARED MEMORY RESOURCES AND CONFIGURABLE FUNCTIONS - A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The memory device includes a memory block having a plurality of banks, wherein each of the banks has a plurality of memory cells, and wherein the memory block has multiple ports. An output interface provides data on a second plurality of serial links. A cache coupled to the IO interface and to the plurality of banks, stores write data designated for a given memory cell location when the given memory cell location is currently being accessed, thereby avoiding a collision. Memory device includes one or more memory access controllers (MACs) coupled to the memory block and one or more arithmetic logic units (ALUs) coupled to the MACs. The ALUs perform one or more operations on data prior to the data being transmitted out of the IC via the IO, such as read/modify/write or statistics or traffic management functions, thereby reducing congestion on the serial links and offloading appropriate operations from the host to the memory device. | 01-15-2015 |
20140317460 | MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND BUILT-IN SELF-TESTING - A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively. | 10-23-2014 |
20140218083 | DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 08-07-2014 |
20140210531 | DELAY-LOCKED LOOP WITH INDEPENDENT PHASE ADJUSTMENT OF DELAYED CLOCK OUTPUT PAIRS - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 07-31-2014 |
20140082453 | SUBSTITUTE REDUNDANT MEMORY - An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together. | 03-20-2014 |
20140078841 | PROGRAMMABLE MEMORY BUILT IN SELF REPAIR CIRCUIT - An integrated circuit chip comprising at least one programmable built-in self-repair (PBISR) for repairing memory is described. The PBISR comprises an interface that receives signals external to the integrated chip. The PBISR further includes a port slave module that programs MBISR registers, program and instruction memory. The PBISR further comprises a programmable transaction engine and a programmable checker. Further, the MBISR comprises an eFUSE cache that implements logic to denote defective elements. | 03-20-2014 |
20130342241 | Pseudo-Supply Hybrid Driver - A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level. | 12-26-2013 |
20130336074 | Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. | 12-19-2013 |
20130332665 | MEMORY WITH BANK-CONFLICT-RESOLUTION (BCR) MODULE INCLUDING CACHE - A memory device includes a block of memory cells and a cache. The block of memory cells is not a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided. | 12-12-2013 |
20130313723 | SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS - A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays. | 11-28-2013 |
20130173970 | MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR - A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. | 07-04-2013 |
20130169314 | METHODS AND CIRCUITS FOR ADJUSTING PARAMETERS OF A TRANSCEIVER - Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold. | 07-04-2013 |
20130154698 | DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 06-20-2013 |
20130076450 | LOW NOISE BIAS CIRCUIT FOR A PLL OSCILLATOR - A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise. | 03-28-2013 |
20130003476 | MEMORY DEVICE INCLUDING A MEMORY BLOCK HAVING A FIXED LATENCY DATA OUTPUT - A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to receiving a read command and being clocked by a first clock signal having a selectable delay dependent upon a propagation delay for the read data to be output by a memory core. The clock generation unit is configured to generate a second clock signal having a selectable delay based on a system clock signal. The read data provided by the memory block in response to the second clock signal such that the read data has a latency that approximately the same, or is relatively fixed, for different frequencies of the system clock signal. | 01-03-2013 |
20120267769 | INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS - A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively. | 10-25-2012 |
20120250442 | Methods For Accessing DRAM Cells Using Separate Bit Line Control - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 10-04-2012 |
20120250441 | Separate Pass Gate Controlled Sense Amplifier - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 10-04-2012 |
20120221882 | Reducing Latency In Serializer-Deserializer Links - A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates. | 08-30-2012 |
20120140581 | Multiple Cycle Memory Write Completion - A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. | 06-07-2012 |
20120068339 | VLSI Package for High Performance Integrated Circuit - A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having functional components, wherein (a) the power lines and the data channels in the package substrate are coupled to the functional components of the substrate by conducting bumps, (b) the conducting balls coupling the data access channels in the PCB to the data channels in the package substrate are located along the edges of the package substrate; and (c) the conducting balls coupling the power lines in the PCB and the power lines in the package substrate are located in an interior portion of the package substrate. Also, an integrated circuit may further include a circuit substrate having active components, including a SerDes circuit at a center portion of the substrate. | 03-22-2012 |
20120056257 | Non-Volatile Memory System with Modified Memory Cells - A method and system in which an embedded memory is fabricated in accordance with a conventional logic process includes one or more non-volatile memory cells, each having an access transistor and a capacitor, which share a common floating gate electrode. The coupling capacitor is provided with a dielectric layer having a thickness greater than the dielectric layer of the access transistor. Regions under the capacitor are implanted with a high dose implant to form an electrically shorted doped area in the channel region of the capacitor. The high dose implant improves the coupling ratio of the capacitor and enhances the uniformity of the capacitor's oxide layer. | 03-08-2012 |
20120047260 | Data Synchronization For Circuit Resources Without Using A Resource Buffer - A resource synchronizer synchronizes transmission of data to a SerDes of a device so that the SerDes is capable of providing the data to a resource of the device without buffering the data between the SerDes and the resource. | 02-23-2012 |
20120025397 | Semiconductor Chip Layout - A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays. | 02-02-2012 |
20120025347 | Method of forming a MIM capacitor - An embedded memory system includes an array of dynamic random access memory (DRAM) cells, on the same substrate as an array of logic transistors. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The eDRAM system includes fewer metal layers in the logic area than in the memory area | 02-02-2012 |
20120025285 | SYSTEM WITH LOGIC AND EMBEDDED MIM CAPACITOR - An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the logic region than in the memory region | 02-02-2012 |
20110234282 | Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope - A method and structure for characterizing signals used to operate high speed circuitry on an integrated circuit chip. Signals to be characterized, such as column select signals, sense amplifier enable signals and word line signals, are generated on the chip. Each of these signals has an identical corresponding pattern during successive cycles of an input clock signal. These signals are sampled on the chip with successively delayed versions of the input clock signal, thereby generating a plurality of data samples that represent the patterns of the signals over a cycle of the input clock signal. The data samples are stored in a memory block on the chip, and are subsequently serialized and transferred to a location external to the chip. | 09-29-2011 |
20110216596 | Reliability Protection for Non-Volatile Memories - A non-volatile memory cell having enhanced protection against mobile ions. The electric field within the memory cell is controlled in a manner that minimizes migration of mobile ions toward the floating gate. Each conductive layer in the memory cell is biased to reduce the flow of mobile ions toward the floating gate. The memory cell is preferably manufactured using a conventional logic process. | 09-08-2011 |
20110209002 | Programmable Test Engine (PCDTE) For Emerging Memory Technologies - A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters. The PCDTE may transmit information off of the chip to exercise transmit/receive circuitry of the chip. | 08-25-2011 |
20110191619 | Reducing Latency in Serializer-Deserializer Links - A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates. | 08-04-2011 |
20110191564 | Hierarchical Organization Of Large Memory Blocks - A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency. | 08-04-2011 |
20110191548 | High Utilization Multi-Partitioned Serial Memory - A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency. | 08-04-2011 |
20110188335 | Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. | 08-04-2011 |
20110149673 | Three State Word Line Driver ForA DRAM Memory Device - A memory bank includes an array of memory cells, word lines for accessing the memory cells, and word line drivers coupled to the word lines. When the memory bank is being accessed, the word line drivers are coupled to receive a first supply voltage, which is applied to the non-selected word lines of the memory bank. The first supply voltage turns off access transistors of the memory cells coupled to the non-selected word lines. When the memory bank is not being accessed, the word line drivers are coupled to receive a second supply voltage, which is applied to each of the word lines of the memory bank. The second supply voltage turns off the access transistors of the memory cells coupled of the word lines. The first and second supply voltages are selected such that the first supply voltage turns off the access transistors harder than the second supply voltage. | 06-23-2011 |
20110141812 | Method and Apparatus for Restoring Data in a Non-Volatile Memory - A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data. | 06-16-2011 |
20110085398 | Multiple Cycle Memory Write Completion - A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. | 04-14-2011 |
20100275170 | Porting Analog Circuit Designs - A computer-based method of converting an analog integrated circuit design from a source technology to a target technology, by providing a computer readable source schematic file and a computer readable source layout file for the analog integrated circuit design in the source technology, providing a computer readable technology transfer file that includes conversion tables between properties of the source technology and properties of the target technology, converting the source schematic file in the source technology to a target schematic file in the target technology with the computer using the technology transfer file, and converting the source layout file in the source technology to a target layout file in the target technology with the computer using the technology transfer file. | 10-28-2010 |
20100271094 | Signal Alignment System - Through the use of a multi-step sweep, the present invention is capable of increasing the speed and improving the error resistance of a signal alignment. In a specific embodiment of the invention, a method for the signal alignment of a target signal and an adjustable signal is disclosed. The target signal is sampled using three or more phase shifted versions of the adjustable signal to obtain a group of target signal state values. Next, through reference to the group of target signal state values it is determined that an edge of the target signal lies between a first phase shifted version and a second consecutive phase shifted version. In response, the first phase shifted version is selected as the starting point for a second sweep. During the second sweep, the phase of the first phase shifted version is sequentially adjusted in relatively small incremental steps to minimize the phase difference relative to the target signal. | 10-28-2010 |
20100235590 | Multi-bank Multi-port Architecture - A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports. | 09-16-2010 |
20100208530 | Two Bits Per Cell Non-Volatile Memory Architecture - A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier. | 08-19-2010 |
20100205504 | Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process - A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure. | 08-12-2010 |
20100202203 | Data restoration method for a non-volatile memory - A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data. The manner in which data is restored will depend on whether the data changed because of an erase failure or a program failure. If only a program failure occurred then the data will be reprogrammed without an intervening erase step. If the data experienced an erase failure, then the data will be erased prior to being programmed with correct data. | 08-12-2010 |
20100140680 | Double Polysilicon Process for Non-Volatile Memory - A process flow for creating a non-volatile memory cell, the process flow including the steps of forming a doped well in a semiconducting portion of a substrate, forming a gate dielectric layer on top of the substrate, depositing a first polysilicon layer on top of the gate dielectric layer, patterning and etching the first polysilicon layer, selectively oxidizing the first polysilicon layer, implanting lightly-doped source/drain regions into the well, forming sidewall spacers adjacent the first polysilicon layer, implanting source/drain regions into the well, thereby forming a channel area, depositing a dielectric layer on top of the first polysilicon layer, depositing a second polysilicon layer on top of the dielectric layer, forming a masking layer on the second polysilicon layer, and etching both the second polysilicon layer and the dielectric layer using the masking layer. | 06-10-2010 |
20100120213 | Embedded DRAM with multiple gate oxide thicknesses - A method of forming an embedded DRAM cell having multiple-thickness gate dielectrics. An oxidation-enhancing dopant is selectively implanted into a well region in an area that is exposed by a first mask. A thermal oxidation step simultaneously produces the field dielectric for two distinct devices each having a different oxide thickness. The method is applicable to quad-density DRAM cells using fewer oxidation steps. The method is also applicable to planar DRAM cells, and does not require increasing the number of masks during the fabrication of planar DRAM cells. | 05-13-2010 |
20100118596 | Embedded DRAM with bias-independent capacitance - An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed. | 05-13-2010 |
20080209303 | Error Detection/Correction Method - A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions. | 08-28-2008 |