NetSpeed Systems Patent applications |
Patent application number | Title | Published |
20150324288 | SYSTEM AND METHOD FOR IMPROVING SNOOP PERFORMANCE - The present disclosure is directed to hardware hash tables, and more specifically, to generation of a cache coherent system such as in a Network on Chip (NoC). The present disclosure is further directed to a directory structure that includes a new field, referred to, for instance as, encoded value, which indicates the original owner of a dirty line. As an original holder may have held or modified the original line, by tracking the original holder, example implementations can track the agents that are potentially dirty, as the encoded value can indicate the agent with the most recently unique line, which can then be shared with the other agents. | 11-12-2015 |
20150288596 | SYSTEMS AND METHODS FOR SELECTING A ROUTER TO CONNECT A BRIDGE IN THE NETWORK ON CHIP (NOC) - The present disclosure is directed to systems and methods for connecting hosts to any router by the use of bridges. Example implementations described herein are directed to determining connections between routers and hosts based on the topology of the NoC and cost functions. Unused routers may also be removed from the NoC configuration and unused directional host ports of routers may be utilized to connect hosts together depending on a cost function and the desired implementation. | 10-08-2015 |
20150288531 | INTEGRATED NOC FOR PERFORMING DATA COMMUNICATION AND NOC FUNCTIONS - The present disclosure is directed to a NoC interconnect that consolidates one or more Network on Chip functions into one Network on Chip. The present disclosure is further directed to a Network on Chip (NoC) interconnect comprising a plurality of first agents, wherein each agent can be configured to communicate with other ones of the plurality of first agents. NoC of the present disclosure can further include a second agent configured to perform a NoC function, and a bridge associated with the second agent, wherein the bridge can be configured to packetize messages from the second agent to the plurality of first agents, and to translate messages from the plurality of first agents to the second agent. | 10-08-2015 |
20150236963 | QOS IN A SYSTEM WITH END-TO-END FLOW CONTROL AND QOS AWARE BUFFER ALLOCATION - The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the NoC to compel the acceptance of data and the allocation of an appropriate buffer. Messages sent to the agent may also have a priority associated with the message, wherein higher priority messages have automatic bandwidth allocation and lower priority messages are processed using a handshake protocol. | 08-20-2015 |
20150188847 | STREAMING BRIDGE DESIGN WITH HOST INTERFACES AND NETWORK ON CHIP (NoC) LAYERS - Systems and methods described herein are directed to streaming bridge design implementations that help interconnect and transfer transaction packets between multiple source and destination host interfaces through a Network on Chip (NoC) interconnect, which includes a plurality of NoC router layers and virtual channels (VCs) connecting the router layers. Implementations are configured to support a variety of different traffic profiles, each having a different set of traffic flows. Streaming bridge design implementation can divide streaming bridge into a streaming TX bridge and a streaming RX bridge, wherein TX bridge is operatively coupled with host TX interfaces and RX bridge is operatively coupled with host RX interfaces, and where TX bridge forwards transaction packets from host TX interfaces to different router layers/VCs of NoC, and RX bridge, on the other hand, receives packets from NoC router layers/VCs and transmits the packets to host RX interfaces based on Quality of Service. | 07-02-2015 |
20150186277 | CACHE COHERENT NOC WITH FLEXIBLE NUMBER OF CORES, I/O DEVICES, DIRECTORY STRUCTURE AND COHERENCY POINTS - The present application is directed to designing a NoC interconnect architecture by a means of specification, which can indicate implementation parameters of the NoC including, but not limited to, number of NoC agent interfaces, and number of cache coherency controllers. Flexible identification of NoC agent interfaces and cache coherency controllers allows for an arbitrary number of agents to be associated with the NoC upon configuring the NoC from the specification. | 07-02-2015 |
20150178435 | AUTOMATIC PIPELINING OF NOC CHANNELS TO MEET TIMING AND/OR PERFORMANCE - Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels. | 06-25-2015 |
20150143050 | REUSE OF DIRECTORY ENTRIES FOR HOLDING STATE INFORMATION - The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory. | 05-21-2015 |
20150117261 | USING MULTIPLE TRAFFIC PROFILES TO DESIGN A NETWORK ON CHIP - The present application is directed to designing an efficient Network on Chip (NoC) interconnect architecture that is adaptable to varied interface protocols of different SoC components/hosts and is compliant to handle different types and models of traffic profiles. Aspects of the present application include a method, which may involve utilizing multiple traffic profiles described in a specification to generate a NoC that satisfies all the traffic profiles. Such a NoC interconnect architecture can be formed from multiple traffic profiles by generating a single consolidated traffic profile from individual or subset based dependency graphs of the multiple traffic profiles. | 04-30-2015 |
20150103822 | NOC INTERFACE PROTOCOL ADAPTIVE TO VARIED HOST INTERFACE PROTOCOLS - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that support a variety of different component protocols each having different sets of data and/or metadata even after the NoC is designed and finalized. Example implementations include, automatically changing format of packets received from an originating SoC component by an originating bridge based on a NoC interface protocol and then transmitting the packet across the NoC interconnect to a destination bridge. The format may again be changed based on the protocol of the destination SoC component. The proposed protocol can be configured to map various transactions presented to it, be they packets belonging to the physical, data link layer, network layer or transport layer. As part of the mapping process, virtual channels for latency or deadlock avoidance may be created and may be maintained for the entire life of the packet within the NoC. | 04-16-2015 |
20150052309 | COMBINING ASSOCIATIVITY AND CUCKOO HASHING - Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash table applicable to CPU caches and cache coherence directories. Set-associative tables and cuckoo hashing are combined for construction of a directory table of a directory based cache coherence controller. A method may allow configuration of C cuckoo ways, where C is an integer greater than or equal to 2, wherein each cuckoo way C | 02-19-2015 |
20150043575 | SUPPORTING MULTICAST IN NOC INTERCONNECT - Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein. | 02-12-2015 |
20150036536 | AUTOMATIC NoC TOPOLOGY GENERATION - Example implementations described herein are directed to automatically determine an optimal NoC topology using heuristic based optimizations. First, an optimal orientation of ports of various hosts is determined based on the system traffic and connectivity specification. Second, the NoC routers to which the host's port are directly connected to are determined in the NoC layout. Third, an optimal set of routes are computed for the system traffic and the required routers and channels along the routes are allocated forming the full NoC topology. The three techniques can be applied in any combination to determine NoC topology, host port orientation, and router connectivity that reduces load on various NoC channels and improves latency, performance, and message transmission efficiency between the hosts. | 02-05-2015 |
20150032437 | SYSTEM LEVEL SIMULATION IN NETWORK ON CHIP ARCHITECTURE - Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect. | 01-29-2015 |
20150016257 | IDENTIFICATION OF INTERNAL DEPENDENCIES WITHIN SYSTEM COMPONENTS FOR EVALUATING POTENTIAL PROTOCOL LEVEL DEADLOCKS - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels. | 01-15-2015 |
20140301241 | MULTIPLE HETEROGENEOUS NOC LAYERS - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the topology of different NoC layers and maps system traffic flows to various routes in various NoC layers that satisfies the latency requirements of the flows. The number of layers and their topology is dynamically allocated and optimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers and updating the topology of the NoC layers as they are mapped. In addition to allocating additional NoC layers and topologies to satisfy the latency requirements of the flows, the NoC layers and topologies may also be allocated to satisfy the bandwidth requirements of the flows or to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various flows. | 10-09-2014 |
20140211622 | CREATING MULTIPLE NOC LAYERS FOR ISOLATION OR AVOIDING NOC TRAFFIC CONGESTION - Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem. | 07-31-2014 |
20140204764 | QOS IN HETEROGENEOUS NOC BY ASSIGNING WEIGHTS TO NOC NODE CHANNELS AND USING WEIGHTED ARBITRATION AT NOC NODES - Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations. | 07-24-2014 |
20140204735 | AUTOMATIC DEADLOCK DETECTION AND AVOIDANCE IN A SYSTEM INTERCONNECT BY CAPTURING INTERNAL DEPENDENCIES OF IP CORES USING HIGH LEVEL SPECIFICATION - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips. | 07-24-2014 |
20140177648 | TAGGING AND SYNCHRONIZATION FOR FAIRNESS IN NOC INTERCONNECTS - Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication. | 06-26-2014 |
20140177473 | HIERARCHICAL ASYMMETRIC MESH WITH VIRTUAL ROUTERS - A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers. | 06-26-2014 |
20140115298 | ASYMMETRIC MESH NoC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links. | 04-24-2014 |
20140115218 | ASYMMETRIC MESH NoC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links. | 04-24-2014 |
20140098683 | HETEROGENEOUS CHANNEL CAPACITIES IN AN INTERCONNECT - Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system. | 04-10-2014 |
20140068132 | AUTOMATIC CONSTRUCTION OF DEADLOCK FREE INTERCONNECTS - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips. | 03-06-2014 |