SMART Modular Technologies, Inc. Patent applications |
Patent application number | Title | Published |
20130132639 | NON-VOLATILE MEMORY PACKAGING SYSTEM WITH CACHING AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface. | 05-23-2013 |
20130128685 | MEMORY MANAGEMENT SYSTEM WITH POWER SOURCE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level. | 05-23-2013 |
20130103887 | COMPUTING SYSTEM WITH NON-DISRUPTIVE FAST MEMORY RESTORE MECHANISM AND METHOD OF OPERATION THEREOF - A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the high-speed memory; and formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface. | 04-25-2013 |
20130083473 | EXTENDED CAPACITY MEMORY SYSTEM WITH LOAD RELIEVED MEMORY AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof | 04-04-2013 |
20130039128 | NON-VOLATILE DYNAMIC RANDOM ACCESS MEMORY SYSTEM WITH NON-DELAY-LOCK-LOOP MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting a back-up interface through a first multiplexer and a second multiplexer, asserting an on-board termination, and accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including: selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof, disabling the on-board termination, and accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency. | 02-14-2013 |
20130036264 | MULTI-RANK MEMORY MODULE THAT EMULATES A MEMORY MODULE HAVING A DIFFERENT NUMBER OF RANKS - A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller. | 02-07-2013 |
20120060009 | DYNAMIC BACK-UP STORAGE SYSTEM WITH RAPID RESTORE AND METHOD OF OPERATION THEREOF - A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device. | 03-08-2012 |
20110125966 | MULTI-RANK MEMORY MODULE THAT EMULATES A MEMORY MODULE HAVING A DIFFERENT NUMBER OF RANKS - A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller. | 05-26-2011 |
20100238754 | CLOCK AND POWER FAULT DETECTION FOR MEMORY MODULES - A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module. | 09-23-2010 |
20100211765 | CLOCK AND POWER FAULT DETECTION FOR MEMORY MODULES - A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module. | 08-19-2010 |
20100020515 | METHOD AND SYSTEM FOR MANUFACTURING MICRO SOLID STATE DRIVE DEVICES - A method of manufacturing a stacked module is disclosed and in particular a micro solid state device (MSSD). | 01-28-2010 |