SOCIONEXT INC. Patent applications |
Patent application number | Title | Published |
20160116533 | DIAGNOSTIC APPARATUS - A diagnostic apparatus is disclosed, which includes a processor configured to extract, from a plurality of components included in an integrated circuit to be diagnosed, a failure candidate based on test results obtained from actual operations of the integrated circuit, the actual operations being implemented by individually applying a plurality of types of test patterns to the integrated circuit, extract, from a plurality of pass patterns of the test patterns, a pass pattern with which a signal is transmitted to the failure candidate, based on log data obtained from simulations with the test patterns, the test results of the plurality of pass patterns being normal, and execute, using a fail pattern of the test patterns and the extracted pass patterns, a failure simulation assuming that the failure candidate is failed, the test result of the fail pattern being abnormal. | 04-28-2016 |
20160085557 | PROCESSOR AND PROCESSING METHOD OF VECTOR INSTRUCTION - A processor includes: a plurality of pipelines including a first pipeline and a second pipeline and configured to pipeline-process vector instructions including load instructions with respect to a memory, and when an instruction issuance controller configured to decode a vector instruction read out from an instruction memory and issue instructions to the pipelines issues a first load instruction with respect to a first region of a memory to the first pipeline and a second load instruction with respect to the first region of the memory is being processed in the second pipeline, a processing order in the first load instruction in the first pipeline is changed on the basis of an offset value determined according to a number of cycles that have been processed already in the second load instruction so that an access address of the first load instruction matches an access address of the second load instruction. | 03-24-2016 |
20160048330 | COMMAND PROCESSING APPARATUS, METHOD AND INTEGRATED CIRCUIT APPARATUS - A command processing apparatus that processes a plurality of commands which are issued independently from a first master and a second master is provided. The command processing apparatus sequentially issues commands to a storage apparatus including a plurality of banks. The first master issues a first command and a second command in order to the command processing apparatus, with the first command being a command to request access to a first bank and the second command being a command to request access to a second bank different from the first bank. When the second master issues a third command to the command processing apparatus during an interval between issuance of the first command and the second command, the command processing apparatus issues the second command to the storage apparatus consecutively after the first command by prioritizing the second command over the third command. | 02-18-2016 |
20150295086 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. | 10-15-2015 |