SOITEC Patent applications |
Patent application number | Title | Published |
20160042989 | PROCESS FOR MANUFACTURING A COMPOSITE STRUCTURE - The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer. | 02-11-2016 |
20150325686 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXATION, AND RELATED STRUCTURES - Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods. | 11-12-2015 |
20150214372 | SOI FINFET WITH REDUCED FIN WIDTH DEPENDENCE - The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor. | 07-30-2015 |
20150191344 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON OPPOSING SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES - Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods. | 07-09-2015 |
20150179520 | METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES USING LASER LIFT-OFF PROCESS, AND RELATED SEMICONDUCTOR STRUCTURES - Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate. | 06-25-2015 |
20150128860 | DEPOSITION SYSTEMS HAVING DEPOSITION CHAMBERS CONFIGURED FOR IN-SITU METROLOGY WITH RADIATION DEFLECTION AND RELATED METHODS - Deposition chambers ( | 05-14-2015 |
20150122313 | MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES - The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate with a lower surface and an upper surface; providing a second substrate with a lower surface and an upper surface; bonding the first substrate to the second substrate at the upper surface of the first substrate and the lower surface of the second substrate; and subsequently forming at least one first solar cell layer on the lower surface of the first substrate and at least one second solar cell layer at the upper surface of the second substrate. | 05-07-2015 |
20150059832 | MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES - The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a final base substrate; providing a first engineered substrate comprising a first zipper layer and a first seed layer; providing a second substrate; transferring the first seed layer to the final base substrate; forming at least one first solar cell layer on the first seed layer after transferring the first seed layer to the final base substrate, thereby obtaining a first wafer structure; forming at least one second solar cell layer on the second substrate, thereby obtaining a second wafer structure; and bonding the first and the second wafer structure to each other. | 03-05-2015 |
20150027519 | MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES - The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate, providing a second substrate having a lower surface and an upper surface, forming at least one first solar cell layer on the first substrate to obtain a first wafer structure, forming at least one second solar cell layer on the upper surface of the second substrate to obtain a second wafer structure, and bonding the first wafer structure to the second wafer structure, wherein the at least one first solar cell layer is bonded to the lower surface of the second substrate and removing the first substrate. | 01-29-2015 |
20150014824 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The present invention relates to a method for fabricating a substrate for a semiconductor device comprising an interface region between a first layer and a second layer having different electrical properties and an exposed surface, wherein at least the second layer includes defects and/or dislocations, the method comprising the steps of: a) removing material at one or more locations of the defects and/or dislocations, thereby forming pits, wherein the pits intersect the interface region, and b) passivating the pits. The invention also relates to a corresponding semiconductor device structure. | 01-15-2015 |
20150014822 | METHOD OF TESTING A SEMICONDUCTOR ON INSULATOR STRUCTURE AND APPLICATION OF SAID TEST TO THE FABRICATION OF SUCH A STRUCTURE - The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (Q | 01-15-2015 |
20140370695 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The present invention relates to a method for fabricating a semiconductor structure comprising a semiconductor layer and a metallic layer, to improve the breakdown voltage properties of the device and reduce leakage currents, the method comprises the steps of a) providing a semiconductor layer comprising defects and/or dislocations; b) removing material at one or more locations of the defects and/or dislocations thereby forming pits in the semiconductor layer, c) passivating the pits, and c) providing the metallic layer over the semiconductor layer. The invention also relates to a corresponding semiconductor structure. | 12-18-2014 |
20140339681 | METHOD FOR FABRICATING A COMPOSITE STRUCTURE TO BE SEPARATED BY EXFOLIATION - The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing:
| 11-20-2014 |
20140327013 | METHOD FOR MANUFACTURING A THICK EPTAXIAL LAYER OF GALLIUM NITRIDE ON A SILICON OR SIMILAR SUBSTRATE AND LAYER OBTAINED USING SAID METHOD - The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of B | 11-06-2014 |
20140326416 | METHOD FOR SEPARATING A LAYER FROM A COMPOSITE STRUCTURE - The disclosure relates to a method for separating a layer from a composite structure, the structure comprising a composite stack formed from at least a support substrate, which is partially transparent at a determined wavelength, the layer to be separated and a separation layer interposed between the support substrate and the layer to be separated, the method comprising irradiation of the separation layer through the support substrate by means of incident light ray at the determined wavelength in order to induce weakening or separation by exfoliation of the separation layer, the light ray being inclined so as to form an angle of incidence Θ such that θ>θ | 11-06-2014 |
20140321225 | SENSE AMPLIFIER WITH DUAL GATE PRECHARGE AND DECODE TRANSISTORS - The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T | 10-30-2014 |
20140284768 | SEMICONDUCTOR ON INSULATOR STRUCTURE WITH IMPROVED ELECTRICAL CHARACTERISTICS - A semiconductor structure comprising a first semiconductor layer, a bulk semiconductor layer, an insulation layer between the first semiconductor layer and the bulk semiconductor layer, a first implanted region that is at least partially within the insulation layer; and a second doped region that is at least partially within the bulk semiconductor layer, wherein the first implanted region has an implant profile that shows a maximum within the insulation layer and a tail extending within the bulk semiconductor layer so as to inhibit the diffusion of a second doping material of the second doped region within the insulation layer. | 09-25-2014 |
20140264408 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 09-18-2014 |
20140264371 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 09-18-2014 |
20140264265 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 09-18-2014 |
20140217553 | TEMPLATE LAYERS FOR HETEROEPITAXIAL DEPOSITION OF III NITRIDE SEMICONDUCTOR MATERIALS USING HVPE PROCESSES - Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods. | 08-07-2014 |
20140217419 | SEMICONDUCTOR STRUCTURES INCLUDING STACKS OF INDIUM GALLIUM NITRIDE LAYERS - Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods. | 08-07-2014 |
20140183601 | METHOD FOR TRANSFERRING A LAYER OF A SEMICONDUCTOR AND SUBSTRATE COMPRISING A CONFINEMENT STRUCTURE - A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that is distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into the donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer. | 07-03-2014 |
20140158041 | METHOD AND DEVICE FOR FABRICATING A LAYER IN SEMICONDUCTOR MATERIAL - The invention concerns a method for fabricating a substrate in semiconductor material characterized in that it comprises the steps of: starting from a donor substrate in a first semiconductor material at an initial temperature, contacting a surface of the donor substrate with a bath of a second semiconductor material held in the liquid state at a temperature higher than the initial temperature, the second semiconductor material being chosen so that its melting point is equal to or lower than the melting point of the first semiconductor material, solidifying the bath material on the surface to thicken the donor substrate with a solidified layer. The invention also concerns a device for implementing the method. | 06-12-2014 |
20140144486 | ACTIVE COOLING FOR A CONCENTRATED PHOTOVOLTAIC CELL - A wasted heat harvesting device for harvesting electricity including a switching device configured to convey a magnetic field from a first region to at least a second region when the temperature of the switching device crosses a predetermined temperature. | 05-29-2014 |
20140138796 | STRAIN RELAXATION USING METAL MATERIALS AND RELATED STRUCTURES - Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods. | 05-22-2014 |
20140084290 | MANUFACTURING METHOD FOR A SEMICONDUCTOR ON INSULATOR TYPE SUBSTRATE FOR RADIOFREQUENCY APPLICATIONS - The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radiofrequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate ( | 03-27-2014 |
20140077751 | MODULAR ELECTRICAL ENERGY PRODUCTION DEVICE - A modular electrical energy production device that includes a plurality of input connectors; a regulator unit coupled electrically to the input connectors; a converter unit, a storage device and an optional first output connector, coupled electrically to the regulator unit; a control unit; and a second output connector coupled electrically to the converter unit. The invention also concerns an electrical energy production system that includes a first modular electrical energy production device and a second modular electrical energy production device. | 03-20-2014 |
20140065759 | METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE - A method for bonding first and second wafers by molecular adhesion. The method includes placing the wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure above which initiation of bonding wave propagation is prevented, bringing the first wafer and the second wafer into alignment and contact, and spontaneously initiating the propagation of a bonding wave between the wafers after they are in contact solely by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure. | 03-06-2014 |
20140041584 | ABATEMENT OF REACTION GASES FROM GALLIUM NITRIDE DEPOSITION - Systems for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment is optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material. | 02-13-2014 |
20140038388 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE HAVING LOW ELECTRICAL LOSSES, AND CORRESPONDING STRUCTURE - A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes. | 02-06-2014 |
20140030877 | PROCESS TO DISSOLVE THE OXIDE LAYER IN THE PERIPHERAL RING OF A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - A process for avoiding formation of a Si—SiO | 01-30-2014 |
20140027714 | QUANTUM WELL THERMOELECTRIC COMPONENT FOR USE IN A THERMOELECTRIC DEVICE - A quantum well thermoelectric component for use in a thermoelectric device based on the thermoelectric effect,
| 01-30-2014 |
20140015023 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 01-16-2014 |
20140014029 | METHOD OF FABRICATING A COMPOSITE STRUCTURE WITH A STABLE BONDING LAYER OF OXIDE - A method of preventing microcavity formation in the bonding layer of a composite structure resulting from creep and thermal expansion due to high temperature exposure of the composite structure The method includes the steps of providing the thin film with a thickness of 5 micrometers or less; providing the bonding layer of oxide with a thickness that is equal to or greater than the thickness of the thin film with the bonding layer formed by low pressure chemical vapor deposition. The thin film or support substrate have a mean thermal expansion coefficient of 7×10 | 01-16-2014 |
20140001642 | INTERPOSERS INCLUDING FLUIDIC MICROCHANNELS AND RELATED STRUCTURES AND METHODS | 01-02-2014 |
20140001604 | SEMICONDUCTOR STRUCTURES INCLUDING FLUIDIC MICROCHANNELS FOR COOLING AND RELATED METHODS | 01-02-2014 |
20130341756 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 12-26-2013 |
20130327266 | TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER - The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl | 12-12-2013 |
20130323861 | PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS - The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate. | 12-05-2013 |
20130309841 | METHOD FOR MOLECULAR BONDING OF SILICON AND GLASS SUBSTRATES - The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates. | 11-21-2013 |
20130302970 | A METHOD OF HIGH TEMPERATURE LAYER TRANSFER - A method of transferring a layer from a donor substrate onto a receiving substrate comprises ionic implantation of at least one species into the donor substrate and forming a layer of concentration of the species intended to form microcavities or platelets; bonding the donor substrate with the receiving substrate by wafer bonding; and splitting at high temperature to split the layer in contact with the receiving substrate by cleavage, at a predetermined cleavage temperature, at the layer of microcavities or platelets formed in the donor substrate. The method further comprises, after the first implantation step and before the splitting step, ionic implantation of silicon ions into the donor substrate to form a layer of concentration of silicon ions in the donor substrate, the layer of concentration of silicon ions at least partially overlapping the layer of concentration of the species intended to form microcavities or platelets. | 11-14-2013 |
20130294038 | ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND PROCESS FOR MANUFACTURING SUCH A DEVICE - The invention relates to an electronic device for radio frequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/m K and a superficial layer having a thickness of at least 5 μm, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/m K. The invention also relates to two processes for manufacturing such a device. | 11-07-2013 |
20130244410 | METHODS OF FORMING BULK III-NITRIDE MATERIALS ON METAL-NITRIDE GROWTH TEMPLATE LAYERS, AND STRUCTURES FORMED BY SUCH METHODS - Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. | 09-19-2013 |
20130234157 | METHODS FOR FORMING GROUP III-NITRIDE MATERIALS AND STRUCTURES FORMED BY SUCH METHODS - Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer. | 09-12-2013 |
20130234148 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING III-V SEMICONDUCTOR MATERIAL USING SUBSTRATES COMPRISING MOLYBDENUM, AND STRUCTURES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material such as GaN over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride. | 09-12-2013 |
20130221496 | METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer. | 08-29-2013 |
20130217206 | METHODS OF PROVIDING THIN LAYERS OF CRYSTALLINE SEMICONDUCTOR MATERIAL, AND RELATED STRUCTURES AND DEVICES - Methods of fabricating semiconductor devices include forming a metal silicide in a portion of a crystalline silicon layer, and etching the metal silicide using an etchant selective to the metal silicide relative to the crystalline silicon to provide a thin crystalline silicon layer. Silicon-on-insulator (SOI) substrates may be formed by providing a layer of crystalline silicon over a base substrate with a dielectric material between the layer of crystalline silicone and the base substrate, and thinning the layer of crystalline silicon by forming a metal silicide layer in a portion of the crystalline silicon, and then etching the metal silicide layer using an etchant selective to the metal silicide layer relative to the crystalline silicon. | 08-22-2013 |
20130214423 | METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES INCLUDING INTERPOSERS WITH CONDUCTIVE VIAS, AND RELATED STRUCTURES AND DEVICES - Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods. | 08-22-2013 |
20130210171 | METHOD FOR MOLECULAR ADHESION BONDING WITH COMPENSATION FOR RADIAL MISALIGNMENT - A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment. | 08-15-2013 |
20130207244 | PROCESS FOR FABRICATING A SILICON-ON-INSULATOR STRUCTURE - Embodiments of to invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s. | 08-15-2013 |
20130199441 | GAS INJECTORS FOR CHEMICAL VAPOUR DEPOSITION (CVD) SYSTEMS AND CVD SYSTEMS WITH THE SAME - The present invention provides improved gas injectors for use with CVD (chemical vapour deposition) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high volume manufacturing of GaN substrates. | 08-08-2013 |
20130181308 | METHODS OF FABRICATING DILUTE NITRIDE SEMICONDUCTOR MATERIALS FOR USE IN PHOTOACTIVE DEVICES AND RELATED STRUCTURES - Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a vapor phase epitaxy (HVPE) chamber. | 07-18-2013 |
20130175672 | LOW TEMPERATURE LAYER TRANSFER PROCESS USING DONOR STRUCTURE WITH MATERIAL IN RECESSES IN TRANSFER LAYER, SEMICONDUCTOR STRUCTURES FABRICATED USING SUCH METHODS - Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods. | 07-11-2013 |
20130164874 | METHODS OF FORMING DILUTE NITRIDE MATERIALS FOR USE IN PHOTOACTIVE DEVICES AND RELATED STRUCTURES - Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements. | 06-27-2013 |
20130161637 | SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE LAYERS AND OVERLYING SEMICONDUCTOR LAYERS HAVING CLOSELY MATCHING COEFFICIENTS OF THERMAL EXPANSION, AND RELATED METHODS - Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments. | 06-27-2013 |
20130161636 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES USING THERMAL SPRAY PROCESSES, AND SEMICONDUCTOR STRUCTURES FABRICATED USING SUCH METHODS - Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods. | 06-27-2013 |
20130160802 | PROCESSES AND SYSTEMS FOR REDUCING UNDESIRED DEPOSITS WITHIN A REACTION CHAMBER ASSOCIATED WITH A SEMICONDUCTOR DEPOSITION SYSTEM - Processes and systems are used to reduce undesired deposits within a reaction chamber associated with a semiconductor deposition system. A cleaning gas may be caused to flow through at least one gas flow path extending through at least one gas furnace, and the heated cleaning gas may be introduced into a reaction chamber to remove at least a portion of undesired deposits from within the reaction chamber. | 06-27-2013 |
20130160702 | METHODS OF GROWING III-V SEMICONDUCTOR MATERIALS, AND RELATED SYSTEMS - Methods and systems are increase the number of Group V ions formed from Group V precursors in methods of forming III-V semiconductor materials to enhance the growth rate of the III-V semiconductor material. In some embodiments, a Group V precursor is heated and at least partially decomposed in a heated diffuser to form Group V ions. In additional embodiments, microwave energy is applied to a Group V precursor and the Group V precursor is at least partially decomposed to form Group V ions. Group III ions are also formed, and the Group III and Group V ions are used to form a III-V semiconductor material within a chamber. | 06-27-2013 |
20130154065 | PROCESS FOR TREATING A SUBSTRATE USING A LUMINOUS FLUX OF DETERMINED WAFELENGTH, AND CORRESPONDING SUBSTRATE - A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer, layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and grows as the temperature rises. The luminous flux may be applied in several places of the surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer. | 06-20-2013 |
20130139946 | PROCESS FOR BONDING TWO SUBSTRATES - The invention relates to a method for bonding two substrates, in particular two semiconductor substrates which, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C. | 06-06-2013 |
20130137247 | THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS - The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases. | 05-30-2013 |
20130134547 | METHOD FOR FABRICATING A LOCALLY PASSIVATED GERMANIUM-ON-INSULATOR SUBSTRATE - The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention. | 05-30-2013 |
20130126896 | III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. | 05-23-2013 |
20130111719 | METHOD FOR IMPLANTING A PIEZOELECTRIC MATERIAL - A method of producing a structure made of a piezoelectric material, including: a) production of a stack including at least one metal layer and at least one conductive layer on a substrate made of piezoelectric material, wherein at least one electrical contact is established between the conductive layer and a metal element outside the stack; b) an ionic and/or atomic implantation, through the conductive layer and the metal layer; c) transfer of the substrate onto a transfer substrate, followed by fracturing of the transferred piezoelectric substrate, in an embrittlement area. | 05-09-2013 |
20130105932 | METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE | 05-02-2013 |
20130104802 | GALLIUM TRICHLORIDE INJECTION SCHEME | 05-02-2013 |
20130100749 | NANO-SENSE AMPLIFIER - A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. | 04-25-2013 |
20130075868 | METHODS OF TRANSFERRING LAYERS OF MATERIAL IN 3D INTEGRATION PROCESSES AND RELATED STRUCTURES AND DEVICES - Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods. | 03-28-2013 |
20130072009 | METHOD FOR PREPARING A SUBSTRATE BY IMPLANTATION AND IRRADIATION - A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach said detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues. | 03-21-2013 |
20130071997 | METHOD FOR REDUCING IRREGULARITIES AT THE SURFACE OF A LAYER TRANSFERRED FROM A SOURCE SUBSTRATE TO A GLASS-BASED SUPPORT SUBSTRATE - A method for reducing irregularities at the surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 μm and 600 μm. | 03-21-2013 |
20130058369 | SEMICONDUCTOR DEVICE HAVING AN InGaN LAYER - An InGaN-on-substrate structure that includes an InGaN layer and two mirror layers on opposing sides of and sandwiching the InGaN layer. The InGN layer includes an InGaN seed layer and an active InGaN layer grown on the InGaN seed layer. Such a structure is useful in a vertical optoelectronic device. | 03-07-2013 |
20130054154 | SYSTEM AND METHOD FOR ASSESSING INHOMOGENEOUS DEFORMATIONS IN MULTILAYER PLATES - A method and device for evaluating inhomogeneous deformations in a first wafer bonded by molecular adhesion to a second wafer. This evaluation method includes the steps of making at least one reading of a plurality of measurement points, the reading corresponding to a surface profile of the first wafer along a predefined direction and over a predefined length, computing a second derivative from the measurement points of the surface profile and evaluating a level of inhomogeneous deformations in the first wafer according to the second derivative. | 02-28-2013 |
20130052806 | DEPOSITION SYSTEMS HAVING ACCESS GATES AT DESIRABLE LOCATIONS, AND RELATED METHODS - Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber. The systems also include at least one access gate through which a workpiece substrate may be loaded into the reaction chamber and unloaded out from the reaction chamber. The at least one access gate is located remote from the gas injection device. Methods of depositing semiconductor material may be performed using such deposition systems. Methods of fabricating such deposition systems may include coupling an access gate to a reaction chamber at a location remote from a gas injection device. | 02-28-2013 |
20130052333 | DEPOSITION SYSTEMS HAVING REACTION CHAMBERS CONFIGURED FOR IN-SITU METROLOGY AND RELATED METHODS - Deposition systems include a reaction chamber, at least one thermal radiation emitter for heating matter within the reaction chamber, and at least one metrology device for detecting and/or measuring a characteristic of a workpiece substrate in situ within the reaction chamber. One or more chamber walls may be transparent to the thermal radiation and to radiation signals to be received by the metrology device, so as to allow the radiation to pass into and out from the reaction chamber, respectively. At least one volume of opaque material is located to shield a sensor of the metrology device from at least some of the thermal radiation. Methods of forming a deposition system include providing such a volume of opaque material at a location shielding the sensor from the thermal radiation. Methods of using a deposition system include shielding the sensor from at least some of the thermal radiation. | 02-28-2013 |
20130047918 | DEPOSITION SYSTEMS INCLUDING A PRECURSOR GAS FURNACE WITHIN A REACTION CHAMBER, AND RELATED METHODS - Deposition systems include a reaction chamber, a substrate support structure disposed within the chamber for supporting a substrate within the reaction chamber, and a gas input system for injecting one or more precursor gases into the reaction chamber. The gas input system includes at least one precursor gas furnace disposed at least partially within the reaction chamber. Methods of depositing materials include separately flowing a first precursor gas and a second precursor gas into a reaction chamber, flowing the first precursor gas through at least one precursor gas flow path extending through at least one precursor gas furnace disposed within the reaction chamber, and, after heating the first precursor gas within the at least one precursor gas furnace, mixing the first and second precursor gases within the reaction chamber over a substrate. | 02-28-2013 |
20130047917 | DIRECT LIQUID INJECTION FOR HALIDE VAPOR PHASE EPITAXY SYSTEMS AND METHODS - Methods of depositing compound semiconductor materials on one or more substrates include metering and controlling a flow rate of a precursor liquid from a precursor liquid source into a vaporizer. The precursor liquid may comprise at least one of GaCl | 02-28-2013 |
20130045584 | METHOD OF ELIMINATING FRAGMENTS OF MATERIAL PRESENT ON THE SURFACE OF A MULTILAYER STRUCTURE - The invention relates to a method of eliminating fragments of material present on the exposed surface of a first wafer bonded to a second wafer, the method including a step consisting of placing the first wafer in a liquid solution and propagating ultrasonic waves in the solution. The invention also relates to a process for manufacturing a multilayer structure comprising the following successive steps: bonding of a first wafer to a second wafer so as to form a multilayer structure; annealing of the structure; and thinning of the first wafer, including at least one step of chemically etching the first wafer. The process further includes, after the chemical etching step, the elimination of fragments of material present on the exposed surface of the thinned first wafer. | 02-21-2013 |
20130045583 | METHOD FOR MEASURING DEFECTS IN A SILICON SUBSTRATE - A method for measuring defects in a silicon substrate obtained by silicon ingot pulling, wherein the defects have a size of less than 20 nm. The method includes applying a first defect consolidation heat treatment to the substrate at a temperature of between 750 and 850° C. for a time of between 30 minutes and 1 hour to consolidate the defects; applying a second defect enlargement heat treatment to the substrate at a temperature of between 900 and 1000° C. for a time of between 1 hour and 10 hour to enlarge the defects to a size of greater than or equal to 20 nm, with the enlarged defects containing oxygen precipitates; measuring size and density of the enlarged defects in a surface layer of the substrate; and calculating the initial size of the defects on the basis of the measurements of the enlarged defects. | 02-21-2013 |
20130043600 | BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE - Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods. | 02-21-2013 |
20130032272 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICES - The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure. The bonding and loadlock modules remain at a pressure below atmospheric pressure while the wafer is transferred from the loadlock module into the bonding module. | 02-07-2013 |
20130029474 | METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER ONTO A SUPPORT SUBSTRATE - A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization. | 01-31-2013 |
20130026663 | METHOD FOR CURING DEFECTS IN A SEMICONDUCTOR LAYER - A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C. | 01-31-2013 |
20130026608 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE COMPRISING A FUNCTIONALIZED LAYER ON A SUPPORT SUBSTRATE - The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer. | 01-31-2013 |
20130015442 | BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME - Methods of forming semiconductor structures include transferring a portion ( | 01-17-2013 |
20130012024 | STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEM AND MANUFACTURING PROCESS - A process for making cavities in a multilayer structure by providing a multilayer structure that includes a surface layer, a planar support substrate and a buried layer between the layer and the support substrate, wherein the buried layer comprises areas of first and second materials with the first material having a higher etching rate than the second material; producing an opening in the surface layer that extends to the area(s) of the first material of the buried layer; and etching the first material to form at least one cavity in the buried layer. | 01-10-2013 |
20130005122 | METHOD FOR FINISHING A SUBSTRATE OF THE SEMICONDUCTOR-ON-INSULATOR TYPE - The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises:
| 01-03-2013 |
20120329243 | PROCESS FOR FABRICATING A SEMICONDUCTOR STRUCTURE EMPLOYING A TEMPORARY BOND - The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate. | 12-27-2012 |
20120322229 | METHOD FOR BONDING TWO SUBSTRATES - The invention relates to a method for bonding two substrates by applying an activation treatment to at least one of the substrates, and performing the contacting step of the two substrates under partial vacuum. Due to the combination of the two steps, it is possible to carry out the bonding and obtain high bonding energy with a reduced number of bonding voids. The invention is in particular applicable to a substrate of processed or at least partially processed devices. | 12-20-2012 |
20120319128 | SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 12-20-2012 |
20120319121 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE HAVING LOW ELECTRICAL LOSSES, AND CORRESPONDING STRUCTURE - A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes. | 12-20-2012 |
20120318330 | VOLTAGE MATCHED MULTIJUNCTION SOLAR CELL - A voltage matched multijunction solar cell having first and second solar cell stacks which are electrically connected parallel to each other. The first solar cell stack is optimized for absorption of incoming solar light in a first wavelength range and the second solar cell stack is optimized for absorption of incoming solar light in a second wavelength range, wherein the first and the second wavelength range do not or at most only partially overlap each other. | 12-20-2012 |
20120313237 | BONDED SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING SAME - Embodiments of the invention include methods and structures for fabricating a semiconductor structure, and, particularly for improving the planarity of a bonded semiconductor structure comprising a processed semiconductor structure and a semiconductor structure. | 12-13-2012 |
20120298710 | SUBSTRATE-SPLITTING DEVICE WITH DETECTION OF OBSTACLES - A device for splitting substrates that include a cleavage plane therein. The device includes a base and a control device for performing controlled displacement of certain substrates. The control device includes at least one pusher that is mobile relative to the base. The pusher is adapted to accommodate substrates in a reception space thereon, and is capable of displacing substrates arranged above it in a substrates support. A detector is provided to determine the absence or the presence of obstacles inside at least one region of the reception space of the pusher when the pusher is in a detection position. | 11-29-2012 |
20120292748 | METHODS AND STRUCTURES FOR FORMING INTEGRATED SEMICONDUCTOR STRUCTURES - The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure. | 11-22-2012 |
20120280367 | METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for manufacturing a semiconductor substrate by providing a seed support layer and a handle support layer, forming at least one semiconductor layer, in particular of a Group III/V-semiconductor material, over the seed support layer, wherein the at least one semiconductor layer is in a strained state, forming a bonding layer over the at least one semiconductor layer, forming a bonding layer over the handle support layer, and bonding the seed and handle substrates together to obtain a donor-handle compound, by direct bonding between the bonding layer of the seed substrate and the bonding layer of the handle substrate. At least one of the bonding layer of the seed substrate and the bonding layer of the handle substrate includes a silicon nitride. | 11-08-2012 |
20120280249 | METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods. | 11-08-2012 |
20120275254 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PRECHARGE TRANSISTORS - The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors. | 11-01-2012 |
20120275253 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PASS-GATE TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-up transistors. | 11-01-2012 |
20120275252 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT SWITCH TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source. | 11-01-2012 |
20120258554 | PROCESS FOR RECYCLING A SUBSTRATE - A process for recycling a support substrate of a material substantially transparent to at least a wavelength of electromagnetic radiation. The process includes providing an initial substrate; forming an intermediate layer on a bonding face of the support substrate having an initial roughness, with the intermediate layer being of a material substantially transparent to at least a wavelength of electromagnetic radiation; forming an electromagnetic radiation absorbing layer either on the bonding face of the initial substrate or on the intermediate layer; bonding the initial substrate to the support substrate via the electromagnetic radiation absorbing layer; and irradiating the electromagnetic radiation absorbing layer through the support substrate and the intermediate layer to induce separation of the support substrate from the initial substrate. | 10-11-2012 |
20120250444 | PSEUDO-INVERTER CIRCUIT ON SeOI - A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage. | 10-04-2012 |
20120244687 | METHOD OF MANUFACTURING A BASE SUBSTRATE FOR A SEMI-CONDUCTOR ON INSULATOR TYPE SUBSTRATE - A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure. | 09-27-2012 |
20120241918 | PROCESS FOR THE REALIZATION OF ISLANDS OF AT LEAST PARTIALLY RELAXED STRAINED MATERIAL - The present invention relates to the field of semiconductor manufacturing. More specifically, it relates to a method of forming islands of at least partially relaxed strained material on a target substrate including the steps of forming islands of the strained material over a side of a first substrate; bonding the first substrate, on the side including the islands of the strained material, to the target substrate; and after the step of bonding splitting the first substrate from the target substrate and at least partially relaxing the islands of the strained material by a first heat treatment. | 09-27-2012 |
20120241821 | HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS - A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10 | 09-27-2012 |
20120228689 | WAFER WITH INTRINSIC SEMICONDUCTOR LAYER - The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method. | 09-13-2012 |
20120228672 | METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE - The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET. | 09-13-2012 |
20120225539 | DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIALS, AND RELATED STRUCTURES - Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, the layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods. | 09-06-2012 |
20120223419 | METHOD FOR CONTROLLING THE DISTRIBUTION OF STRESSES IN A SEMICONDUCTOR-ON-INSULATOR TYPE STRUCTURE AND CORRESPONDING STRUCTURE - A method for controlling the distribution of the stresses in a structure of the semiconductor-on-insulator type during its manufacturing, which includes a thin layer of semiconducting material on a supporting substrate and an insulating layer present on each of the front and rear faces of the supporting substrate, with the insulating layer on the front face forming at least one portion of a thick buried insulator (BOX) layer. The method includes the adhesive bonding of the thin layer onto the supporting substrate. Prior to this adhesive bonding, the insulating layer on the rear face of the supporting substrate is covered with a distinct material that is capable of withstanding deoxidation. The covering material, in combination with this insulating layer on the rear face of the supporting substrate, at least partly compensates for the stress exerted by the buried insulator (BOX) on the supporting substrate. | 09-06-2012 |
20120214291 | RELAXATION OF STRAINED LAYERS - A method for relaxing a layer of a strained material. The method includes depositing a first low-viscosity layer on a first face of a strained material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained material layer; and applying a mechanical pressure to a second face of the strained material layer wherein the second face is opposite to the first face and with the mechanical pressure applied perpendicularly to the strained material layer during at least part of the heat treatment to relax the strained material. | 08-23-2012 |
20120199953 | SEMICONDUCTOR STRUCTURE WITH SMOOTHED SURFACE AND PROCESS FOR OBTAINING SUCH A STRUCTURE - The present invention relates to a process for smoothing the surface of a semiconductor wafer by fusion. The process includes defining a reference length which dimensions wafer surface roughness that is to be reduced or removed, and scanning the surface with a fusion beam while adjusting parameters of the fusion beam so as to fuse, during the scanning of the surface, a local surface zone of the wafer whose length is greater than or equal to the reference length, with the scanning continued to smooth the entire surface of the wafer by eliminating surface roughnesses of period lower than the reference length. The present invention also relates to a semiconductor wafer having a surface layer made of a semiconducting material that is smoothed by the process and that does not exhibit any roughness of period lower than the reference length. | 08-09-2012 |
20120164843 | TRANSFER OF HIGH TEMPERATURE WAFERS - This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency. | 06-28-2012 |
20120164778 | METHOD OF BONDING BY MOLECULAR BONDING - A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to the peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers. | 06-28-2012 |
20120132922 | COMPOSITE SUBSTRATE WITH CRYSTALLINE SEED LAYER AND CARRIER LAYER WITH A COINCIDENT CLEAVAGE PLANE - A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction. | 05-31-2012 |
20120118233 | SYSTEMS FOR FORMING SEMICONDUCTOR MATERIALS BY ATOMIC LAYER DEPOSITION - Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns. | 05-17-2012 |
20120112205 | SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING SEMICONDUCTOR MATERIAL ON A NON-GLASSY BONDING LAYER - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material. | 05-10-2012 |
20120100692 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES WITH STRAINED SEMICONDUCTOR MATERIAL - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material. | 04-26-2012 |
20120100691 | PROCESSES FOR FABRICATING HETEROSTRUCTURES - The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material. | 04-26-2012 |
20120098033 | HETEROSTRUCTURES COMPRISING CRYSTALLINE STRAIN RELAXATION LAYERS - The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure. | 04-26-2012 |
20120085400 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES USING QUANTUM DOT STRUCTURES AND RELATED STRUCTURES - Methods of fabricating photovoltaic devices include forming a plurality of subcells in a vertically stacked arrangement on the semiconductor material, each of the subcells being formed at a different temperature than an adjacent subcell such that the adjacent subcells have differing effective band-gaps. The methods of fabricating also include inverting the structure, attaching another substrate to the second semiconductor material, and removing the substrate. For example, each of the subcells may comprise a III-nitride material, and each subsequent subcell may include an indium content different than the adjacent subcell. Novel structures may be formed using such methods. | 04-12-2012 |