Taejin Info Tech Co., Ltd Patent applications |
Patent application number | Title | Published |
20140137135 | MULTI-CORE-BASED LOAD BALANCING DATA PROCESSING METHODS - Systems and methods for processing data are provided. A system can include a plurality of cores and a core manager. A load balancing unit can check and compare loads of the cores. An address mapping unit can perform a mapping process based on the loads of the cores, and the core manager can route data appropriately, thereby improving the overall performance of the system. | 05-15-2014 |
20140133257 | BACK-UP POWER MANAGEMENT FOR EFFICIENT BATTERY USAGE - Battery backup devices and methods of performing a backup operation using the same are provided. A battery backup device can include a partial battery power controller configured to shut off power to components to be backed up one by one as data backup is completed on each device. The battery backup devices and methods provided can efficiently utilize battery power such that power consumption and charging time can be reduced. | 05-15-2014 |
20140129788 | HIGH-PERFORMANCE LARGE SCALE SEMICONDUCTOR STORAGE MODULE WITH HYBRID TECHNOLOGY - An open architecture is provided for enabling at least two memory types for a single memory disk unit. The memory disk unit includes an interface and a DMA controller. The DMA controller controls the transfer of data to/from memory of at least two memory types of the memory disk unit through a hybrid memory control module. A corresponding memory controller (and in some cases, an ECC controller) is provided for each memory of the at least two memory types. The hybrid memory control architecture can control existing memory controllers by matching protocols for the particular memory controller. Address/memory commands and signal timing can be matched up to the appropriate controller by the hybrid memory control architecture. | 05-08-2014 |
20140129765 | METHOD TO IMPROVE DATA RELIABILITY IN DRAM SSD USING ASYNCHRONOUS LOGGING AND INCREMENTAL BACKUP - Data back-up and recovery methods for DRAM SSDs and other high performance disks are provided. During operation, write events to the DRAM SSD are asynchronously backed-up onto a back-up HDD storage disk from an in-memory buffer. Should a DRAM SSD failure occur, the system can continue to operate, albeit at a lower performance, using the back-up HDD storage disk. Should the main power fail, data remaining in the in-memory buffer is flushed to the back-up HDD storage disk and writing events that did not make it to the in-memory buffer due to insufficient space are incrementally backed-up from the DRAM SSD to the secondary storage. Once power returns from the main power, data from the back-up storage disk and the secondary storage are transferred to the DRAM SSD. | 05-08-2014 |
20140129751 | HYBRID INTERFACE TO IMPROVE SEMICONDUCTOR MEMORY BASED SSD PERFORMANCE - A system and hybrid interface for high-performance memory-based storage devices are disclosed. The hybrid interface includes a polling interface and interrupt interface that are selected by a consideration of latency and CPU usage for a particular request to the storage device. | 05-08-2014 |
20110179198 | STORAGE DEVICE OF SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE/SERIAL ADVANCED TECHNOLOGY ATTACHMENT TYPE - Provided is a storage device of a serial attached small computer system interface/serial advanced technology attachment (SAS/SATA) type, which provides data storage/reading services through an SAS/SATA interface. The SAS/SATA type storage device includes: a memory disk unit which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; an SAS/SATA host interface unit which interfaces between the memory disk unit and a host; and a controller unit which adjusts synchronization of a data signal transmitted/received between the SAS/SATA host interface unit and the memory disk unit to control a data transmission/reception speed between the SAS/SATA host interface unit and the memory disk unit. The storage device can support a low-speed data processing speed for the host and simultaneously support a high-speed data processing speed for the memory disk unit, so that there are advantages in that the performance of the memory disk can be fully utilized to enable high-speed data processing in an existing interface environment. | 07-21-2011 |