Entries |
Document | Title | Date |
20080203389 | Semiconductor apparatus having temperature sensing diode - A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate. | 08-28-2008 |
20080230779 | [100] Or [110] aligned, semiconductor-based, large-area, flexible, electronic devices - Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices. | 09-25-2008 |
20080315197 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a substrate of single crystal silicon; a first device formed in a first region of a surface of the substrate; a first interlayer insulating film formed on the substrate; a polycrystalline silicon layer formed in a second region on the first interlayer insulating film; a second device formed in the polycrystalline silicon layer; a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film covering the polycrystalline silicon layer; and a pad formed in a third region on the second interlayer insulating film. The second region includes at least part of a directly overlying zone of the first region. The third region includes at least part of a region which is the directly overlying zone of the first region and a directly overlying zone of the second region. | 12-25-2008 |
20090014719 | SEMICONDUCTOR DEVICE WITH LARGE BLOCKING VOLTAGE - A junction FET having a large gate noise margin is provided. The junction FET comprises an n | 01-15-2009 |
20090095956 | SINGLE-CRYSTAL SILICON SUBSTRATE, SOI SUBSTRATE, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained. | 04-16-2009 |
20090121224 | DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers. | 05-14-2009 |
20090127554 | Semiconductor structure having multilayer of polysilicon and display panel applied with the same - A semiconductor structure includes a substrate, a first polysilicon (polysilicon) region, a second polysilicon region, an insulating layer and a third polysilicon region. The first and second polysilicon regions are formed on the substrate and spaced apart by a gap. The insulating layer formed on the substrate covers the first and second polysilicon regions. The third polysilicon region is formed on the insulating layer and disposed above the gap. When the semiconductor structure is applied to a display panel, a grain boundary of the third polysilicon region in a displaying region and a channel of an active layer intersect at an angle, and the grain boundary of the third polysilicon region in a circuit driving region is substantially parallel to the channel of the active layer. | 05-21-2009 |
20090166622 | PLASMA PROCESSING APPARATUS AND SEMICONDUCTOR ELEMENT MANUFACTURED BY SUCH APPARATUS - When a flow rate of a diluent gas is larger than a flow rate of a reaction gas, a reaction gas introducing tube ( | 07-02-2009 |
20090166623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced. | 07-02-2009 |
20090166624 | CRYSTALLIZATION APPARATUS, CRYSTALLIZATION METHOD, PHASE MODULATION ELEMENT, DEVICE AND DISPLAY APPARATUS - A phase modulation element according to the present invention has a first area having a first phase value based on a phase modulation unit having a predetermined size and a second area having a second phase value based on the phase modulation unit having the predetermined size, and each phase distribution is defined by a change in area shares of the first area and the second area depending on each position. | 07-02-2009 |
20090173939 | Hybrid Wafers - A hybrid wafer comprises a single-crystal Si | 07-09-2009 |
20090179200 | Semiconductor device - A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a second electrode for injecting holes, and a light emission part electrically connected to the first electrode and the second electrode, where the light emission part includes amorphous or polycrystalline silicon consisting of a single layer or plural layers and where the dimension of the silicon in at least one direction is controlled to be several nanometers. | 07-16-2009 |
20090184317 | ARRAY OF MUTUALLY INSULATED GEIGER-MODE AVALANCHE PHOTODIODES, AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region. | 07-23-2009 |
20090200550 | METHOD FOR FORMING AN ELECTRONIC DEVICE ON A FLEXIBLE SUBSTRATE SUPPORTED BY A DETACHABLE CARRIER - A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to yield the resultant electronic device. | 08-13-2009 |
20090218566 | LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein. | 09-03-2009 |
20090230393 | DIODE - In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n− type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n− type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed. Moreover, a natural oxide film formed between the n− type semiconductor layer and the p type polysilicon layer in formation of the p type polysilicon layer can also reduce the amount of holes injected into the n− type semiconductor layer. Thus, a time to extract the holes in reverse voltage application, that is, a reverse recovery time can be shortened without using a life time killer. | 09-17-2009 |
20090278125 | CRYSTALLINE SEMICONDUCTOR FILMS, GROWTH OF SUCH FILMS AND DEVICES INCLUDING SUCH FILMS - The present invention describes an approach to grow highly crystalline semiconductor films, multilayers of semiconductor thin films on foreign substrate such as glass, quartz. Specifically, The film were grown by first forming crystalline seeds, and transferring the seeds onto the substrate, and growing continuous semiconductor film through epitaxial growth on the seeds. | 11-12-2009 |
20100006840 | MEMS/NEMS STRUCTURE COMPRISING A PARTIALLY MONOCRYSTALLINE ANCHOR AND METHOD FOR MANUFACTURING SAME - The invention relates to a method for producing a MEMS/NEMS structure from a substrate made in a monocrystalline semiconductor material, the structure comprising a flexible mechanical element connected to the substrate by at least one anchoring zone, the method comprising the following steps:
| 01-14-2010 |
20100025683 | REDUCTION OF EDGE EFFECTS FROM ASPECT RATION TRAPPING - A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures. | 02-04-2010 |
20100025684 | METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LAYER, GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer ( | 02-04-2010 |
20100044704 | VERTICAL THERMOELECTRIC STRUCTURES - A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity. | 02-25-2010 |
20100051945 | SILICON WAFER AND METHOD FOR PRODUCING THE SAME - A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×10 | 03-04-2010 |
20100051946 | POLY-EMITTER TYPE BIPOLAR JUNCTION TRANSISTOR, BIPOLAR CMOS DMOS DEVICE, AND MANUFACTURING METHODS OF POLY-EMITTER TYPE BIPOLAR JUNCTION TRANSISTOR AND BIPOLAR CMOS DMOS DEVICE - A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base area formed at a part of an upper portion of the epitaxial layer, and a poly-emitter area formed on a surface of the semiconductor substrate in the base area and including a polysilicon material. A BCD device includes a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor. | 03-04-2010 |
20100059748 | METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT, AND ELEMENT SUBSTRATE - Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved. | 03-11-2010 |
20100127259 | SEMICONDUCTOR DEVICE - A semiconductor device has a MOS transistor that has a gate connected to a first terminal, a source connected to a second terminal and a drain connected to a third terminal, a first polysilicon diode that has an anode connected to the first terminal, a first single-crystalline silicon diode that is connected to a cathode of the first polysilicon diode at a cathode thereof and to the second terminal at an anode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the first polysilicon diode, a second polysilicon diode that has a cathode connected to the first terminal and a second single-crystalline silicon diode that is connected to an anode of the second polysilicon diode at an anode thereof and to the third terminal at a cathode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the second polysilicon. | 05-27-2010 |
20100127260 | Antireflection film, antireflection film manufacturing method, and semiconductor device using the antireflection film - To improve a transmission rate of an antireflection film, the antireflection film includes: a first silicon oxide film (2), which is formed on a silicon substrate ( | 05-27-2010 |
20100140618 | Sensor and method for the manufacture thereof - A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm, and the diode is implemented in a polycrystalline semiconductor layer. The diode is implemented by way of two low-doped diode regions or at least one low-doped diode region. At least parts of the supply leads are implemented by way of highly doped supply lead regions of the shared polycrystalline semiconductor layer. | 06-10-2010 |
20100155728 | EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME - An epitaxial wafer and method for fabricating the same can prevent a bowing phenomenon of the epitaxial wafer. The epitaxial wafer includes a substrate configured to be doped in a first doping concentration; an epitaxial layer configured to be formed over a first side of the substrate and doped in a second doping concentration lower than the first doping concentration; and a back seal layer configured to be formed over a second side of the substrate and include a layer having a tensile stress, wherein the second side is opposite to the first side, of the substrate. | 06-24-2010 |
20100163872 | Bipolar Junction Transistor and Method of Manufacturing the Same - A bipolar junction transistor and a method of manufacturing a bipolar junction transistor are disclosed. An exemplary bipolar junction transistor includes a second conductivity type base region in a first conductivity type substrate, step-shaped recesses in the base region, a polysilicon layer doped with a first conductivity type impurity in the step-shaped recesses, and a step-shaped emitter region between the polysilicon layer and the base region. | 07-01-2010 |
20100176397 | METHOD FOR PRODUCING PARTIAL SOI STRUCTURES COMPRISING ZONES CONNECTING A SUPERFICIAL LAYER AND A SUBSTRATE - The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises:
| 07-15-2010 |
20100176398 | ELECTRONIC DEVICE IMPROVED IN HEAT RADIATION PERFORMANCE FOR HEAT GENERATED FROM ACTIVE ELEMENT - An electronic device of the present invention includes a first substrate provided with a thin film active element, having a thickness of 200 μm or lower, and a second substrate formed with a high thermal conductivity portion. The second substrate is applied to one surface of the two surfaces of the first substrate, i.e., the surface being the side other than the side that formed with the thin film active element. The thin film active element has a maximum power consumption of 0.01 to 1 mW. The high thermal conductivity portion is a region that corresponds to the position of the thin film active element and whose thermal conductivity falls within the range from 0.1 to 4 W/cm·deg. | 07-15-2010 |
20100200854 | Method for reclaiming a surface of a substrate - A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary. | 08-12-2010 |
20100230673 | Semiconductor Fuse Structure and a Method of Manufacturing a Semiconductor Fuse Structure - The invention relates to a semiconductor fuse structure comprising a substrate ( | 09-16-2010 |
20100237346 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A rectifier is formed by forming a first electrode layer, a semiconductor layer and a second electrode layer. A third electrode layer is formed between the first electrode layer and the semiconductor layer, or between the second electrode layer and the semiconductor layer. | 09-23-2010 |
20100252831 | SQUARE PILLAR-SHAPED SWITCHING ELEMENT FOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A switching element for a memory device includes a base layer including a plurality of line-type trenches. First insulation patterns are formed on the base layer excluding the trenches. First diode portions are formed on the bottoms of the trenches in the form of a thin film. Second insulation patterns are formed on the first diode portions and are spaced apart from each other to form holes in the trenches having the first diode portions provided therein. Square pillar-shaped second diode portions are formed in the holes over the first diode portions. | 10-07-2010 |
20100258799 | Bipolar transistor and method of manufacturing the same - A bipolar transistor at least includes a semiconductor substrate including an N | 10-14-2010 |
20100283053 | NONVOLATILE MEMORY ARRAY COMPRISING SILICON-BASED DIODES FABRICATED AT LOW TEMPERATURE - In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described. | 11-11-2010 |
20100301335 | High Voltage Insulated Gate Bipolar Transistors with Minority Carrier Diverter - High power insulated gate bipolar junction transistors are provided that include a wide band gap semiconductor bipolar junction transistor (“BJT”) and a wide band gap semiconductor MOSFET that is configured to provide a current to the base of the BJT. These devices further include a minority carrier diversion semiconductor layer on the base of the BJT and coupled to the emitter of the BJT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT. | 12-02-2010 |
20100308330 | Methods of Manufacturing Resistors and Structures Thereof - Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transistor material stack, forming a gate of a transistor in a first region of the workpiece and leaving a portion of the transistor material stack in a second region of the workpiece. A top portion of the transistor material stack is removed in the second region, and a top portion of the workpiece is removed in the first region proximate the gate of the transistor, forming recessed regions in the workpiece in the first region. A semiconductive material is formed in the recessed regions of the workpiece in the first region and over a portion of the transistor material stack in the second region, forming a resistor in the second region. | 12-09-2010 |
20100320462 | N-TYPE CONDUCTIVE ALUMINUM NITRIDE SEMICONDUCTOR CRYSTAL AND MANUFACTURING METHOD THEREOF - This invention provides a selfsupporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing the vertical conductive type AlN semiconductor device. | 12-23-2010 |
20110006304 | SEMICONDUCTOR DEVICE WITH ALTERNATELY ARRANGED P-TYPE AND N-TYPE THIN SEMICONDUCTOR LAYERS AND METHOD FOR MANUFACTURING THE SAME - The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased. | 01-13-2011 |
20110012109 | METHOD OF FORMING A GROUP III-NITRIDE CRYSTALLINE FILM ON A PATTERNED SUBSTRATE BY HYDRIDE VAPOR PHASE EPITAXY (HVPE) - A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation. | 01-20-2011 |
20110108838 | ELECTRO-MECHANICAL TRANSDUCER, AN ELECTRO-MECHANICAL CONVERTER, AND MANUFACTURING METHODS OF THE SAME - An electro-mechanical transducer contains a vibrating electrode ( | 05-12-2011 |
20110127529 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure. | 06-02-2011 |
20110168996 | Polycrystalline heterostructure infrared detector - A midwave infrared lead salt photodetector manufactured by a process comprising the step of employing molecular beam epitaxy (MBE) to grow a heterostructure photoconductive detector with a wide-gap surface layer that creates a surface channel for minority carriers. | 07-14-2011 |
20110186840 | DIAMOND SOI WITH THIN SILICON NITRIDE LAYER - A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon. | 08-04-2011 |
20110198590 | SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT - In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article. | 08-18-2011 |
20110215320 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In a first aspect, a method of forming a memory cell is provided that includes: (a) forming a layer of dielectric material above a substrate; (b) forming an opening in the dielectric layer; (c) depositing a solution that includes a carbon-based switching material on the substrate; (d) rotating the substrate to cause the solution to flow into the opening and to form a carbon-based switching material layer within the opening; and (e) forming a memory element using the carbon-based switching material layer. Numerous other aspects are provided. | 09-08-2011 |
20110215321 | POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC - A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate. | 09-08-2011 |
20110220890 | Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 09-15-2011 |
20110240997 | Epitaxial Structures, Methods of Forming the Same, and Devices Including the Same - Epitaxial structures, methods of making epitaxial structures, and devices incorporating such epitaxial structures are disclosed. The methods and the structures employ a liquid-phase Group IVA semiconductor element precursor ink (e.g., including a cyclo- and/or polysilane) and have a relatively good film quality (e.g., texture, density and/or purity). The Group IVA semiconductor element precursor ink forms an epitaxial film or feature when deposited on a (poly)crystalline substrate surface and heated sufficiently for the Group IVA semiconductor precursor film or feature to adopt the (poly)crystalline structure of the substrate surface. Devices incorporating a selective emitter that includes the present epitaxial structure may exhibit improved power conversion efficiency relative to a device having a selective emitter made without such a structure due to the improved film quality and/or the perfect interface formed in regions between the epitaxial film and contacts formed on the film. | 10-06-2011 |
20110254002 | DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data interconnection pattern formed on the semiconductor layer pattern, a protection layer formed on the substrate and the data interconnection pattern, contact holes formed on the substrate to expose at least a portion of an upper surface of the semiconductor pattern and at least a portion of an upper surface of the data interconnection pattern, and contact electrodes formed in the contact holes to be in contact with the exposed upper surfaces of the data interconnection pattern and the semiconductor layer pattern. | 10-20-2011 |
20120032168 | PHOTONIC DEVICE AND METHOD OF MAKING THE SAME - A photonic device ( | 02-09-2012 |
20120037903 | Method For Manufacturing Semiconductor Device, Semiconductor Device And Electronic Appliance - A non-single-crystal semiconductor layer is formed over a substrate, and then a single crystal semiconductor layer is formed over part of the non-single-crystal semiconductor layer. Thus, a semiconductor element of a region which requires a large area (e.g. a pixel region in a display device) can be formed using the non-single-crystal semiconductor layer, and a semiconductor element of a region which requires high speed operation (e.g. a driver circuit region in a display device) can be formed using the single crystal semiconductor layer. | 02-16-2012 |
20120043540 | Semiconductor device, method for manufacturing same, and display device - The present invention provides a semiconductor device capable of suppressing a contact failure due to an increase in contact resistance, a production method of the semiconductor device, and a display device. The present invention provides a semiconductor device which includes a thin-film diode including a crystalline semiconductor layer which includes a cathode region and an anode region, a cathode electrode connected to the cathode region, and an anode electrode connected to the anode region, the thin-film diode, the cathode electrode, and the anode electrode being disposed on a substrate, and which is featured in that the crystalline semiconductor layer includes a first low-impurity-concentration region having an impurity concentration lower than the impurity concentration of the cathode region, in that the first low-impurity-concentration region is arranged adjacent to the cathode region, and in that the cathode electrode is in contact with an area of the cathode region, the area being within 3 μm from the boundary at which the cathode region is in contact with the first low-impurity-concentration region. | 02-23-2012 |
20120068178 | TRENCH POLYSILICON DIODE - Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench. | 03-22-2012 |
20120074403 | METHOD FOR GROWING GaN CRYSTAL AND GaN CRYSTAL SUBSTRATE - The present invention is to provide GaN crystal growing method for growing a GaN crystal with few stacking faults on a GaN seed crystal substrate having a main surface inclined at an angle of 20° to 90° from the (0001) plane, and also to provide a GaN crystal substrate with few stacking faults. A method for growing a GaN crystal includes the steps of preparing a GaN seed crystal substrate | 03-29-2012 |
20120091456 | CONFORMAL ELECTROMAGNETIC SENSOR (FOR DETECTION OF NON-DESTRUCTIVE IMAGING AND INVESTIGATION) - A conformal electro-magnetic (EM) detector and a method of applying such a detector are provided herein as well as variations thereof Variations include, but are not limited to, single-element, area detectors; an array of multiple active elements. | 04-19-2012 |
20120097945 | POLYCRYSTALLINE METAL-BASED LED HEAT DISSIPATING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A polycrystalline metal-based LED heat dissipating structure includes a composite substrate, an insulated heat conducting layer, printed circuit layer, electric and heat conducting layer, and a polycrystalline metal-based LED. The composite substrate and the printed circuit layer are linked by the insulated heat conducting layer. The printed circuit layer and the polycrystalline metal-based LED are linked by the electric and heat conducting layer. Through the above structure, the life time of the polycrystalline metal-based LED will be prolonged and the light decadency will be prevented. | 04-26-2012 |
20120104390 | Germanium-Containing Release Layer For Transfer of a Silicon Layer to a Substrate - A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed. | 05-03-2012 |
20120132912 | SEMICONDUCTOR DEVICE - A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n | 05-31-2012 |
20120138928 | Method of Manufacturing Low Resistivity Contacts on n-Type Germanium - Disclosed are methods for manufacturing semiconductor devices and the devices thus obtained. In one embodiment, the method comprises obtaining a semiconductor substrate comprising a germanium region doped with n-type dopants at a first doping level and forming an interfacial silicon layer overlying the germanium region, where the interfacial silicon layer is doped with n-type dopants at a second doping level and has a thickness higher than a critical thickness of silicon on germanium, such that the interfacial layer is at least partially relaxed. The method further includes forming over the interfacial silicon layer a layer of material having an electrical resistivity smaller than 1×10 | 06-07-2012 |
20120146022 | DISPLAY PANEL, DISPLAY DEVICE, AND METHOD MANUFACTURING SAME - The invention provides a display panel and display device enabling easy connection to an external connection component depending on the type of a mounted component, and provides a display device manufacturing method allowing a simple manufacturing process. The display panel of the present invention is a display panel in which a thin film transistor array substrate and an opposed substrate are disposed opposing each other. The thin film transistor array substrate has a first routing wiring that is routed at the outer edge of the substrate, a common transfer section that is formed at a position overlapping with the first routing wiring when the substrate surface is viewed from a normal direction, and a first terminal region, having a plurality of terminals formed thereon including a terminal that is joined to the first routing wiring, at an end portion of the substrate. The opposed substrate has a second routing wiring, and a second terminal region, having a plurality of terminals formed thereon including a terminal that is joined to the second routing wiring, at an end portion of the substrate. The first routing wiring and the second routing wiring conduct with each other via the common transfer section. | 06-14-2012 |
20120175613 | POLYCRYSTALLINE SILICON MASS AND PROCESS FOR PRODUCING POLYCRYSTALLINE SILICON MASS - The present invention provides a clean and high-purity polycrystalline silicon mass having a small content of chromium, iron, nickel, copper, and cobalt in total, which are heavy metal impurities that reduce the quality of single-crystal silicon. In the vicinity of an electrode side end of a polycrystalline silicon rod obtained by the Siemens method, the total of the chromium, iron, nickel, copper, and cobalt concentrations is high. Accordingly, before a crushing step of a polycrystalline silicon rod | 07-12-2012 |
20120199831 | LIQUID CRYSTAL DISPLAY DEVICE - To provide a liquid crystal display device having high visibility and high image quality by relieving color phase irregularity. A light-shielding layer is selectively provided so as to overlap with a contact hole for electrical connection to a source region or a drain region of a thin film transistor. Alternatively, by providing an opening portion of a colored layer (color filter) with an opening so as to overlap with a contact hole, uneven alignment of liquid crystal molecules does not influence display, and a liquid crystal display having high image quality can be provided. | 08-09-2012 |
20120205653 | PRESSURE SENSOR AND METHOD FOR MANUFACTURING PRESSURE SENSOR - A pressure sensor | 08-16-2012 |
20120211747 | PN JUNCTIONS AND METHODS - A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area. | 08-23-2012 |
20120241740 | METHOD OF FORMING A PHOTOSENSITIVE PATTERN, METHOD OF MANUFACTURING A DISPLAY SUBSTRATE, AND DISPLAY SUBSTRATE - A method of forming a photosensitive pattern on a substrate with a photosensitive layer disposed thereon may include moving at least one of the substrate and a set of micro-mirrors in a first direction, the set of micro-mirrors being disposed above the substrate and being arranged as an array, the array having a first edge extending in a second direction, the second direction being at an acute angle with respect to the first direction. The method may also include selectively turning on one or more micro-mirrors of the set of micro-mirrors according to a position of the set of micro-mirrors relative to the photosensitive layer, thereby irradiating one or more spot beams on the photosensitive layer. The photosensitive layer exposed by the spot beams is developed to form a photosensitive pattern having an edge portion extending in a third direction crossing the first and second directions. | 09-27-2012 |
20120248442 | METHOD OF FORMING A FINE PATTERN, DISPLAY SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME USING THE METHOD OF FORMING A FINE PATTERN - A method is provided for forming a fine pattern. In the method, a first fine pattern and a first metal pattern are formed by respectively patterning a first fine pattern layer on a base substrate and a first metal layer on the first fine pattern layer. A second fine pattern layer and a second metal layer are sequentially formed over the first fine pattern and the first metal pattern. The second metal layer is patterned, so that a second metal pattern between adjacent portions of the first fine pattern. The second fine pattern layer is patterned using the second metal pattern as a mask, so that a second fine pattern is formed between adjacent portions of the first fine pattern. | 10-04-2012 |
20120267627 | POLYCRYSTALLINE TEXTURING COMPOSITION AND METHOD - An aqueous acidic composition which includes alkaline compounds, fluoride ions and oxidizing agents is provided for texturing polycrystalline semiconductors. Methods for texturing are also disclosed. The textured polycrystalline semiconductors have reduced reflectance of light incidence. | 10-25-2012 |
20120305918 | PEROVSKITE SEMICONDUCTOR THIN FILM AND METHOD OF MAKING THEREOF - Perovskite semiconductor thin films and the method of making Perovskite semiconductor thin films are disclosed. Perovskite semiconductor thin films were deposited on inexpensive substrates such as glass and ceramics. CsSnI | 12-06-2012 |
20120313095 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT EMPLOYING POLYSILICON DIODE - An electrostatic discharge (ESD) protection circuit includes a polysilicon diode, a switch element, and a load element. The poly silicon diode has a first terminal and a second terminal. The switch element has a control terminal coupled to the first terminal of the polysilicon diode, a first terminal coupled to the second terminal of the polysilicon diode, and a second terminal. The load element is coupled to the control terminal of the switch element and the second terminal of the switch element. | 12-13-2012 |
20120326148 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed. | 12-27-2012 |
20130001553 | SEMICONDUCTOR DEVICES HAVING REDUCED SUBSTRATE DAMAGE AND ASSOCIATED METHODS - Optoelectronic devices, materials, and associated methods having increased operating performance are provided. In one aspect, for example, an optoelectronic device can include a semiconductor material, a first doped region in the semiconductor material, a second doped region in the semiconductor material forming a junction with the first doped region, and a laser processed region associated with the junction. The laser processed region is positioned to interact with electromagnetic radiation. Additionally, at least a portion of a region of laser damage from the laser processed region has been removed such that the optoelectronic device has an open circuit voltage of from about 500 mV to about 800 mV. | 01-03-2013 |
20130015441 | IC CARD AND BOOKING-ACCOUNT SYSTEM USING THE IC CARD - It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm. | 01-17-2013 |
20130026468 | RADIATION DETECTOR AND METHOD OF MANUFACTURING THE SAME - A graphite substrate is processed to have surface unevenness in a range of 1 μm to 8 μm. Thereby, a semiconductor film to be laminated on the graphite substrate has a stable film quality, and thus adhesion of the graphite substrate and the semiconductor layer can be enhanced. When an electron blocking layer is interposed between the graphite substrate and the semiconductor layer, the electron blocking layer is thin and thus the surface unevenness of the graphite substrate is transferred onto the electron blocking layer. Consequently, the electron blocking layer also has surface unevenness approximately in such range. Thus, almost the same effect as a configuration in which the semiconductor layer is directly connected to the graphite substrate can be produced. | 01-31-2013 |
20130026469 | SILICON WAFERS AND INGOTS WITH REDUCED OXYGEN CONTENT AND METHODS FOR PRODUCING THEM - Silicon nitride coated crucibles for holding melted semiconductor material and for use in preparing multicrystalline silicon ingots by a directional solidification process; methods for coating crucibles; methods for preparing silicon ingots and wafers; compositions for coating crucibles and silicon ingots and wafers with a low oxygen content. | 01-31-2013 |
20130032801 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME - The electronic device includes a substrate, a first electrode formed over a surface of the substrate, a second electrode located on an opposite side of the first electrode from the substrate so as to face the first electrode, and a functional layer interposed between the first electrode and second electrode and formed by means of anodizing a first polycrystalline semiconductor layer in an electrolysis solution so as to contain a plurality of semiconductor nanocrystals. The electronic device further includes a second polycrystalline semiconductor layer interposed between the first electrode and the functional layer so as to be in close contact with the functional layer. The second polycrystalline semiconductor layer has an anodic oxidization rate in the electrolysis solution lower than that of the first polycrystalline semiconductor layer so as to function as a stop layer for exclusively anodizing the first polycrystalline semiconductor layer. | 02-07-2013 |
20130037804 | DISPLAY DEVICE - A display device includes: a base film including plastic; an active layer on the base film, the active layer including a polysilicon layer formed by crystallizing an amorphous silicon layer using a laser; a barrier layer between the active layer and the base film; and a laser absorption layer between the barrier layer and the active layer. | 02-14-2013 |
20130037805 | VERTICAL SEMICONDUCTOR DEVICE - A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region. When the vertical semiconductor device is viewed in a plane, a region in the diffusion layer that has the impurity surface density higher than that satisfying the RESURF condition has a greater mean gradient of the impurity surface density than a region in the diffusion layer that has the impurity surface density lower than that satisfying the RESURF condition. | 02-14-2013 |
20130069064 | SEMICONDUCTOR DEVICE - A semiconductor device has a transistor in which a resistance is inserted between a gate electrode and a source electrode, and a diode inserted between the gate electrode and the source electrode in series in relation to the resistance. | 03-21-2013 |
20130075728 | ARRAY SUBSTRATE AND DISPLAY APPARATUS USING THE SAME - An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain. | 03-28-2013 |
20130082261 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode. | 04-04-2013 |
20130105795 | WAVEGUIDE-INTEGRATED GRAPHENE PHOTODETECTORS | 05-02-2013 |
20130119383 | SEMICONDUCTOR DEVICE AND ELECTRONIC UNIT - Thin-film transistors and techniques for forming thin-film transistors (TFT). In some embodiments, there is provided a method of forming a TFT, comprising forming a body region of the TFT comprising an organic semiconducting material, and forming a protective layer comprising an organic insulating material. Forming the protective layer comprises contacting the body region of the TFT with a solution comprising the organic insulating material. The organic insulating material is a material that phase separates with the organic semiconducting material when the solution contacts the organic semiconducting material. In other embodiments, there is provided an apparatus comprising a TFT. The TFT comprises a body region comprising an organic semiconducting material and a protective layer contacting the body region and comprising an organic insulating material that, when a solution comprising the organic insulating material contacts the organic semiconducting material, causes the organic insulating material to phase separate with the organic semiconducting material. | 05-16-2013 |
20130119384 | PARASITIC LATERAL PNP TRANSISTOR AND MANUFACTURING METHOD THEREOF - A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed. | 05-16-2013 |
20130140566 | BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE - Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base. | 06-06-2013 |
20130153901 | BSI Image Sensor Chips and Methods for Forming the Same - A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer. | 06-20-2013 |
20130161618 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure. | 06-27-2013 |
20130168676 | Super-Junction Structure of Semiconductor Device and Method of Forming the Same - A super-junction of a semiconductor device is formed by forming a polysilicon layer on a semiconductor substrate; patterning the polysilicon layer to form pillars for a super-junction structure; and growing an epitaxial layer between the pillars to form a continuous PN junction structure of the super-junction, which forms the super-junction structure more accurately. It is therefore possible to simplify the process for forming the super-junction without using a repetitive ion implantation process a trench process, thereby increasing productivity and device reliability. | 07-04-2013 |
20130200372 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention provides a structure of the TFT in which a current-voltage characteristic can be improved. The present invention refers to a thin film transistor comprising a lamination layer wherein a first conductive film, a first insulating film and a second conductive film are sequentially laminated, a semiconductor film formed so as to be in contact with the side surface of the lamination layer, and a third conductive film covering the semiconductor film through a second insulating film. The first conductive film and the second conductive film are a source electrode and a drain electrode, and a region which is in contact with the first insulating film and the third conductive film is a channel forming region in semiconductor film, and the third conductive film is a gate electrode. | 08-08-2013 |
20130207109 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a substrate upon which the semiconductor device is to be disposed, heating the substrate to a first temperature that exceeds at least one of a softening point or glass transition temperature of the substrate, and depositing a polysilicon layer onto the substrate. A semiconductor device includes a substrate having at least one of a softening point, T | 08-15-2013 |
20130228779 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes out a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose out the fourth cavity. | 09-05-2013 |
20130240885 | SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate including a substrate body divided into device regions and a peripheral region generally outside the device regions, and having one surface generally facing away from an other surface, and trenches which are defined generally in the device regions substantially on the one surface; and an active layer formed substantially in the trenches and made of polysilicon; semiconductor devices formed substantially over the active layer; and through electrodes substantially passing through the peripheral region of the substrate body. | 09-19-2013 |
20130277675 | SOI WAFER, MANUFACTURING METHOD THEREFOR, AND MEMS DEVICE - In order to obtain a SOI wafer having an excellent ability of gettering metal impurities, an efficient method of manufacturing a SOI wafer, and a highly reliable MEMS device using such a SOI wafer, provided is a SOI wafer including: a support wafer ( | 10-24-2013 |
20130285058 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present invention discloses a thin-film transistor (TFT) array substrate and a manufacturing method thereof. Depositing a transparent conductive layer and a first metal layer in turn on a substrate patterned by a first multi-tone mask (MTM) to form a gate, a common electrode and a reflecting layer; depositing a gate insulation layer and a semiconductor layer patterned by a second MTM to remain the semiconductor layer on the gate; and depositing a second metal layer patterned by a third MTM to form a source and a drain. | 10-31-2013 |
20130285059 | MICROMACHINE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced. | 10-31-2013 |
20130320342 | ULTRA-LARGE GRAIN POLYCRYSTALLINE SEMICONDUCTORS THROUGH TOP-DOWN ALUMINUM INDUCED CRYSTALLIZATION (TAIC) - A seed layer structure is annealed. The seed layer structure comprises a crystallization catalyst material on a seed semiconductor over a substrate. The seed semiconductor comprises an amorphous portion. Annealing of the seed layer structure converts the amorphous portion into a crystalline portion. The crystalline portion is connected to the substrate by subsurface crystal legs. The crystallization catalyst material formed underneath the crystalline portion by annealing is removed from the underneath of the crystalline portion. | 12-05-2013 |
20130328047 | STRUCTURE FOR PICKING UP A COLLECTOR AND METHOD OF MANUFACTURING THE SAME - A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions. | 12-12-2013 |
20130341621 | Electrical Device and Method for Manufacturing Same - An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other. | 12-26-2013 |
20130341622 | Polycrystalline Silicon Wafer - Provided is a polycrystalline silicon wafer produced by a melting and unidirectional solidification method, where the polycrystalline silicon wafer has a diameter of 450 mm or more, a thickness of 900 μm or more, and an average crystal grain size of 5 to 50 mm, and is made up of one piece. The present invention provides a large-sized polycrystalline silicon wafer having a wafer size of 450 mm or more, of which: mechanical properties are similar to those of monocrystalline silicon wafers; the crystal size is large; the surface roughness is low; the surface has a high cleanliness; the polished surface has less unevenness by having a definite crystal orientation; and the sag value is similar to that of monocrystalline silicon wafers. | 12-26-2013 |
20140001473 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140027773 | Semiconductor Device Including a Diode and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor cell array in the semiconductor body of a first conductivity type. The semiconductor device further includes a first trench in the transistor cell array between transistor cells. The first trench extends into the semiconductor body from a first side and includes a pn junction diode electrically coupled to the semiconductor body at a sidewall. | 01-30-2014 |
20140034948 | LED epitaxial Structure - An LED epitaxial structure includes the first layer thin film and the second layer thin film. The first layer thin film and the second layer thin film are polycrystalline aluminum nitride and single crystal aluminum nitride respectively, which have good thermal conductivity, insulation, mechanical intensity, and chemistry stability. Based on the substrate mentioned above, growing a single crystal gallium nitride on the second layer thin film as the third layer thin film allows the single crystal aluminum nitride and gallium nitride to have good lattice and thermal expansion match, resulting in the promotion of light emitting and thermal conduction efficiency. | 02-06-2014 |
20140048804 | FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL - A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate. | 02-20-2014 |
20140054589 | BISMUTH-DOPED SEMI-INSULATING GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD - The present invention discloses a semi-insulating wafer of Ga | 02-27-2014 |
20140061645 | Thin Film Transistor Array Substrate, Manufacturing Method Thereof, And Display Device - A thin film transistor (TFT) array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method comprises: forming a first passivation layer ( | 03-06-2014 |
20140061646 | Arrray Substrate And Display Device - Embodiments of the invention provide an array substrate and a display device. The array substrate comprises a common electrode and a pixel electrode that are formed on a base substrate. The common electrode comprises a first common electrode and a second common electrode, the first common electrode is provided below the pixel electrode and separated from the pixel electrode by an insulating layer, the second common electrode is provided in the same layer as the pixel electrode. The pixel electrode comprises a plurality of strip electrodes, the second common electrode also comprises a plurality of strip electrodes, and the strip electrodes of the pixel electrode and the strip electrodes of the second common electrode are alternately arranged. | 03-06-2014 |
20140084290 | MANUFACTURING METHOD FOR A SEMICONDUCTOR ON INSULATOR TYPE SUBSTRATE FOR RADIOFREQUENCY APPLICATIONS - The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radiofrequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate ( | 03-27-2014 |
20140091304 | LASER POWER AND ENERGY SENSOR UTILIZING ANISOTROPIC THERMOELECTRIC MATERIAL - A laser-radiation sensor includes a copper substrate on which is grown an oriented polycrystalline buffer layer surmounted by an oriented polycrystalline sensor-element of an anisotropic transverse thermoelectric material. An absorber layer, thermally connected to the sensor-element, is heated by laser-radiation to be measured and communicates the heat to the sensor-element, causing a thermal gradient across the sensor-element. Spaced-apart electrodes in electrical contact with the sensor-element sense a voltage corresponding to the thermal gradient as a measure of the incident laser-radiation power. | 04-03-2014 |
20140091305 | Polysilicon Thin Film And Manufacturing Method Thereof, Array Substrate And Display Device - A polysilicon thin film and a manufacturing method thereof, an array substrate and a display device are disclosed. The manufacturing method of the polysilicon thin film comprises the following steps: forming a graphene layer and an amorphous silicon layer which are adjacent; forming polysilicon by way of crystallizing amorphous silicon so as to obtain the polysilicon thin film. The polysilicon thin film manufactured by the method possesses good characteristics. | 04-03-2014 |
20140097432 | SHEET OF SEMICONDUCTING MATERIAL, LAMINATE, AND SYSTEM AND METHODS FOR FORMING SAME - Methods of forming a laminate comprising a sheet of semiconductor material utilize a system. The system comprises a fibrous sheet, a guide member for guiding the fibrous sheet, and a melt of a semiconductor material. The sheet of semiconductor material and a laminate comprising the fibrous sheet and the sheet of semiconductor material are also included. | 04-10-2014 |
20140117356 | SEMICONDUCTOR STRUCTURE FOR IMPROVED OXIDE FILL IN - A semiconductor device includes a substrate, a semiconductor layer, and a material layer. The semiconductor layer is formed over the substrate. The material layer is formed over the semiconductor layer. The semiconductor layer and the material layer have a tapered profile in a vertical direction extending from the substrate. | 05-01-2014 |
20140117357 | LIGHT EMITTING DEVICE PACKAGE - Embodiments provide a light emitting device package including a package body having a top-opened cavity disposed in at least a portion thereof, a first electrode layer and a second electrode layer electrically isolated from the package body with an insulating layer interposed therebetween, the first electrode layer and the second electrode layer being electrically isolated from each other at a bottom surface of the cavity, a light emitting device placed on the bottom surface of the cavity configured to emit light through the open region of the cavity, and a sensor placed on at least a portion of the package body at the outside of the cavity configured to measure output of the light emitting device. | 05-01-2014 |
20140131710 | STRUCTURES AND TECHNIQUES FOR ELECTRO-STATIC DISCHARGE (ESD) PROTECTION USING RING STRUCTURED DIODES - Electro-Static Discharge (ESD) protection using at least one ring-shape diode is disclosed. The ring-shape diode can be constructed from polysilicon, active region body on insulated substrate, or junction diode on silicon substrate. The diodes can have a first type of implant in an outer ring and a second type of implant in an inner ring to serve as two terminals of a diode coupled through contacts, vias, or metals. The two types of implant ring regions are separated with an isolation structure. The isolation can be LOCOS, STI, dummy gate, or silicide block layer (SBL). The ESD structure has at least a ring-shape diode with a first terminal coupled to an I/O pad and the second terminal coupled to a first supply voltage. The contours of the ring-shape diode can be circles, polygons, or other shapes. The ring-shape ESD structures can be multiple and be constructed in concentric manner. | 05-15-2014 |
20140131711 | STRUCTURES AND TECHNIQUES FOR USING SEMICONDUCTOR BODY TO CONSTRUCT BIPOLAR JUNCTION TRANSISTORS - A bipolar junction transistor built with a mesh structure of cells provided on a semiconductor body is disclosed. The mesh structure has at least one emitter cell with a first type of implant. At least one emitter cell has at least one side coupled to at least one cell with a first type of implant to serve as collector of the bipolar. The spaces between the emitter and collector cells are the intrinsic base of a bipolar device. At least one emitter cell has at least one vortex coupled to at least one cell with a second type of implant to serve as the extrinsic base of the bipolar. The emitter, collector, or base cells can be arbitrary polygons as long as the overall geometry construction can be very compact and expandable. The implant regions between cells can be separated with a space. A silicide block layer can cover the space and overlap into at least a portion of both implant regions. | 05-15-2014 |
20140151704 | Method, System, and Apparatus for Preparing Substrates and Bonding Semiconductor Layers to Substrates - Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed. | 06-05-2014 |
20140191236 | Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 07-10-2014 |
20140264341 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer. | 09-18-2014 |
20140264342 | SEMICONDUCTOR DEVICE INCLUDING A RESISTOR AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer. | 09-18-2014 |
20140284603 | COMPOSITE MICRO-ELECTRO-MECHANICAL-SYSTEM APPARATUS AND MANUFACTURING METHOD THEREOF - A MEMS apparatus comprising composite vibrating unit and the manufacturing method thereof are disclosed. The vibrating unit includes a stiffness element on which a first material is disposed. A second material being a conductive material is disposed on the first material and is extended to the stiffness element to remove electric charge on first material. When a temperature is changed, a variation direction of a Young's modulus of the first material is opposite to a variation direction of a Young's modulus of the stiffness element. The unique attributes above allow vibrating unit of the MEMS apparatus such as resonator and gyroscope to have stable resonance frequency against the change of temperature. | 09-25-2014 |
20140284604 | SEMICONDUCTOR STRUCTURE FOR EXTREME ULTRAVIOLET ELECTROSTATIC CHUCK WITH REDUCED CLAMPING EFFECT - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate. | 09-25-2014 |
20140291680 | SILICON MEMBER AND METHOD OF PRODUCING THE SAME - A silicon member and a method of producing the silicon member are provided. Cracking is suppressed in the silicon member even if the silicon member is used in a condition where it is heated. The silicon member | 10-02-2014 |
20140319524 | SUBSTRATES HAVING A BROADBAND ANTIREFLECTION LAYER AND METHODS OF FORMING A BROADBAND ANTIREFLECTION LAYER - In accordance with the purpose(s) of the present disclosure, as embodied and broadly described herein, embodiments of the present disclosure, in one aspect, relate to methods of making substrates having an antireflective layer, substrates having an antireflective layer, devices including a substrate having an antireflective layer, and the like. | 10-30-2014 |
20140327006 | Active Device Substrate and Manufacturing Method Thereof - An active device substrate includes a flexible substrate, an inorganic de-bonding layer, and at least one active device. The flexible substrate has a first surface and a second surface opposite to the first surface, wherein the first surface is a flat surface. The inorganic de-bonding layer covers the first surface of the flexible substrate, and the material of the inorganic de-bonding layer is metal, metal oxide or combination thereof. The active device is disposed on or above the second surface of the flexible substrate. | 11-06-2014 |
20140332814 | METHODS FOR THE SYNTHESIS OF ARRAYS OF THIN CRYSTAL GRAINS OF LAYERED SEMICONDUCTORS SNS2 AND SNS AT DESIGNED LOCATIONS - Methods of producing arrays of thin crystal grains of layered semiconductors, including the creation of stable atomic-layer-thick to micron-thick membranes of crystalline semiconductors by chemical vapor deposition. | 11-13-2014 |
20140339560 | SEMICONDUCTOR DEVICE - A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer. | 11-20-2014 |
20140367686 | ULTRATHIN SOLID STATE DIES AND METHODS OF MANUFACTURING THE SAME - Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region. | 12-18-2014 |
20150041810 | METHOD TO FABRICATE MICRO AND NANO DIAMOND DEVICES - A method including forming a diamond material on the surface of a substrate; forming a first contact and a separate second contact; and patterning the diamond material to form a nanowire between the first contact and the second contact. An apparatus including a first contact and a separate second contact on a substrate; and a nanowire including a single crystalline or polycrystalline diamond material on the substrate and connected to each of the first contact and the second contact. | 02-12-2015 |
20150294864 | METHOD FOR SUPPLYING SOURCE GAS FOR PRODUCING POLYCRYSTALLINE SILICON AND POLYCRYSTALLINE SILICON - In a method according to the present invention, an occurrence ratio of popcorn is suppressed by adjusting kinetic energy of a source gas supplied to a reaction furnace for producing polycrystalline silicon with a Siemens method (flow velocity and a supply amount of the source gas in source gas supply nozzle ejection ports). Specifically, in performing deposition reaction of the polycrystalline silicon under a reaction pressure of 0.25 MPa to 0.9 MPa, when flow velocity of the source gas in gas supply ports of the source gas supply nozzles ( | 10-15-2015 |
20150294966 | Semiconductor Device with Electrostatic Discharge Protection Structure - A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first isolation layer on the first surface of the semiconductor body and a first electrostatic discharge protection structure on the first isolation layer. The first electrostatic discharge protection structure has a first terminal and a second terminal. A second isolation layer is provided on the electrostatic discharge protection structure. A gate contact area on the second isolation layer is electrically coupled to the first terminal of the first electrostatic discharge protection structure. An electric contact structure is arranged in an overlap area between the gate contact area and the semiconductor body. The electric contact structure is electrically coupled to the second terminal of the first electrostatic discharge protection structure and electrically isolated from the gate contact area. | 10-15-2015 |
20150303247 | METHOD FOR FABRICATING A STRUCTURE - This method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C. | 10-22-2015 |
20150318442 | ELECTROLUMINESCENT DEVICES AND APPLICATIONS THEREOF - In one aspect, electroluminescent architectures and devices are described herein. An electroluminescent device, in some embodiments, comprises a first electrode, a second electrode and at least one light emitting layer comprising charge carrier injection structures in contact with an electroluminescent phase in a predetermined spatial distribution, the electroluminescent phase comprising luminescent centers in a semiconductor matrix. | 11-05-2015 |
20150325558 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell. | 11-12-2015 |
20150340320 | SEMICONDUCTOR DEVICES INCLUDING BULB-SHAPED TRENCHES - A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed. | 11-26-2015 |
20150340356 | SEMICONDUCTOR DEVICE - A protective diode is provided above a first guard ring region which surrounds an active region, with a field oxide film interposed there between. The protective diode may include a series pn zener diode in which a p+ layer and an n− layer are adjacent to each other. In a semiconductor device having the first guard ring region provided below the protective diode, cracks in the surface protective film may be prevented by providing a surface protective film that may be a polyimide film. The first guard ring region is provided below the protective diode and is connected to a second guard ring region that is provided in a portion other than the portion provided below the protective diode through a third guard ring region which is an intermediate region (R). Thus, when a surge voltage is applied, concentration of electric field on the outermost guard ring may be reduced. | 11-26-2015 |
20150380583 | NECKLACES OF SILICON NANOWIRES - In an embodiment of the disclosure, a structure is provided which comprises a silicon substrate and a plurality of necklaces of silicon nanowires which are in direct physical contact with a surface of the silicon substrate, wherein the necklaces cover an area of the silicon substrate. | 12-31-2015 |
20160013354 | INTEGRATED CIRCUIT INCLUDING ESD DEVICE | 01-14-2016 |
20160020295 | Semiconductor Devices and Fabrication Methods With Improved Word Line Resistance And Reduced Salicide Bridge Formation - Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor. The method may allow for a semiconductor with a silicide layer with improved resistance and reduced silicide bridge formation. | 01-21-2016 |
20160035898 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING METAL OXIDE - A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer. | 02-04-2016 |
20160035929 | LATERAL SINGLE-PHOTON AVALANCHE DIODE AND METHOD OF PRODUCING A LATERAL SINGLE-PHOTON AVALANCHE DIODE - The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation. | 02-04-2016 |
20160042948 | METAL INDUCED NANOCRYSTALLIZATION OF AMORPHOUS SEMICONDUCTOR QUANTUM DOTS - A method of forming crystallized semiconductor particles includes: forming amorphous semiconductor particles in a vacuumed aggregation chamber; transporting the amorphous semiconductor particles formed in the vacuumed aggregation chamber to a vacuumed deposition chamber within which a substrate is held; and applying a vapor of a metal catalyst to the amorphous semi-conductor particles while still in transit to the substrate in the vacuumed deposition chamber to induce crystallization of at least portion of the amorphous semiconductor particles via the metal catalyst in the transit, thereby depositing the crystallized semiconductor particles with the metal catalyst attached thereto onto the substrate. | 02-11-2016 |
20160049471 | PROCESS FOR FABRICATING SILICON NANOSTRUCTURES - A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent. | 02-18-2016 |
20160056309 | METHOD AND OPTOELECTRONIC STRUCTURE PROVIDING POLYSILICON PHOTONIC DEVICES WITH DIFFERENT OPTICAL PROPERTIES IN DIFFERENT REGIONS - Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure. | 02-25-2016 |
20160104741 | INTEGRATED IMAGING DEVICE FOR INFRARED RADIATION AND METHOD OF PRODUCTION - The integrated imaging device comprises a substrate ( | 04-14-2016 |
20160111348 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an interlayer insulating film covering: a cathode region and an anode region to form a pn junction with each other; a cathode electrode provided on the interlayer insulating film and connected to the cathode region through a first contact hole; and an anode electrode provided on the interlayer insulating film and connected to the anode region through a second contact hole. Among current paths in the cathode and anode regions, the current path in one of the cathode and anode regions that has a larger sheet resistance is shorter than the other current path, the current path in the cathode region extending from an interface of the pn junction to an end of the first contact hole closest to the interface, the current path in the anode region extending from the interface to an end of the second contact hole closest to the interface. | 04-21-2016 |
20160111551 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device including at least one electronic component and a method of manufacturing the same are provided. The electronic device may include a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer, and a first metal layer disposed on the insulating layer. The insulating layer may have a pattern corresponding to a pattern of the semiconductor layer or the first metal layer. The flexible layer has a Young's modulus less than 40 GPa and is disposed on the substrate to encapsulate the semiconductor layer. At least one first opening penetrates the flexible layer. At least one second metal layer is disposed on the flexible layer and in the first opening and electrically connected to the semiconductor layer. | 04-21-2016 |
20160133666 | Back-End Processing Using Low-Moisture Content Oxide Cap Layer - A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiO | 05-12-2016 |
20160189961 | Polycrystalline Silicon Substrate and Manufacturing Method thereof - The present invention discloses a polycrystalline silicon substrate and a manufacturing method thereof. The method comprises: provide a substrate; sequentially form an amorphous silicon layer, an insulating layer and a metal catalyst layer; anneal the substrate at the first time, so that metal ions of the metal catalyst layer extend down to the amorphous silicon layer through the insulating layer, thereby inducing the amorphous silicon on the amorphous silicon layer to crystallize at the first time; remove the insulating layer and the metal catalyst layer; anneal the substrate at the second time, so that the metal ions lateral diffuse along the amorphous silicon layer, thereby inducing the amorphous silicon on the amorphous silicon layer to crystallize at the second time, forming the polycrystalline silicon layer. Through the above way, it can reduce the metal catalyst residues during forming the polycrystalline silicon layer, decreasing the leakage current of the semiconductor layer in the thin film transistor, thereby raising the performance of the thin film transistor. | 06-30-2016 |
20160380012 | PHOTO SENSOR MODULE - The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer. | 12-29-2016 |
20170236916 | SEMICONDUCTOR DEVICE INCLUDING SENSE INSULATED-GATE BIPOLAR TRANSISTOR | 08-17-2017 |