Entries |
Document | Title | Date |
20080197380 | Semiconductor component comprising a drift zone and a drift control zone - A semiconductor component is disclosed herein comprising a drift zone and a drift control zone. The drift control zone is arranged adjacent to the drift zone and is dielectrically insulated from the drift zone by a dielectric layer. The drift control zone includes at least one first semiconductor layer and one second semiconductor layer. The first semiconductor layer has a higher charge carrier mobility than the second semiconductor layer. | 08-21-2008 |
20080203430 | ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR - Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias. | 08-28-2008 |
20080203431 | GaN-BASED NITRIC OXIDE SENSORS AND METHODS OF MAKING AND USING THE SAME - GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of separated GaN layers and an AlGaN layer interposed between and in contact with the GaN layers. Source and drain contact regions are formed on one of the GaN layers, and an exposed GaN gate region is formed between the source and drain contact regions for contact with the NO-containing fluid. The semiconductor structure most preferably is formed on a suitable substrate (e.g., SiC). An insulating layer may be provided so as to cover the semiconductor structure. The insulating layer will have a window formed therein so as to maintain exposure of the GaN gate region and thereby allow the gate region to contact the NO-containing fluid. Electrical contact pads are preferably provided in some embodiments so as to be in electrical contact with the source and drain contact regions, respectively. Electrical leads may thus be connected to the contact pads. According to other embodiments, the NO detection device will include a metalloporphyrin adsorbed on the GaN gate region. | 08-28-2008 |
20080203432 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A transistor including a gate insulation layer, a gate, and source/drain regions, the transistor comprising a semiconductor layer formed under the gate insulation layer for use as a channel region in a substrate, wherein the semiconductor layer is formed of a material having a lower bandgap than silicon. | 08-28-2008 |
20080203433 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickens and carrier gas concentration under the third compound semiconductor layer. | 08-28-2008 |
20080237638 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer. | 10-02-2008 |
20080246058 | GALLIUM NITRIDE MATERIAL TRANSISTORS AND METHODS ASSOCIATED WITH THE SAME - Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation. | 10-09-2008 |
20080258176 | Antimonide-based compound semiconductor with titanium tungsten stack - An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer. | 10-23-2008 |
20080272397 | SEMICONDUCTOR DEVICE WITH MODULATED FIELD ELEMENT - The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This element changes its conductivity and/or dielectric properties depending on the electrical potentials of the interface or interfaces between the modulated field element and the semiconductor device and/or incident electromagnetic radiation. The element is either connected to only one terminal of the semiconductor device, or not connected to any terminal of a semiconductor device nor to its active area(s). Such an element can be used as modulated field plate, or a part of a field plate, as a passivation layer or its part, as a guard ring or its part, as a smart field or charge control element or its part, as a feedback element or its part, as a sensor element or its part, as an additional electrode or its part, as an electromagnetic signal path or its part, and/or for any other functions optimizing or modernizing device performance. | 11-06-2008 |
20080277691 | Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions - A method for fabricating a microelectronic device including a support, an etched stack of thin layers including at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, plural semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or plural transistor channels. A gate surrounds the bars and is located between the first block and the second block, the gate being in contact with a first and second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via the insulating spacers. | 11-13-2008 |
20080277692 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer made of an Al | 11-13-2008 |
20080290370 | Semiconductor devices and methods of manufacturing thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material. | 11-27-2008 |
20080290371 | SEMICONDUCTOR DEVICES INCLUDING IMPLANTED REGIONS AND PROTECTIVE LAYERS - A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer. | 11-27-2008 |
20080296621 | III-nitride heterojunction device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 12-04-2008 |
20080303063 | Capacitorless DRAM and methods of manufacturing the same - Provided are a capacitorless DRAM and methods of manufacturing the same. The capacitorless DRAM may include a substrate including a source, a drain and a channel, a gate on the channel of the substrate, and a hole reserving unit below the channel. | 12-11-2008 |
20080308844 | Spin Transistor Using Perpendicular Magnetization - A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of the channel layer; a gate formed on the semiconductor substrate between the source and the drain to adjust spins of electrons passing through the channel layer, wherein spin-polarized electrons are injected from the source to the channel layer, and the electrons injected into the channel layer pass though the channel layer and are injected into the drain, and wherein the spins of the electrons passing through the channel layer undergo precession due to a spin-orbit coupling induced magnetic field according to a voltage of the gate. | 12-18-2008 |
20090001421 | NANOTUBE TRANSISTOR INTEGRATED CIRCUIT LAYOUT - An integrated circuit layout of a carbon nanotube transistor device includes a first and second conductive material. The first conductive material is connected to ends of single-walled carbon nanotubes below (or above) the first conductive material. The second conductive material is not electrically connected to the nanotubes below (or above) the second conductive material. The first conductive material may be metal, and the second conductive material may be polysilicon or metal. The nanotubes are perpendicular to the first conductive material. In one implementation, the first and second conductive materials form interdigitated fingers. In another implementation, the first conductive material forms a serpentine track. | 01-01-2009 |
20090001422 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - There is provided a manufacturing method of a semiconductor apparatus, including forming an InGaP layer on a substrate, forming a gate electrode having a Ti layer and an Au layer by vapor deposition on an upper surface of the InGaP layer, further forming a GaAs layer on the upper surface of the InGaP layer in a region different from a region in which the gate electrode is formed, and further forming a source electrode and a drain electrode on an upper surface of the GaAs layer. When the gate electrode having the Ti and Au layers is formed on the upper surface of the InGaP layer, the Ti and Au layers are formed with a substrate temperature being set equal to or lower than 180° C. | 01-01-2009 |
20090026497 | Method for Producing Semiconductor Device - A method for producing a semiconductor device ( | 01-29-2009 |
20090026498 | FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A field effect transistor includes: a nitride semiconductor layer having a channel layer; a gate electrode including a Schottky electrode that contacts the nitride semiconductor layer and includes a gallium doped zinc oxide (GZO) layer annealed in an inactive gas atmosphere; and ohmic electrodes connecting with the channel layer. | 01-29-2009 |
20090032845 | SOI FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC JUNCTION LEAKAGE - A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated. | 02-05-2009 |
20090039392 | III-NITRIDE POWER SEMICONDUCTOR DEVICE - A III-nitride power semiconductor device that includes a two dimensional electron gas having a reduced charge region under the gate thereof. | 02-12-2009 |
20090045438 | FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR - In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature. | 02-19-2009 |
20090050936 | NITRIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER INCLUDING THE SAME - A nitride semiconductor device includes a RESURF layer containing p-type In | 02-26-2009 |
20090050937 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region. | 02-26-2009 |
20090057718 | High Temperature Ion Implantation of Nitride Based HEMTS - A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer. | 03-05-2009 |
20090065810 | III-NITRIDE BIDIRECTIONAL SWITCHES - Bidirectional switches are described. The bidirectional switches include first and a second III-N based high electron mobility transistor. In some embodiments, the source of the first transistor is in electrical contact with a source of the second transistor. In some embodiments, the drain of the first transistor is in electrical contact with a drain of the second transistor. In some embodiments, the two transistors share a drift region and the switch is free of a drain contact between the two transistors. Matrix converters can be formed from the bidirectional switches. | 03-12-2009 |
20090078964 | ENHANCEMENT MODE III-NITRIDE SEMICONDUCTOR DEVICE WITH REDUCED ELECTRIC FIELD BETWEEN THE GATE AND THE DRAIN - An enhancement mode III-nitride heterojunction device that includes a region between the gate and the drain electrode thereof that is at the same potential as the source electrode thereof when the device is operating. | 03-26-2009 |
20090078965 | INDIVIDUALLY CONTROLLED MULTIPLE III-NITRIDE HALF BRIDGES - A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die. | 03-26-2009 |
20090085063 | COMPOUND SEMICONDUCTOR DEVICE WITH T-SHAPED GATE ELECTRODE AND ITS MANUFACTURE - A method for manufacturing a compound semiconductor device forms an EB resist layer on first SiN film, performs EB exposure at high dose for recess forming opening and at low dose for eaves removing opening, develops the high dose EB resist pattern to etch the first SiN film, selectively etches the cap layer to form a recess wider than the opening of the first SiN film leaving eaves of SiN, develops the low dose EB resist pattern to form the eaves removing opening, etches the first SiN film to extinguish the eaves, forms second SiN film on the exposed surface, forms a resist pattern having a gate electrode opening on the second SiN film to etch the second SiN film, forms a metal layer to form a gate electrode by lift-off. The SiN film in eaves shape will not be left. | 04-02-2009 |
20090090936 | ELECTRIC FIELD READ/WRITE HEAD, METHOD OF MANUFACTURING THE SAME, AND INFORMATION STORAGE DEVICE COMPRISING ELECTRIC FIELD READ/WRITE HEAD - Provided is an electric field head including a resistance sensor to read information recorded on a recording medium. The resistance sensor includes a first semiconductor layer including a source and a drain, and a second semiconductor layer that is heterogeneously combined with the first semiconductor layer. Also, the electric field head further includes a channel between the source and the drain, in a junction region of the first and second semiconductor layers. | 04-09-2009 |
20090095983 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME - In one example embodiment, an integrated semiconductor circuit ( | 04-16-2009 |
20090095984 | DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE - A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region. | 04-16-2009 |
20090108296 | SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES - An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon. | 04-30-2009 |
20090108297 | SEMI-INSULATING NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE, AND FIELD-EFFECT TRANSISTOR - A method of manufacturing a semi-insulating nitride semiconductor substrate includes the steps of forming on an underlying substrate, a mask in which dotted or striped coating portions having a width or a diameter Ds from 10 μm to 100 μm are arranged at an interval Dw from 250 μm to 2000 μm, growing a nitride semiconductor crystal on the underlying substrate with an HVPE method at a growth temperature from 1040° C. to 1150° C. by supplying a group III raw material gas and a group V raw material gas of which group V/group III ratio R | 04-30-2009 |
20090108298 | SEMICONDUCTOR DEVICE - A semiconductor device includes: substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain placed between the gate electrode and the drain electrode; an active area placed on the substrate region of the underneath part of the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the active area, the active area between gate and source, and the active area between gate and drain. Furthermore, width W | 04-30-2009 |
20090114950 | Semiconductor Device and Method of Manufacturing such a Device - The invention relates to a semiconductor device ( | 05-07-2009 |
20090121258 | FIELD EFFECT TRANSISTOR CONTAINING A WIDE BAND GAP SEMICONDUCTOR MATERIAL IN A DRAIN - A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region. | 05-14-2009 |
20090127584 | Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor - Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone. | 05-21-2009 |
20090140293 | HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article. | 06-04-2009 |
20090140294 | HETERO-STRUCTURED, INVERTED-T FIELD EFFECT TRANSISTOR - The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer. | 06-04-2009 |
20090140295 | GaN-based semiconductor device and method of manufacturing the same - A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer. | 06-04-2009 |
20090146183 | Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device - Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method. | 06-11-2009 |
20090146184 | SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance. | 06-11-2009 |
20090152590 | METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS - A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided. | 06-18-2009 |
20090159929 | HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device. | 06-25-2009 |
20090166676 | SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT - A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe. | 07-02-2009 |
20090166677 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and a transistor formed over the semiconductor substrate. The transistor includes a semiconductor layer laminate formed over the semiconductor substrate, a source electrode and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate, and a gate electrode formed between the source electrode and the drain electrode. The source electrode is electrically connected to the anode, and the drain electrode is electrically connected to the cathode. | 07-02-2009 |
20090173968 | Field Effect Transistor - A semiconductor device | 07-09-2009 |
20090189186 | Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor | 07-30-2009 |
20090189187 | Active area shaping for Ill-nitride device and process for its manufacture - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 07-30-2009 |
20090189188 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (Al | 07-30-2009 |
20090189189 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer. | 07-30-2009 |
20090194790 | Field effect transister and process for producing the same - A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess part and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess part; a gate electrode formed on the insulating layer at the recess part; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess part in between and electrically connected to the semiconductor operating layer. The recess part includes a side wall protruding and inclined relative to the semiconductor operating layer. | 08-06-2009 |
20090194791 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device including an electron transport layer that is formed on a substrate and includes a III-V nitride compound semiconductor, a gate insulating film that is positioned above the compound semiconductor layer, and a gate electrode that is positioned on the gate insulating film. The gate insulating film includes a first insulating film that includes oxygen, at least a single metal element selected from a metal bonding with the oxygen and forming a metal oxide having a dielectric constant no less than 10, and at least a single metal element selected from Si and Al. | 08-06-2009 |
20090200575 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate. | 08-13-2009 |
20090212324 | HETEROJUNCTION FIELD EFFECT TRANSISTOR - An aspect of the invention provides a heterojunction field effect transistor that comprises: a base; a first GaN channel layer formed on the base; an AlN electron supply layer formed on the first GaN layer, and a second GaN cap layer formed on the AlN layer. | 08-27-2009 |
20090212325 | Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode formed on the third semiconductor layer. A concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode. | 08-27-2009 |
20090212326 | Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two dimensional carrier gas layer of a first conductive type on a heterojunction interface between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the second semiconductor layer and having an impurity introduced therein; a source electrode formed on the third semiconductor layer; a drain electrode formed on the third semiconductor layer and separated from the source electrode; a fourth semiconductor layer formed on or above the second semiconductor layer and has a second conductive type which is different from the first conductive type; and a gate electrode electrically connected on the fourth semiconductor layer. The fourth semiconductor layer is located adjacent to and surrounded by the third semiconductor layer. | 08-27-2009 |
20090218597 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME - A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate. | 09-03-2009 |
20090218598 | WARP-FREE SEMICONDUCTOR WAFER, AND DEVICES USING THE SAME - A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces. | 09-03-2009 |
20090230428 | DEVICES USING ABRUPT METAL-INSULATOR TRANSITION LAYER AND METHOD OF FABRICATING THE DEVICE - The abrupt metal-insulator transition device includes: an abrupt metal insulator transition material layer including an energy gap of less than or equal to | 09-17-2009 |
20090230429 | Field effect transistor - A field effect transistor ( | 09-17-2009 |
20090230430 | Field effect transistor - A field effect transistor includes a layer structure made of compound semiconductor ( | 09-17-2009 |
20090230431 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention has as an objective to provide: a semiconductor device to satisfy both of the trade-off characteristic advantages of the HBT; and the HFET and a manufacturing method thereof. The semiconductor device in the present invention is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer which are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode, the GaAs cap layer including portion of the GaAs external sub-collector region, and the source electrode and the drain electrode being formed on the GaAs cap layer. | 09-17-2009 |
20090242937 | Semiconductor device and manufacturing method - A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode. | 10-01-2009 |
20090250723 | Electronic Device and Heterojunction FET - In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO | 10-08-2009 |
20090261383 | OPTICAL DEVICE HAVING STRAINED BURIED CHANNEL - Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area. | 10-22-2009 |
20090267113 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semi-conductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed. | 10-29-2009 |
20090267114 | FIELD EFFECT TRANSISTOR - A field effect transistor | 10-29-2009 |
20090278171 | High linearity doped-channel FET - A high linearity doped-channel FET, comprises a substrate, a buffer layer, a channel layer and a cap layer stacked downwardly thereon. The cap layer has a source region, a drain region with a distance apart from the source region and a gate region formed by removing part of the cap layer between the source region and the drain region. A source electrode and a drain electrode are respectively formed on the source region and the drain region, and a gate electrode is formed on the gate region, wherein the source region and the drain region of the cap layer are respectively provided with an opening for forming a good ohmic contact between the source region and the drain region with the channel layer respectively. | 11-12-2009 |
20090278172 | GaN based semiconductor element - The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves. | 11-12-2009 |
20090294800 | HYBRID FET INCORPORATING A FINFET AND A PLANAR FET - A stack of a vertical fin and a planar semiconductor portion are formed on a buried insulator layer of a semiconductor-on-insulator substrate. A hybrid field effect transistor (FET) is formed which incorporates a finFET located on the vertical fin and a planar FET located on the planar semiconductor portion. The planar FET enables a continuous spectrum of on-current. The surfaces of the vertical fin and the planar semiconductor portion may be set to coincide with crystallographic orientations. Further, different crystallographic orientations may be selected for the surfaces of the vertical fin and the surfaces of the planar semiconductor portion to tailor the characteristics of the hybrid FET. | 12-03-2009 |
20090294801 | METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE - Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned. | 12-03-2009 |
20090294802 | FIELD EFFECT TRANSISTOR WITH FREQUENCY DEPENDENT GATE-CHANNEL CAPACITANCE - A field effect transistor having a channel, a gate, and a means for decreasing a gate-to-channel capacitance of the transistor as an operating frequency of the transistor increases. The means can comprise, for example, a barrier layer disposed between the gate and the channel, which has a dielectric permittivity and/or a conductivity that varies with an operating frequency of the transistor. In an embodiment, the barrier layer comprises a conducting material, such as conducting polymer, conducting semiconductor, conducting semi-metal, amorphous silicon, polycrystalline silicon, and/or the like. | 12-03-2009 |
20090302349 | STRAINED GERMANIUM FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - A strained germanium field effect transistor (FET) and method of fabricating the same is related to the strained Ge field effect transistor with a thin and pure Ge layer as a carrier channel. The pure Ge layer with the thickness between 1 nm and 10 nm is formed between an unstrained substrate and a gate insulation layer, and directly contacts with the unstrained substrate. The gate is disposed on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained Ge FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. Furthermore, a Si protective layer with extremely thin thickness can be deposed between and directly contacts with the gate insulation layer and the pure Ge layer. | 12-10-2009 |
20090302350 | Tensile Strained NMOS Transistor Using Group III-N Source/Drain Regions - Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors. | 12-10-2009 |
20090309134 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A multilayer structure including a first electron supply layer and a second electron supply layer is used for an electron supply layer. A multilayer structure including an SiN film and an SiO | 12-17-2009 |
20090315075 | SEMICONDUCTOR DEVICE - A semiconductor device is, constituted by: a nitride group semiconductor functional layer which includes a first nitride group semiconductor region, a second nitride group semiconductor region provided on the first nitride group semiconductor region by a hetero junction, and a two-dimensional carrier gas channel near the hetero junction of the first nitride group semiconductor region; a first main electrode and a second main electrode connected to the two-dimensional carrier gas channel by ohmic contact; and a gate electrode disposed between the first main electrode and the second main electrode. The nitride group semiconductor region has different thicknesses between the second main electrode and the gate electrode, and between the first main electrode and the gate electrode. | 12-24-2009 |
20090315076 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. | 12-24-2009 |
20100001317 | CMOS TRANSISTOR AND THE METHOD FOR MANUFACTURING THE SAME - A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion. | 01-07-2010 |
20100001318 | Field effect transistor, method of manufacturing the same, and semiconductor device - A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers | 01-07-2010 |
20100006894 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer. | 01-14-2010 |
20100006895 | III-NITRIDE SEMICONDUCTOR DEVICE - A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction. | 01-14-2010 |
20100025729 | PASSIVATED III-V FIELD EFFECT STRUCTURE AND METHOD - An improved insulated gate field effect device ( | 02-04-2010 |
20100032716 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer becomes a substantially maximum value. | 02-11-2010 |
20100044751 | ENHANCEMENT MODE III-NITRIDE DEVICE WITH FLOATING GATE AND PROCESS FOR ITS MANUFACTURE - An enhancement mode III-Nitride device has a floating gate spaced from a drain electrode which is programmed by charges injected into the floating gate to form a permanent depletion region which interrupts the 2-DEG layer beneath the floating gate. A conventional gate is formed atop the floating gate and is insulated therefrom by a further dielectric layer. The device is a normally off E mode device and is turned on by applying a positive voltage to the floating gate to modify the depletion layer and reinstate the 2-DEG layer. The device is formed by conventional semiconductor fabrication techniques. | 02-25-2010 |
20100044752 | Semiconductor device and manufacturing method - A metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) has a substrate in which an electron supply layer is interposed between an electron channel layer and the surface of the substrate. A pair of main electrodes are formed on the surface of the substrate. A recess is formed in the surface of the substrate between the main electrodes. A gate insulation film is formed on the surface of the substrate, at least between the first and second main electrodes, covering the inside walls and floor of the recess. A gate electrode is formed on the gate insulation film, filling in the recess. The gate insulation film has a crystal density of at least 2.9 g/cm | 02-25-2010 |
20100044753 | SEMICONDUCTOR DEVICE - A nitride semiconductor device | 02-25-2010 |
20100044754 | STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area. | 02-25-2010 |
20100052014 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (Al | 03-04-2010 |
20100059791 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device, which reduces the earth inductance, and a fabrication method for the same is provided. | 03-11-2010 |
20100065886 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween. | 03-18-2010 |
20100065887 | FIELD EFFECT TRANSISTOR SOURCE OR DRAIN WITH A MULTI-FACET SURFACE - FET configurations in which two (or more) facets are exposed on a surface of a semiconductor channel, the facets being angled with respect to the direction of the channel, allow for conformal deposition of a convex or concave S/D. A convex tip of the S/D enhances electric fields at the interface, reducing the resistance between the S/D and the channel. In contrast, a S/D having a concave tip yields a dual-gate FET that emphasizes reduced short-channel effects rather than electric field enhancement. The use of self-limiting, selective wet etches to expose the facets facilitates process control, control of interface chemistry, and manufacturability. | 03-18-2010 |
20100072516 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes an active layer formed between an n-type cladding layer and a p-type cladding layer, and a current confining layer having a conductive area through which a current flows to the active layer. The current confining layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed on and in contact with the first semiconductor layer and has a smaller lattice constant than that of the first semiconductor layer. The third semiconductor layer is formed on and in contact with the second semiconductor layer and has a lattice constant that is smaller than that of the first semiconductor layer and larger than that of the second semiconductor layer. | 03-25-2010 |
20100078681 | Integrated Circuit Including a Hetero-Interface and Self Adjusted Diffusion Method for Manufacturing the Same - An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region. | 04-01-2010 |
20100078682 | POWER MOSFET HAVING A STRAINED CHANNEL IN A SEMICONDUCTOR HETEROSTRUCTURE ON METAL SUBSTRATE - A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor. | 04-01-2010 |
20100078683 | SEMICONDUCTOR DEVICE - A semiconductor device include: a nitride group semiconductor functional layer including a second nitride group semiconductor region on a first nitride group semiconductor region where a two-dimensional carrier gas layer is made, the second nitride group semiconductor region functioning as a barrier layer; a first main electrode electrically connected to one end of the two-dimensional carrier gas layer; a second main electrode electrically connected to the other end of the two-dimensional carrier gas layer; and metal oxide films placed between the first and second main electrodes, electrically connected to the first main electrode, and reducing a carrier density of the two-dimensional carrier gas layer. | 04-01-2010 |
20100078684 | SELECTIVE HIGH-K DIELECTRIC FILM DEPOSITION FOR SEMICONDUCTOR DEVICE - Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer. | 04-01-2010 |
20100084685 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an SiGe film formed on part of a semiconductor substrate and including a channel region and at least part of source/drain extension regions between which the channel region is positioned, source/drain contact regions formed in a surface area of the semiconductor substrate and brought into contact with the pair of source/drain extension regions, a gate structure having a gate insulation film formed on the SiGe film and a gate electrode formed on the gate insulation film, first sidewall films formed on the SiGe film along side surfaces of the gate structure, second sidewall films formed on the SiGe film along the first sidewall films, third sidewall films formed on the source/drain contact regions along side surfaces of the SiGe film and the second sidewall films, and first silicide films formed on the source/drain contact regions. | 04-08-2010 |
20100084686 | ASSYMETRIC HETERO-DOPED HIGH-VOLTAGE MOSFET (AH2MOS) - An asymmetric heterodoped metal oxide (AH | 04-08-2010 |
20100090250 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride. | 04-15-2010 |
20100102357 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and the second nitride semiconductor layer such that a two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode; a drain electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having p-type conductivity; and a gate electrode formed on the fourth nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap. | 04-29-2010 |
20100127307 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer. | 05-27-2010 |
20100148217 | Graded high germanium compound films for strained semiconductor devices - Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed. | 06-17-2010 |
20100155779 | Field Effect Transistor - In a field effect transistor, a Group III nitride semiconductor layer structure containing a hetero junction, a source electrode | 06-24-2010 |
20100155780 | SEMICONDUCTOR DEVICE - An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode. | 06-24-2010 |
20100187570 | Heterojunction Transistors Having Barrier Layer Bandgaps Greater Than Channel Layer Bandgaps and Related Methods - A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed. | 07-29-2010 |
20100193839 | III-V-Group compound semiconductor device - A III-V-group compound semiconductor device includes a substrate, a channel layer provided over the substrate, a barrier layer provided on the channel layer so as to form a hetero-interface, a plurality of electrodes provided on the barrier layer, an insulator layer provided to cover an entire upper surface of the barrier layer except for at least partial regions of the electrodes, and a hydrogen-absorbing layer stacked on the insulator layer or an integrated layer in which an hydrogen-absorbing layer is integrated with the insulator layer. | 08-05-2010 |
20100193840 | SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES - A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin. | 08-05-2010 |
20100207164 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a first nitride semiconductor layer | 08-19-2010 |
20100219450 | ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES - A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap. | 09-02-2010 |
20100219451 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A p-type nitride compound semiconductor layer is formed on a buffer formed on a substrate. An n-type contact region is formed by ion implantation under a source electrode and a drain electrode. An electric-field reducing layer made of an n-type nitride compound semiconductor is formed on the p-type nitride compound semiconductor layer. A career density of the electric-field reducing layer is lower than that of the n-type contact region. A first end portion of the electric-field reducing layer contacts with the n-type contact region, and a second end portion of the electric-field reducing layer overlaps with a gate electrode. | 09-02-2010 |
20100224910 | FIELD EFFECT TRANSISTOR - Disclosed is an HJFET | 09-09-2010 |
20100230721 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a gate electrode formed on a gate insulation film on a main surface of a semiconductor substrate of a first conductivity type; source/drain regions formed to sandwich a channel region formed below the gate electrode, the source/drain regions having a structure in which a first semiconductor layer and a second semiconductor layer are stacked in this order, the first semiconductor layer containing a first element and an impurity of a second conductivity type that are forgiving strain to the channel region, and containing a second element that is for suppressing a diffusion of the impurity of the second conductivity type, the second semiconductor layer containing the first element and the impurity of the second conductivity type; and source/drain extension regions adjacent to the channel region, the extension regions extending respectively from the second semiconductor layers. | 09-16-2010 |
20100244097 | FIELD EFFECT TRANSISTOR - Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode | 09-30-2010 |
20100252862 | Source/Drain Engineering of Devices with High-Mobility Channels - An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof. | 10-07-2010 |
20100252863 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes. | 10-07-2010 |
20100258841 | BACK DIFFUSION SUPPRESSION STRUCTURES - An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer. | 10-14-2010 |
20100258842 | ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS - An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å. | 10-14-2010 |
20100258843 | ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME - An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process. | 10-14-2010 |
20100258844 | BUMPED, SELF-ISOLATED GaN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE - A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device. | 10-14-2010 |
20100276732 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lower barrier layer | 11-04-2010 |
20100283083 | Normally-off field effect transistor using III-nitride semiconductor and method for manufacturing such transistor - Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region. | 11-11-2010 |
20100289062 | Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same - A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers. | 11-18-2010 |
20100295096 | Integrated Devices on a Common Compound Semiconductor III-V Wafer - A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs. | 11-25-2010 |
20100301392 | Source/Drain Re-Growth for Manufacturing III-V Based Transistors - A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer. | 12-02-2010 |
20100301393 | FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR - There is provided a field effect transistor of a normally-OFF operation having a low contact resistance and capable of avoiding increases in on-resistance and maintaining high channel mobility. In this field effect transistor, a thin-layer portion | 12-02-2010 |
20100301394 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. | 12-02-2010 |
20100308373 | FIELD-EFFECT TRANSISTOR - A field-effect transistor provided with a substrate, a channel layer, a carrier supply layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer that is laminated on the carrier supply layer between the source electrode and the drain electrode, and suppresses current collapse, an opening that is formed between an edge of the first insulating layer opposing the drain electrode and the drain electrode, and a second insulating layer that is laminated on the carrier supply layer exposed in the opening. | 12-09-2010 |
20100308374 | STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD - A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate. | 12-09-2010 |
20100314663 | SEMICONDUCTOR DEVICE - One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor. | 12-16-2010 |
20100320504 | SEMICONDUCTOR DEVICE COMPRISING GATE ELECTRODE SURROUNDING ENTIRE CIRCUMFERENCE OF CHANNEL REGION AND METHOD FOR MANUFACTURING THE SAME - Two first semiconductor layers are on a silicon substrate at a given distance from each other. Two second semiconductor layers are on the respective first semiconductor layers and includes a material different from a material of the first semiconductor layers. A first channel region is formed like a wire between the two second semiconductor layers. A first insulating layer is around the first channel region. A second insulating film is on each of opposite side surfaces of the two first semiconductor layers. A third insulating film is on each of opposite side surfaces of the two second semiconductor layers. A gate electrode is on the first, second, and third insulating films. Film thickness of the second insulating film is larger than film thickness of the first insulating film. | 12-23-2010 |
20100320505 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND AMPLIFIER - A semiconductor device includes a nitride semiconductor layer having a (0001) face and a (000-1) face, formed above a common substrate; a (0001) face forming layer provided partially between the substrate and the nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, provided on the nitride semiconductor layer having the (0001) face; and a hole extracting electrode provided on the nitride semiconductor layer having the (000-1) face. | 12-23-2010 |
20100327317 | Germanium on insulator using compound semiconductor barrier layers - Embodiments of an apparatus and methods for providing germanium on insulator using a large bandgap barrier layer are generally described herein. Other embodiments may be described and claimed. | 12-30-2010 |
20100327318 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer ( | 12-30-2010 |
20100327319 | CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g. Si) channel and allows to contain the whole doping (e.g. B atoms) entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current. | 12-30-2010 |
20100327320 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum. | 12-30-2010 |
20100327321 | Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling - A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions. | 12-30-2010 |
20110006345 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field effect transistor according to the present invention includes A field effect transistor, comprising: a nitride-based semiconductor multilayer structure, at least including, a drift layer formed of n-type or i-type AlxGa | 01-13-2011 |
20110006346 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device that has high electron mobility while reducing a gate leakage current, and superior uniformity and reproducibility of the threshold voltage, and is also applicable to the enhancement mode type. The semiconductor device according to the present invention is a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed Al | 01-13-2011 |
20110012173 | SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped GaN layer ( | 01-20-2011 |
20110012174 | Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region - A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction. | 01-20-2011 |
20110018032 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is provided which is capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the strained silicon layer and silicon-germanium layer. | 01-27-2011 |
20110018033 | SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method. | 01-27-2011 |
20110024795 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of manufacturing a HEMT device that has excellent two-dimensional electron gas characteristics and is capable of performing normally-off operation. A channel layer is formed of a first group III nitride represented by In | 02-03-2011 |
20110031530 | FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE - A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized. | 02-10-2011 |
20110031531 | PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound. | 02-10-2011 |
20110037101 | SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped GaN layer ( | 02-17-2011 |
20110049569 | Semiconductor structure including a field modulation body and method for fabricating same - According to one embodiment, a semiconductor structure including an equipotential field modulation body comprises a trench surrounding an active region of a group III-V power device fabricated in the semiconductor structure, and the equipotential field modulation body formed in the trench and extending over a portion of the active region. The equipotential field modulation body is electrically coupled to a terminal of the group III-V power device. In one embodiment, a method for fabricating a semiconductor structure including an equipotential field modulation body comprises fabricating a trench surrounding an active region of the semiconductor structure, forming the equipotential field modulation body in the trench, the equipotential field modulation body extending over a portion of the active region, and electrically coupling the equipotential field modulation body to a terminal of a group III-V power device fabricated in the active region. | 03-03-2011 |
20110049570 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent ohmic contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of In | 03-03-2011 |
20110049571 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent schottky contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of In | 03-03-2011 |
20110062494 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 03-17-2011 |
20110062495 | Field Effect Transistor with Access Region Recharge - The current invention provides the design of the field effect transistor with lateral channel suitable for high voltage switching. In such a transistor, the electrical charge stored in the high electric field region has to vary as the transistor switches from ON to OFF state and back. The invention provides the method of calculating the necessary recharging path parameters based on the material parameters of the FET and desired blocking voltage, ON state resistance and switching speed. The invention can be used in power electronics by providing circuits and parts, for example, for electrical power distribution between power plant customers, for automotive, craft and space applications and many other applications where high voltage in excess of 400-600 V is involved. | 03-17-2011 |
20110062496 | Methods and Compositions for Preparing Ge/Si Semiconductor Substrates - The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge layer on a semiconductor substrate using an admixture of (a) (GeH | 03-17-2011 |
20110062497 | SEMICONDUCTOR DEVICE STRUCTURE WITH STRAIN LAYER AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect. | 03-17-2011 |
20110068368 | SEMICONDUCTOR DEVICE COMPRISING A HONEYCOMB HETEROEPITAXY - A semiconductor device comprising a honeycomb heteroepitaxy and method for making same are described. One embodiment is a method comprising defining a mask on a silicon substrate, the mask comprising a plurality of nano-size openings therethrough; subsequent to the defining, creating essentially defect-free non-silicon semiconductor nano-islands on portions of a surface of the silicon substrate exposed through the mask openings; subsequent to the creating, depositing high-k gate dielectric is deposited on the nano-islands; and subsequent to the deposition, constructing transistors on the nano-islands. | 03-24-2011 |
20110068369 | METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe - A method for fabricating a circuit structure is disclosed. The method includes depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface. Blanket disposing a first sequence of layers over the SiGe layer, including a high-k dielectric and a metal, and incorporating this first sequence of layers into the gatestacks and gate insulators of both NFET devices and PFET devices. This first sequence of layers is selected to yield desired device parameter values for the PFET devices. The method further includes removing the gatestack, the gate dielectric, and the SiGe layer, and re-forming the NFET devices by deploying a second sequence of layers that include a second high-k dielectric and a second metal. The second sequence of layers is selected to yield desired device parameter values for the NFET devices. A circuit structure is also disclosed. PFET devices have a gate dielectric with a high-k dielectric, a gatestack with a metal, and a silicide formed over the p-source/drain. NFET devices also include a gate dielectric with a high-k dielectric, a gatestack with a metal, and silicide formed over the n-source/drain. An epitaxial SiGe layer over the substrate surface is present everywhere in the device structures with the exception that it is absent underneath the NFET gate dielectric. The PFET and NFET device parameters are independently optimized through the composition of their gate dielectrics and gate stacks. | 03-24-2011 |
20110073909 | REPLACEMENT SPACER FOR TUNNEL FETS - A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess. | 03-31-2011 |
20110073910 | NITRIDE SEMICONDUCTOR MATERIAL, SEMICONDUCTOR ELEMENT, AND MANUFACTURING METHOD THEREOF - The nitride semiconductor material according to the present invention includes a group III nitride semiconductor and a group IV nitride formed on the group III nitride semiconductor, where an interface between the group III nitride semiconductor and the group IV nitride has a regular atomic arrangement. Moreover, an arrangement of nitrogen atoms of the group IV nitride in the interface and an arrangement of group III atoms of the group III nitride semiconductor in the interface may be substantially identical. | 03-31-2011 |
20110079822 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A compound semiconductor device includes an electron transit layer; an electron supply layer formed over the electron transit layer; a first recessed portion and a second recessed portion formed in the electron supply layer; a chemical compound semiconductor layer including impurities that buries the first recessed portion and the second recessed portion and covers over the electron supply layer; a source electrode formed over the chemical compound semiconductor layer which buries the first recessed portion; a drain electrode formed over the chemical compound semiconductor layer which buries the second recessed portion; and a gate electrode formed over the electron supply layer between the source electrode and the drain electrode, wherein, in the chemical compound semiconductor layer, a concentration of impurities included below the source electrode and the drain electrode is higher than a concentration of impurities included near the gate electrode. | 04-07-2011 |
20110084309 | METHOD FOR ENHANCING THE RELIABILITY OF A P-CHANNEL SEMICONDUCTOR DEVICE AND A P-CHANNEL SEMICONDUCTOR DEVICE MADE THEREOF - A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels E | 04-14-2011 |
20110108885 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The object of the present invention is to increase channel current density while a GaN-based field effect transistor operates in a normally-off mode. Provided is a semiconductor device comprising a group 3-5 compound semiconductor channel layer containing nitrogen, an electron supply layer that supplies electrons to the channel layer, a semiconductor layer that is formed on a side of the electron supply layer opposite the side facing the channel layer and that is an intrinsic or n-type group 3-5 compound semiconductor containing nitrogen, and a control electrode that is formed to contact the semiconductor layer or formed with an intermediate layer interposed between itself and the semiconductor layer. | 05-12-2011 |
20110114996 | Inducement of Strain in a Semiconductor Layer - Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces. | 05-19-2011 |
20110127579 | STACKED OXIDE MATERIAL, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming a first oxide component over a base component, causing crystal growth which proceeds from a surface toward an inside of the first oxide component by first heat treatment to form a first oxide crystal component at least partly in contact with the base component, forming a second oxide component over the first oxide crystal component; and causing crystal growth by second heat treatment using the first oxide crystal component as a seed to form a second oxide crystal component. | 06-02-2011 |
20110127580 | CAPACITOR-LESS MEMORY DEVICE - Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability. | 06-02-2011 |
20110133248 | VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure. | 06-09-2011 |
20110133249 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickens and carrier gas concentration under the third compound semiconductor layer. | 06-09-2011 |
20110140169 | Highly conductive source/drain contacts in III-nitride transistors - In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed. | 06-16-2011 |
20110140170 | STRUCTURE AND METHOD FOR MAKING A STRAINED SILICON TRANSISTOR - A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate. | 06-16-2011 |
20110140171 | APPARATUS AND METHODS FOR FORMING A MODULATION DOPED NON-PLANAR TRANSISTOR - Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed. | 06-16-2011 |
20110147795 | MATERIALS FOR INTERFACING HIGH-K DIELECTRIC LAYERS WITH III-V SEMICONDUCTORS - A group III chalcogenide layer for interfacing a high-k dielectric to a III-V semiconductor surface and methods of forming the same. A III-V QWFET includes a gate stack which comprises a high-K gate dielectric layer disposed on an interfacial layer comprising a group III chalcogenide. In an embodiment, a III-V semiconductor surface comprising a native oxide is sequentially exposed to TMA and H | 06-23-2011 |
20110156099 | ENHANCED CONFINEMENT OF SENSITIVE MATERIALS OF A HIGH-K METAL GATE ELECTRODE STRUCTURE - When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions. | 06-30-2011 |
20110169051 | Structure for Use in Fabrication of PiN Heterojunction TFET - A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region. | 07-14-2011 |
20110169052 | MEMFET RAM - A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate is disposed over the channel-formation portion and coupled with the channel-formation portion. The memristive gate includes a plurality of mobile ions and a confinement structure for the plurality of mobile ions. Moreover, the memristive gate is configured to switch the channel-formation portion from a first conductivity state to a second conductivity state in response to migration of the plurality of mobile ions within the confinement structure. | 07-14-2011 |
20110169053 | SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped InGaAs layer; an Si-doped GaAs layer formed thereover and equipped with a first recess portion; a two-layered semiconductor layer formed between the undoped InGaAs layer and the Si-doped GaAs layer, equipped with a second recess portion provided in the first recess portion, and composed of an undoped ordered InGaP layer and an undoped GaAs layer formed thereover; a C-doped GaAs layer provided over the undoped InGaAs layer in the second recess portion; and a sidewall insulating film provided between the C-doped GaAs layer and the interface between the undoped GaAs layer and the undoped ordered InGaP layer, but not provided at a portion between the undoped ordered InGaP layer and the C-doped GaAs layer. | 07-14-2011 |
20110175141 | SEMICONDUCTOR DEVICES INCLUDING MOS TRANSISTORS HAVING AN OPTIMIZED CHANNEL REGION AND METHODS OF FABRICATING THE SAME - A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern. | 07-21-2011 |
20110175142 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer, and having a wider bad gap than the first nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, which are formed on the second nitride semiconductor layer; a high resistive layer formed lower than the first nitride semiconductor layer; a conductive layer formed under and in contact with the high resistive layer; a lower insulating layer formed under the conductive layer; and a bias terminal electrically connected to the conductive layer. | 07-21-2011 |
20110180850 | Configuration and manufacturing method of low-resistance gate structures for semiconductor devices and circuits - The present invention provides methods for fabricating devices with low resistance structures involving a lift-off process. A radiation blocking layer is introduced between two resist layers in order to prevent intermixing of the photoresists. Cavities suitable for the formation of low resistance T-gates or L-gates can be obtained by a first exposure, developing, selective etching of blocking layer and a second exposure and developing. In another embodiment, a low resistance gate structure with pillars to enhance mechanical stability or strength is provided. | 07-28-2011 |
20110180851 | CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION - Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage. | 07-28-2011 |
20110180852 | ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES - A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap. | 07-28-2011 |
20110180853 | CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE - An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material. | 07-28-2011 |
20110186912 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. | 08-04-2011 |
20110193134 | STEP DOPING IN EXTENSIONS OF III-V FAMILY SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer. | 08-11-2011 |
20110198669 | TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced. | 08-18-2011 |
20110198670 | METHOD TO REDUCE MOL DAMAGE ON NiSi - Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance. | 08-18-2011 |
20110210375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device including a tunnel FET, includes a gate electrode, which is formed on a first semiconductor layer formed of Si | 09-01-2011 |
20110210376 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm | 09-01-2011 |
20110215376 | PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION - A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator. | 09-08-2011 |
20110215377 | Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region - A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region. | 09-08-2011 |
20110227132 | FIELD-EFFECT TRANSISTOR - The present invention has as an object to provide a FET having low on-resistance. The FET according to the present invention includes: first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a higher band gap energy than the third nitride semiconductor layer. A channel is formed in a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer. | 09-22-2011 |
20110233610 | Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions - Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium. | 09-29-2011 |
20110233611 | SEMICONDUCTOR DEVICE HAVING ANALOG TRANSISTOR WITH IMPROVED OPERATING AND FLICKER NOISE CHARACTERISTICS AND METHOD OF MAKING SAME - A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1. | 09-29-2011 |
20110241073 | STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer through buried oxide and partially etching the silicon substrate; refilling a bottom and sidewall surfaces of the etched source and drain regions with epitaxial silicide/germanide to form e-SiGe source and drain regions; capping the source and drain regions with self-aligning silicide/germanide; providing a silicide layer formed over the gate conductor line; providing a first stress liner over the gate and the e-SiGe source and drain regions; depositing a planarized dielectric over the self-aligning silicide/germanide; inverting the donor substrate; bonding the donor substrate to a host wafer; and selectively exposing the buried oxide and the e-SiGe source and drain regions by removing the donor wafer. | 10-06-2011 |
20110254053 | SUPERCONDUCTOR TRANSISTOR AND METHOD FOR MANUFACTURING SUCH TRANSISTOR - This field-effect superconductor transistor ( | 10-20-2011 |
20110254054 | SEMICONDUCTOR DEVICE - A semiconductor device has at least an n-type MIS transistor, which includes a first gate insulating film formed on a first semiconductor region in a semiconductor substrate, a first gate electrode formed on the first gate insulating film, first sidewalls formed on the side surfaces of the first gate electrode, and carbon-containing silicon regions formed laterally outside the first sidewalls. The top surfaces of the carbon-containing silicon regions are at a level higher than the top surface of a region in the first semiconductor region lying under the first gate insulating film. | 10-20-2011 |
20110260214 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor manufacturing. According to the present invention, the semiconductor device comprises: a semiconductor substrate; a gate region located above the semiconductor substrate; S/D regions located at both sides of the gate region and made of a stress material; wherein a concentrated stress region is formed between the gate region and the semiconductor substrate, and the concentrated stress region comprises an upper SOI layer adjacent to the gate region above, and a lower stress release layer adjacent to the semiconductor substrate below. The present invention applies to the manufacturing of a MOSFET. | 10-27-2011 |
20110260215 | GALLIUM LATHANIDE OXIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition. | 10-27-2011 |
20110272739 | METHOD FOR FABRICATING A STRAINED STRUCTURE - A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film. | 11-10-2011 |
20110272740 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region. | 11-10-2011 |
20110278646 | Balance Step-Height Selective Bi-Channel Structure on HKMG Devices - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 11-17-2011 |
20110303950 | FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET - Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region. | 12-15-2011 |
20110303951 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility. | 12-15-2011 |
20110309411 | FIELD EFFECT TRANSISTOR - An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a second semiconductor layer including an i-type second oxide semiconductor is provided in contact with the other surface. The energy difference between a vacuum level and a Fermi level in the second oxide semiconductor is larger than that in the first oxide semiconductor. In the first semiconductor layer, a region in the vicinity of the junction surface with the second oxide semiconductor which satisfies the above condition is a region having an extremely low carrier concentration (a quasi-i-type region). By using the region as a channel, the off-state current can be reduced. Further, a drain current of the FET flows through the first oxide semiconductor having a high mobility; accordingly, a large amount of current can be extracted. | 12-22-2011 |
20110316045 | LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET - A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad. | 12-29-2011 |
20110316046 | Field Effect Transistor Device - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 12-29-2011 |
20110316047 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero junction field effect transistor provided with an Al | 12-29-2011 |
20110316048 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode. | 12-29-2011 |
20120001229 | Semiconductor Device and Method for Forming the Same - A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate, the second gate is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of source and drain regions, and parasitic capacitances. | 01-05-2012 |
20120007145 | ASYMMETRIC CHANNEL MOSFET - A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state. | 01-12-2012 |
20120007146 | METHOD FOR FORMING STRAINED LAYER WITH HIGH GE CONTENT ON SUBSTRATE AND SEMICONDUCTOR STRUCTURE - A semiconductor structure and a method for forming the same are provided. The semiconductor structure may comprise a substrate ( | 01-12-2012 |
20120007147 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor film having a heterojunction structure, for example a semiconductor film including a SiGe layer and a Si layer formed on the SiGe layer, impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer becomes higher than that in the upper, Si layer by exploiting the fact that there is a difference between the SiGe layer and the Si layer in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film | 01-12-2012 |
20120012893 | SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor transistor without variation in threshold voltage of an FET and a method of manufacturing the semiconductor transistor, the semiconductor transistor includes: a substrate; a first compound semiconductor layer formed above the substrate; a second compound semiconductor layer formed on the first compound semiconductor layer and having a bandgap larger than a bandgap of the first compound semiconductor layer; an oxygen-doped region formed by doping at least part of the second compound semiconductor layer with oxygen; a third compound semiconductor layer formed on the second compound semiconductor layer; a source electrode electrically connected to the first compound semiconductor layer; a drain electrode electrically connected to the first compound semiconductor layer; and a gate electrode formed on and in contact with the oxygen-doped region. | 01-19-2012 |
20120018780 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode. | 01-26-2012 |
20120018781 | MODULATION-DOPED MULTI-GATE DEVICES - Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film. | 01-26-2012 |
20120025267 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 02-02-2012 |
20120025268 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor. | 02-02-2012 |
20120032230 | METHOD OF FORMING STRAINED SEMICONDUCTOR CHANNEL AND SEMICONDUCTOR DEVICE - The present invention provides a method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. The present invention also provides a semiconductor device manufactured by this process. | 02-09-2012 |
20120032231 | MOS TRANSISTOR STRUCTURE WITH IN-SITU DOPED SOURCE AND DRAIN AND METHOD FOR FORMING THE SAME - A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element. | 02-09-2012 |
20120043585 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 02-23-2012 |
20120056245 | SEMICONDUCTOR DEVICES INCLUDING SILICIDE REGIONS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si—X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si—Y, where Y is a metal or metal alloy | 03-08-2012 |
20120056246 | INSULATED GATE FIELD EFFECT TRANSISTORS - An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced. | 03-08-2012 |
20120061728 | SEMICONDUCTOR ON INSULATOR (XOI) FOR HIGH PERFORMANCE FIELD EFFECT TRANSISTORS - Semiconductor-on-insulator (XOI) structures and methods of fabricating XOI structures are provided. Single-crystalline semiconductor is grown on a source substrate, patterned, and transferred onto a target substrate, such as a Si/SiO | 03-15-2012 |
20120080721 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure includes a recess disposed in a substrate, a non-doped epitaxial layer and a doped epitaxial layer. The non-doped epitaxial layer is disposed on the inner surface of the recess and substantially consists of Si and an epitaxial layer. The non-doped epitaxial layer has a sidewall and a bottom which together cover the inner surface. The bottom thickness is not greater than 120% of the sidewall thickness. The non-doped epitaxial layer and the doped epitaxial layer together fill up the recess. | 04-05-2012 |
20120080722 | METHOD FOR FORMING STRAINED SEMICONDUCTOR CHANNEL AND SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a SiGe relaxed layer on the semiconductor substrate; an NMOS transistor on the SiGe relaxed layer; and a PMOS transistor on the SiGe relaxed layer, in which the NMOS transistor includes a tensile strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer; and the PMOS transistor includes a compressive strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer. The loss of the strained semiconductor material can be avoided and meanwhile the stress in the channel can be better maintained. | 04-05-2012 |
20120080723 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME METHOD - A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates. | 04-05-2012 |
20120086048 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode. | 04-12-2012 |
20120091506 | Method and Structure for pFET Junction Profile With SiGe Channel - A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed. | 04-19-2012 |
20120091507 | STRUCTURE OF HETEROJUNCTION FIELD EFFECT TRANSISTOR AND A FABRICATION METHOD THEREOF - An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer. The fabrication method is a multiple selective etching process, which comprises steps of: etching the n type doped layer by using a first etching process to form a first indentation; etching first etching stop layer by using a second etching process to form a second indentation located under the first indentation; etching the tunneling layer by using a third etching process to form a third indentation located under the second indentation, wherein the said first, second and third indentations form a single gate groove, in which the gate electrode can form a Schottky contact with the Schottky capping layer that is made of a higher energy gap material. | 04-19-2012 |
20120112243 | Bipolar and FET Device Structure - A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. | 05-10-2012 |
20120126287 | COMPOUND SEMICONDUCTOR DEVICE HAVING INSULATION FILM WITH DIFFERENT FILM THICKNESSES BENEATH ELECTRODES - A compound semiconductor device includes a group-III nitride semiconductor layer; an insulation film located on the group-III nitride semiconductor layer; a drain electrode located in a position which is a first distance away from an upper surface of the group-III nitride semiconductor layer; a source electrode located in a position which is the first distance away from the upper surface of the group-III nitride semiconductor layer; a gate electrode located between the drain electrode and the source electrode; and a field plate electrode located between the drain electrode and the gate electrode at a position which is a second distance away from the upper surface of the group-III nitride semiconductor layer, the second distance is shorter than the first distance. | 05-24-2012 |
20120126288 | Semiconductor device and method of manufacturing the same - A semiconductor device having first and second stacks formed successively over a common substrate, in which the first stack that remains after removing the second stack comprises a field effect transistor, the second stack that is stacked over the first stack comprises a device different from the field effect transistor, and the first stack comprising the field effect transistor has an etching stopper layer that defines a stopping position of a recess formed in the first stack and comprises InGaP, a lower compound semiconductor layer that is disposed below a gate electrode disposed in the recess and comprises AlGaAs, and a spacer layer that is interposed between the etching stopper layer and the lower compound semiconductor layer for preventing phosphorus contained in the etching stopper layer from thermally diffusing as far as the lower compound semiconductor layer and chemically bonding with constituents elements of the lower compound semiconductor layer. | 05-24-2012 |
20120126289 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium. | 05-24-2012 |
20120126290 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region. | 05-24-2012 |
20120132957 | HIGH PERFORMANCE STRAINED SOURCE-DRAIN STRUCTURE AND METHOD OF FABRICATING THE SAME - A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour. | 05-31-2012 |
20120139006 | DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET - A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device. | 06-07-2012 |
20120139007 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si | 06-07-2012 |
20120146093 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer | 06-14-2012 |
20120153351 | Stress modulated group III-V semiconductor device and related method - According to one embodiment, a group III-V semiconductor device comprises a compositionally graded body disposed over a substrate and below a buffer layer supporting an active area of the group III-V semiconductor device. The compositionally graded body includes a first region applying compressive stress to the substrate. The compositionally graded body further includes a stress modulating region over the first region, where the stress modulating region applies tensile stress to the substrate. In one embodiment, a method for fabricating a group III-V semiconductor device comprises providing a substrate for the group III-V semiconductor device and forming a first region of a compositionally graded body over the substrate to apply compressive stress to the substrate. The method further comprises forming a stress modulating region of the compositionally graded body over the first region, where the stress modulating region applies tensile stress to the substrate. | 06-21-2012 |
20120153352 | HIGH INDIUM CONTENT TRANSISTOR CHANNELS - The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the formation of high mobility transistor channels from high indium content alloys, wherein the high indium content transistor channels are achieved with a barrier layer that can substantially lattice match with the high indium content transistor channel. | 06-21-2012 |
20120153353 | BURIED OXIDATION FOR ENHANCED MOBILITY - A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions. | 06-21-2012 |
20120153354 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP - When forming sophisticated transistors, for instance comprising high-k metal gate electrode structures, a significant material loss of an embedded strain-inducing semiconductor material may be compensated for, or at least significantly reduced, by performing a second epitaxial growth step after the incorporation of the drain and source extension dopant species. In this manner, superior strain conditions may be achieved, while also the required drain and source dopant profile may be implemented. | 06-21-2012 |
20120153355 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate. | 06-21-2012 |
20120161202 | JUNCTIONLESS ACCUMULATION-MODE DEVICES ON PROMINENT ARCHITECTURES, AND METHODS OF MAKING SAME - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. | 06-28-2012 |
20120161203 | Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation - In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration. | 06-28-2012 |
20120161204 | Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy - In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials. | 06-28-2012 |
20120168819 | Semiconductor pillar power MOS - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a multi-gate vertical MOS configuration with multi semiconductor pillars, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. Furthermore, due to its particular geometry, the parasitic resistances due to the source/drain junctions, are also drastically reduced with respect to standard CMOS technologies. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances. The novel structure does not require Silicon On Insulator technologies and can be built using the standard Bulk CMOS process technology. This characteristic improves the thermal properties of the device which are extremely important in power applications. | 07-05-2012 |
20120168820 | JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure. | 07-05-2012 |
20120168821 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate. | 07-05-2012 |
20120175678 | REPLACEMENT SPACER FOR TUNNEL FETS - A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess. | 07-12-2012 |
20120181578 | PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION - A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator. | 07-19-2012 |
20120187450 | STI SILICON NITRIDE CAP FOR FLAT FEOL TOPOLOGY - Transistor devices are formed with a nitride cap over STI regions during FEOL processing. Embodiments include forming a pad oxide layer on a substrate, forming an STI region in the substrate so that the top surface is level with the top surface of the pad oxide, forming a nitride cap on the STI region and on a portion of the pad oxide layer on each side of the STI region, implanting a dopant into the substrate, deglazing the nitride cap and pad oxide layer, removing the nitride cap, and removing the pad oxide layer. Embodiments include forming a silicon germanium channel (c-SiGe) in the substrate prior to deglazing the pad oxide layer. The nitride cap protects the STI regions and immediately adjacent area during processes that tend to degrade the STI oxide, thereby providing a substantially divot free substrate and an STI region with a zero step height for the subsequently deposited high-k dielectric and metal electrode. | 07-26-2012 |
20120187451 | SEMICONDUCTOR ELEMENT - According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped Al | 07-26-2012 |
20120187452 | SEMICONDUCTOR ELEMENT - According to one embodiment, the semiconductor element includes a first semiconductor layer. The first semiconductor layer contains Al | 07-26-2012 |
20120187453 | INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS - A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO | 07-26-2012 |
20120193678 | FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET - Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region. | 08-02-2012 |
20120193679 | HETEROJUNCTION TUNNELING FIELD EFFECT TRANSISTORS, AND METHODS FOR FABRICATING THE SAME - The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide. | 08-02-2012 |
20120193680 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 08-02-2012 |
20120199877 | MEMORY DEVICES WITH A CONNECTING REGION HAVING A BAND GAP LOWER THAN A BAND GAP OF A BODY REGION - Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation. | 08-09-2012 |
20120199878 | Drain Extended Field Effect Transistors and Methods of Formation Thereof - In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region. | 08-09-2012 |
20120199879 | METHOD OF FORMING AN INVERTED T SHAPED CHANNEL STRUCTURE FOR AN INVERTED T CHANNEL FIELD EFFECT TRANSISTOR DEVICE - A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. | 08-09-2012 |
20120199880 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - In order to solve a problem that, in an initial stage of film growth in a plasma CVD method, it is difficult to form a silicon layer which is excellent in crystallinity, provided is a semiconductor device, including: a substrate; a crystalline silicon layer; a titanium oxide layer containing titanium oxide as a main component; and a pair of electrodes electrically connected to the crystalline silicon layer, in which: the titanium oxide layer and the crystalline silicon layer are formed on the substrate in the mentioned order from the substrate side; and the titanium oxide layer and the crystalline silicon layer are formed in contact to each other. | 08-09-2012 |
20120205716 | Epitaxially Grown Extension Regions for Scaled CMOS Devices - Epitaxially grown extension regions are disclosed for scaled CMOS devices. Semiconductor devices are provided that comprise a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises at least a channel layer formed below the gate stack. One or more etched extension regions containing an epitaxially grown dopant are provided in the channel layer. | 08-16-2012 |
20120223364 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer. | 09-06-2012 |
20120228671 | STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME - A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a SiN stress cap layer covering the gate stack to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided. | 09-13-2012 |
20120228672 | METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE - The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET. | 09-13-2012 |
20120228673 | FIELD-EFFECT TRANSISTOR, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of In | 09-13-2012 |
20120228674 | SEMICONDUCTOR DEVICE, FIELD-EFFECT TRANSISTOR, AND ELECTRONIC DEVICE - Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. | 09-13-2012 |
20120241816 | Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material - When forming sophisticated P-channel transistors, the metal silicide agglomeration in a germanium-containing strain-inducing semiconductor alloy may be avoided or at least significantly reduced by incorporating a carbon and/or nitrogen species in a highly controllable manner. In some illustrative embodiments, the carbon species or nitrogen species is incorporated during the epitaxial growth process so as to form a surface layer of the strain-inducing semiconductor alloy with a desired nitrogen and/or carbon concentration and with a desired thickness without unduly affecting any other device areas. | 09-27-2012 |
20120241817 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a control electrode, a third semiconductor layer, first and second main electrodes. The second semiconductor layer is provided on the first semiconductor layer, and has a higher impurity concentration than the first semiconductor layer. The control electrode is provided inside a first trench with an insulating film interposed, the first trench reaching the first semiconductor layer from a front surface of the second semiconductor layer. The third semiconductor layer is provided inside a second trench and including Si | 09-27-2012 |
20120241818 | TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS - Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded. | 09-27-2012 |
20120248501 | SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer. | 10-04-2012 |
20120248502 | III-V FIELD EFFECT TRANSISTOR (FET) AND III-V SEMICONDUCTOR ON INSULATOR (IIIVOI) FET, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer. | 10-04-2012 |
20120248503 | SEMICONDUCTOR MEMORY CELL, DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect. | 10-04-2012 |
20120261718 | Method And Structure For Compound Semiconductor Contact - The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region. | 10-18-2012 |
20120261719 | HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures. | 10-18-2012 |
20120267683 | EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER - Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities. | 10-25-2012 |
20120267684 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer. | 10-25-2012 |
20120267685 | METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe - In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric. | 10-25-2012 |
20120280279 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 11-08-2012 |
20120292664 | Integrated Circuit (IC) Chip Having Both Metal and Silicon Gate Field Effect Transistors (FETs) and Method of Manufacture - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs. | 11-22-2012 |
20120299062 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 11-29-2012 |
20120305987 | LATERAL TRENCH MESFET - A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench. | 12-06-2012 |
20120305988 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate; a plurality of convex structures formed on the substrate, in which every two adjacent convex structures are separated by a cavity; a plurality of floated films, in which each floated film is formed between the every two adjacent convex structures and connected with tops of the every two adjacent convex structures, the floated films are partitioned into a plurality of sets, a channel layer is formed on a convex structure between the floated films in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and an isolation portion is set between two adjacent sets of floated films; and a gate stack formed on each channel layer. | 12-06-2012 |
20120305989 | METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS - A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor. | 12-06-2012 |
20120305990 | METHODS AND APPARATUS TO REDUCE LAYOUT BASED STRAIN VARIATIONS IN NON-PLANAR TRANSISTOR STRUCTURES - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies. | 12-06-2012 |
20120313143 | HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT - A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction. | 12-13-2012 |
20120313144 | RECESSED GATE FIELD EFFECT TRANSISTOR - A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode. | 12-13-2012 |
20120319166 | TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE - A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base. | 12-20-2012 |
20120319167 | Mask-less and Implant Free Formation of Complementary Tunnel Field Effect Transistors - A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric. | 12-20-2012 |
20120319168 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method therefor includes a Σ-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a Σ-shaped recess. | 12-20-2012 |
20130009209 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer. | 01-10-2013 |
20130009210 | METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCES - A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided. | 01-10-2013 |
20130009211 | SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE - Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects. | 01-10-2013 |
20130015500 | SEMICONDUCTOR DEVICEAANM IZUMIDA; TakashiAACI KanagawaAACO JPAAGP IZUMIDA; Takashi Kanagawa JPAANM MIYATA; ToshitakaAACI KanagawaAACO JPAAGP MIYATA; Toshitaka Kanagawa JP - According to one embodiment, a semiconductor device includes a semiconductor protrusion formed on a semiconductor substrate, a source/drain layer provided in a vertical direction of the semiconductor protrusion, a gate electrode provided on a side surface of the semiconductor protrusion through a gate insulating film, and a channel region provided on the side surface of the semiconductor protrusion. The potential height in the channel region is different between the drain layer side and the source layer side. | 01-17-2013 |
20130020613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a patterned stacked structure formed on a semiconductor substrate, the stacked structure comprising a silicon-containing semiconductor layer overlaying the semiconductor substrate, a gate dielectric layer overlaying the silicon-containing semiconductor layer and a gate layer overlaying the gate dielectric layer; and a doped epitaxial semiconductor layer on opposing sides of the silicon-containing semiconductor layer forming raised source/drain extension regions. Optionally, the silicon-containing semiconductor layer may be used as a channel region. According to this disclosure, the source/drain extension regions can be advantageously made to have a shallow junction depth (or a small thickness) and a high doping concentration. | 01-24-2013 |
20130026539 | REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor. | 01-31-2013 |
20130026540 | METHODS AND APPARATUS FOR FORMING SEMICONDUCTOR STRUCTURES - Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer. | 01-31-2013 |
20130032859 | EPITAXIAL EXTENSION CMOS TRANSISTOR - A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein. | 02-07-2013 |
20130043505 | APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed. | 02-21-2013 |
20130043506 | Fin-FET and Method of Forming the Same - A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure. | 02-21-2013 |
20130043507 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 02-21-2013 |
20130049068 | FINFET DEVICE HAVING A CHANNEL DEFINED IN A DIAMOND-LIKE SHAPE SEMICONDUCTOR STRUCTURE - The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions. | 02-28-2013 |
20130056796 | Novel Method to Increase Breakdown Voltage of Semiconductor Devices - Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN. | 03-07-2013 |
20130069111 | STRAINED SEMICONDUCTOR DEVICES HAVING ASYMMETRICAL HETEROJUNCTION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate. | 03-21-2013 |
20130069112 | SRAM CELL AND METHOD FOR MANUFACTURING THE SAME - A SRAM cell and a method for manufacturing the same are disclosed. In one embodiment, the SRAM cell may comprise a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first FinFET may comprise a first fin which is formed in a semiconductor layer provided on the substrate and abuts the semiconductor layer, and the second FinFET may comprise a second fin which is formed in the semiconductor layer and abuts the semiconductor layer. The semiconductor layer may comprise a plurality of semiconductor sub-layers. The first and second fins can comprise different number of the semiconductor sub-layers and have different heights from each other. | 03-21-2013 |
20130069113 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer. | 03-21-2013 |
20130069114 | High-Voltage Normally-Off Field Effect Transistor - A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel. | 03-21-2013 |
20130069115 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a nitride semiconductor multilayer structure formed on a substrate, a source electrode, a drain electrode, a gate electrode, an insulating film formed on the nitride semiconductor multilayer structure, and a field plate formed on and in contact with the insulating film, and having an end located between the gate electrode and the drain electrode. The insulating film includes a first film, and a second film having a dielectric breakdown voltage lower than that of the first film, and a thin film portion formed between the gate electrode and the drain electrode is formed in the insulating film. The field plate covers the thin film portion, and is connected to the source electrode in an opening. | 03-21-2013 |
20130082304 | FinFET Device and Method Of Manufacturing Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure. | 04-04-2013 |
20130087832 | Tucked Active Region Without Dummy Poly For Performance Boost and Variation Reduction - In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided. | 04-11-2013 |
20130087833 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising: a substrate, a channel layer epitaxially grown in the substrate, a gate stack structure on the channel layer, gate spacers on both sides of the gate stack structure, and source/drain areas on both sides of the channel layer in the substrate, characterized in that the carrier mobility of the channel layer is higher than that of the substrate. In accordance with the semiconductor device and the method of manufacturing the same in the present invention, forming the device channel region by filling the trench with epitaxial high-mobility materials in a gate last process can enhance the carrier mobility in the channel region, thereby the device response speed is substantially improved and the device performance is greatly enhanced. Furthermore, traditional materials for a substrate are still used for the source/drain areas of the device to facilitate usage of a gate last process, thereby enhancing the performance while reducing the cost at the same time. | 04-11-2013 |
20130105861 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER | 05-02-2013 |
20130105862 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 05-02-2013 |
20130113019 | SEMICONDUCTOR DEVICE WITH REDUCED THRESHOLD VARIABILITY HAVING A THRESHOLD ADJUSTING SEMICONDUCTOR ALLOY IN THE DEVICE ACTIVE REGION - Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material. | 05-09-2013 |
20130126942 | SEMICONDUCTOR DEVICE - A low-loss GaN-based semiconductor device is provided. | 05-23-2013 |
20130134481 | Split-Channel Transistor and Methods for Forming the Same - A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel. | 05-30-2013 |
20130140605 | GaN high voltage HFET with passivation plus gate dielectric multilayer structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device. | 06-06-2013 |
20130146943 | IN SITU GROWN GATE DIELECTRIC AND FIELD PLATE DIELECTRIC - Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode. | 06-13-2013 |
20130146944 | SEMICONDUCTOR DEVICE INCLUDING STEPPED GATE ELECTRODE AND FABRICATION METHOD THEREOF - Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer. | 06-13-2013 |
20130146945 | FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. | 06-13-2013 |
20130146946 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME - A semiconductor device includes: a buffer layer provided on a substrate and made of a group III-V nitride semiconductor; a first semiconductor layer provided on the buffer layer and made of a group III-V nitride semiconductor; a second semiconductor layer provided on the first semiconductor layer and made of a group III-V nitride semiconductor; a back electrode provided on a back surface of the substrate and connected to a ground; a source electrode and a drain electrode provided on the second semiconductor layer so as to be apart from each other; a gate electrode provided on the second semiconductor layer; and a plug which passes through the second semiconductor layer, the first semiconductor layer, and the buffer layer, and reaches at least the substrate to electrically connect the source electrode and the back electrode. | 06-13-2013 |
20130153964 | FETs with Hybrid Channel Materials - Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET. | 06-20-2013 |
20130153965 | STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area. | 06-20-2013 |
20130153966 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer made of an Al | 06-20-2013 |
20130161692 | SHIELD WRAP FOR A HETEROSTRUCTURE FIELD EFFECT TRANSISTOR - Devices are disclosed for providing heterojunction field effect transistor (HFETs) having improved performance and/or reduced noise generation. A gate electrode is over a portion of the active region and is configured to modulate a conduction channel in the active region of an HFET. The active region is in a semiconductor film between a source electrode and a drain electrode. A first passivation film is over the active region. An encapsulation film is over the first passivation film. A first metal pattern on the encapsulation film includes a shield wrap over the majority of the active region and is electrically connected to the source electrode | 06-27-2013 |
20130161693 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 06-27-2013 |
20130161694 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 06-27-2013 |
20130161695 | REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY - The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability. | 06-27-2013 |
20130161696 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHODS FOR MANUFACTURING THEREOF - A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel. | 06-27-2013 |
20130161697 | REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN - A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor. | 06-27-2013 |
20130168736 | METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF - A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors. | 07-04-2013 |
20130175578 | IO ESD Device and Methods for Forming the Same - A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode. | 07-11-2013 |
20130175579 | TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer. | 07-11-2013 |
20130193481 | FIELD EFFECT TRANSISTOR AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region. | 08-01-2013 |
20130193482 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 08-01-2013 |
20130193483 | Mosfet Structures Having Compressively Strained Silicon Channel - MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel. | 08-01-2013 |
20130193484 | FIELD-EFFECT TRANSISTOR ON A SELF-ASSEMBLED SEMICONDUCTOR WELL - A device including at least one transistor on a substrate in a first semiconductor material, each transistor including a gate electrode as a gate, two conductor electrodes, an island in a second semiconductor material inlaid in the substrate, defining a region capable of forming a channel as a channel region, and an insulating layer separating the gate from the two electrodes and the channel region. The channel region is inside the island and is in direct electrical contact with at least one of the two conductor electrodes. | 08-01-2013 |
20130200434 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. | 08-08-2013 |
20130207162 | HIGH PERFORMANCE MULTI-FINGER STRAINED SILICON GERMANIUM CHANNEL PFET AND METHOD OF FABRICATION - A field effect transistor and method of fabrication are provided. The field effect transistor comprises a plurality of elongated uniaxially-strained SiGe regions disposed on a silicon substrate, oriented such that they are in parallel to the direction of flow of electrical carriers in the channel. The elongated uniaxially-strained SiGe regions are oriented perpendicular to, and traverse through the transistor gate. | 08-15-2013 |
20130214329 | TRANSISTOR AND METHOD FOR FORMING THE SAME - A transistor and a method for forming the transistor are provided. The transistor can be formed over a substrate including a first region and second regions on opposite sides of the first region. On the substrate, a first SiGe layer can be formed, followed by forming a first silicon layer on the first SiGe layer and forming a second SiGe layer on the first silicon layer. The second SiGe layer and the first silicon layer within the second regions are removed. The first silicon layer within the first region is removed to form a cavity such that the second SiGe layer is floated. An isolating layer is formed in the cavity. Second silicon layers are formed in the second regions. A gate structure is formed on the second SiGe layer within the first region and the second silicon layers are doped to form a source and a drain. | 08-22-2013 |
20130221407 | MULTI-GATE TRANSISTOR DEVICE - A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other. | 08-29-2013 |
20130221408 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, PROTECTIVE ELEMENT, AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an epitaxial substrate formed by stacking a plurality of kinds of semiconductors over one semiconductor substrate by epitaxial growth; a field effect transistor of a first conductivity type formed in a first region; a field effect transistor of a second conductivity type formed in a second region; and a protective element formed in a third region. The protective element includes: a first stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction; and a second stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction. The protective element has two PN junctions on a current path formed between an upper end of the first stacking structure and an upper end of the second stacking structure via a base part of the first stacking structure and the second stacking structure. | 08-29-2013 |
20130228826 | MOS Devices with Modulated Performance and Methods for Forming the Same - A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance. | 09-05-2013 |
20130234205 | NICKELIDE SOURCE/DRAIN STRUCTURES FOR CMOS TRANSISTORS - A nickelide material with reduced resistivity is provided as source/drain contact surfaces in both NMOS and PMOS technology. The nickelide material layer may be a ternary material such as NiInAs, and may be formed from a binary material previously formed in the source/drain regions. The binary material may be the channel material or it may be an epitaxial layer formed over the channel material. The same ternary nickelide material may be used as the source/drain contact surface in both NMOS and PMOS transistors. Various binary or ternary channel materials may be used for the NMOS transistors and for the PMOS transistors. | 09-12-2013 |
20130234206 | MEMORY DEVICES WITH A CONNECTING REGION HAVING A BAND GAP LOWER THAN A BAND GAP OF A BODY REGION - Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation. | 09-12-2013 |
20130248928 | SEMICONDUCTOR DEVICE HAVING NITRIDE LAYERS - According to one embodiment, a semiconductor device having a semiconductor substrate, first to fourth semiconductor layers of nitride, first to third electrodes and a gate electrode is provided. The first semiconductor layer is provided directly on the semiconductor substrate or on the same via a buffer layer. The second semiconductor layer is provided so as to be spaced apart from the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer and has a band gap wider than that of the second semiconductor layer. The fourth semiconductor layer insulates the first and second semiconductor layers. The first electrode forms an ohmic junction with the first to the third semiconductor layers. The second electrode is provided on the third semiconductor layer. The gate electrode is provided between the first and the second electrodes. The third electrode forms a Schottky junction with the first semiconductor layer. | 09-26-2013 |
20130248929 | Reducing Source/Drain Resistance of III-V Based Transistors - An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode. | 09-26-2013 |
20130248930 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. | 09-26-2013 |
20130256753 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer. | 10-03-2013 |
20130270607 | Semiconductor Device Channel System and Method - A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not. | 10-17-2013 |
20130285117 | CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION - A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs. | 10-31-2013 |
20130285118 | CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION - A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs. | 10-31-2013 |
20130299873 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED GATE METALLIZATION - A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region. | 11-14-2013 |
20130299874 | TMAH RECESS FOR SILICON GERMANIUM IN POSITIVE CHANNEL REGION FOR CMOS DEVICE - CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region. | 11-14-2013 |
20130299875 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer. | 11-14-2013 |
20130299876 | Method For Improving Selectivity Of EPI Process - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 11-14-2013 |
20130299877 | Integrated III-Nitride and Silicon Device - A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body. | 11-14-2013 |
20130307025 | TRANSISTOR-BASED APPARATUSES, SYSTEMS AND METHODS - Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions. | 11-21-2013 |
20130313609 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a nitride semiconductor device having an excellent boundary between a nitride semiconductor and a gate insulating film, resulting in improved device characteristics, and a manufacturing method therefor. The nitride semiconductor device includes: an electron transport layer made of a nitride semiconductor; an electron supply layer layered on the electron transport layer, the electron supply layer being made of a nitride semiconductor including Al and having an Al composition different from that of the electron transport layer; a source electrode and a drain electrode formed on the electron supply layer with a gap therebetween; a gate insulating film covering the surface of the electron supply layer between the source electrode and the drain electrode; a passivation film covering a surface of the gate insulating film and having an opening between the source electrode and the drain electrode; and a gate electrode having a main gate body in the opening facing the electron supply layer through the gate insulating film. | 11-28-2013 |
20130313610 | SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH - Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. | 11-28-2013 |
20130320400 | HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed. | 12-05-2013 |
20130320401 | Mixed Orientation Semiconductor Device and Method - A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer. | 12-05-2013 |
20130334571 | EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM - A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate. | 12-19-2013 |
20130334572 | JUNCTIONLESS ACCUMULATION-MODE DEVICES ON DECOUPLED PROMINENT ARCHITECTURES - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. | 12-19-2013 |
20130341677 | GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS - A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer. | 12-26-2013 |
20130341678 | Semiconductor Device with Selectively Etched Surface Passivation - A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel. | 12-26-2013 |
20130341679 | Semiconductor Device with Selectively Etched Surface Passivation - A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer. | 12-26-2013 |
20130341680 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a stacked body, a source electrode, a drain electrode, a gate electrode, a dielectric layer and a silicon nitride layer. The stacked layer has a heterojunction made of a nitride semiconductor. The source and drain electrodes are provided on a surface of the stacked body. The gate electrode is provided on the surface of the stacked body between the source and the drain electrodes, and has a field plate portion. The dielectric layer is provided so as to cover an intersection line of a first side surface of the gate electrode and the surface of the stacked body. The silicon nitride layer is provided so as to cover a region between the source electrode and the gate electrode and a region between the dielectric layer and the drain electrode. The field plate portion protrudes from the first side surface. | 12-26-2013 |
20140001515 | STATIC DISCHARGE SYSTEM | 01-02-2014 |
20140015009 | TUNNEL TRANSISTOR WITH HIGH CURRENT BY BIPOLAR AMPLIFICATION - A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the first zone. | 01-16-2014 |
20140015010 | Drain Extended Field Effect Transistors and Methods of Formation Thereof - In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region. | 01-16-2014 |
20140027816 | HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS - Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface. | 01-30-2014 |
20140027817 | HYBRID TRANSISTOR - A hybrid transistor ( | 01-30-2014 |
20140027818 | Gate Recessed FDSOI Transistor with Sandwich of Active and Etch Control Layers - The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel. | 01-30-2014 |
20140035000 | Source and Drain Doping Profile Control Employing Carbon-Doped Semiconductor Material - Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor. | 02-06-2014 |
20140035001 | COMPOUND SEMICONDUCTOR STRUCTURE - A semiconductor structure ( | 02-06-2014 |
20140035002 | HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE - Semiconductor regions are alternately arranged in a parallel pn layer in which an n-type region and a p-type region are alternately arranged parallel to the main surface of a semiconductor substrate. Pitch between n drift region and p partition region of a second parallel pn layer in an edge termination region is two thirds of pitch between n drift region and p partition region of a first parallel pn layer in an active region. At boundaries between main SJ cells and fine SJ cells at four corners of the semiconductor substrate having rectangular shape in plan view, ends of two pitches of main SJ cells face the ends of three pitches of fine SJ cells. In this way, it is possible to reduce the influence of a process variation and thus reduce mutual diffusion between n drift region and p partition region of the fine SJ cell. | 02-06-2014 |
20140042494 | METAL NANOPARTICLE MONOLAYER - This disclosure generally relates to a device with a monolayer of metal nanoparticles and a method for making the same. The nanoparticles of the monolayer of metal nanoparticles are grouped in an ultrahigh density with an average distance between each neighboring metal nanoparticle less than or equal to about 3 nanometers. The monolayer can be self-assembled on a substrate to facilitate controllable voltage shifts within the device. | 02-13-2014 |
20140048849 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 02-20-2014 |
20140054648 | NEEDLE-SHAPED PROFILE FINFET DEVICE - Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel. | 02-27-2014 |
20140054649 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SEMICONDUCTOR DEVICES INCLUDING A RETROGRADE WELL - Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon. | 02-27-2014 |
20140054650 | Method for Increasing Fin Density - The present disclosure is directed to a method of manufacturing a FinFET structure in which at least one initial set of fin structures is formed by photolithographic processes, followed by forming an additional fin structure by epitaxial growth of a semiconductor material between the initial set of fin structures. The method allows for formation of FinFET structures having increased fin density. | 02-27-2014 |
20140061722 | Transistors, Semiconductor Devices, and Methods of Manufacture Thereof - Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V material of the sacrificial gate material to form a gate of the transistor comprising a Me-III-V compound material. | 03-06-2014 |
20140061723 | MOS TRANSISTOR - A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed. | 03-06-2014 |
20140070276 | Source/Drain Re-Growth for Manufacturing III-V Based Transistors - A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer. | 03-13-2014 |
20140070277 | EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM - A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350 C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate. | 03-13-2014 |
20140077264 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gates on a surface of a substrate, forming sidewalls on side surfaces of the gates, forming a Sigma-shaped recess in the substrate between adjacent gates, forming a SiGe seed layer on an inner surface of the Sigma-shaped recess, forming bulk SiGe doped with boron on a surface of the SiGe seed layer, and filling the Sigma-shaped recess with the boron-doped bulk SiGe, forming a first recess by etching a portion of the SiGe seed layer and the boron-doped bulk SiGe in the Sigma-shaped recess, and forming a SiGe regeneration layer in the first recess beneath the surface of the substrate, wherein the SiGe regeneration layer is doped with boron, and the boron-doped SiGe regeneration layer has a higher concentration of boron than the SiGe seed layer or the boron-doped bulk SiGe. | 03-20-2014 |
20140077265 | Gateless Switch with Capacitively-Coupled Contacts - A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the conducting channel. A control contact is located outside of a region between the input and output contacts, and can be used to adjust the switch between on and off operating states. The switch can be implemented as a radio frequency switch in a circuit. | 03-20-2014 |
20140084342 | STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES - Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer. | 03-27-2014 |
20140084343 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK - Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode. | 03-27-2014 |
20140097468 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer ( | 04-10-2014 |
20140103395 | SEMICONDUCTOR ELEMENT - According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped Al | 04-17-2014 |
20140103396 | STRAIN-INDUCING SEMICONDUCTOR REGIONS - A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate. | 04-17-2014 |
20140103397 | TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES - Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 04-17-2014 |
20140110755 | Apparatus and Method for Forming Semiconductor Contacts - A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure. | 04-24-2014 |
20140110756 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer. | 04-24-2014 |
20140110757 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME METHOD - A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates. | 04-24-2014 |
20140117409 | METHOD AND STRUCTURE FOR BODY CONTACTED FET WITH REDUCED BODY RESISTANCE AND SOURCE TO DRAIN CONTACT LEAKAGE - A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a bridge gate portion and an abutting gate portion, the bridge gate portion comprising a multilayer first gate stack and the gate portion comprising a multilayer second gate stack comprising the gate dielectric layer on the semiconductor body; first and second source/drains formed in the switching region on opposite sides of the channel; and wherein a first work function difference between the bridge portion and the body contact region is different from a second work function difference between the gate portion and the channel region. | 05-01-2014 |
20140131770 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 05-15-2014 |
20140138744 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS - Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion. | 05-22-2014 |
20140138745 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region. | 05-22-2014 |
20140145242 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 05-29-2014 |
20140151746 | FINFET DEVICE WITH ISOLATED CHANNEL - Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate. | 06-05-2014 |
20140159114 | VERTICAL NANOWIRE BASED HETERO-STRUCTURE SPLIT GATE MEMORY - A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell. | 06-12-2014 |
20140167110 | PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION - Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions. | 06-19-2014 |
20140175513 | Structure And Method For Integrated Devices On Different Substartes With Interfacial Engineering - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium Si | 06-26-2014 |
20140183600 | NOVEL FIN STRUCTURE OF FINFET - A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature. | 07-03-2014 |
20140197455 | SEMICONDUCTOR SUBSTRUCTURE HAVING ELEVATED STRAIN MATERIAL-SIDEWALL INTERFACE AND METHOD OF MAKING THE SAME - A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate. | 07-17-2014 |
20140197456 | Semiconductor Device and Fabricating the Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion. | 07-17-2014 |
20140197457 | FinFET Device and Method of Fabricating Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure. | 07-17-2014 |
20140197458 | FinFET Device and Method of Fabricating Same - An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions. | 07-17-2014 |
20140203327 | DEEP GATE-ALL-AROUND SEMICONDUCTOR DEVICE HAVING GERMANIUM OR GROUP III-V ACTIVE LAYER - Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack. | 07-24-2014 |
20140203328 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED GATE METALLIZATION - A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region. | 07-24-2014 |
20140209977 | DOPED AND STRAINED FLEXIBLE THIN-FILM TRANSISTORS - Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer. | 07-31-2014 |
20140209978 | DEVICES WITH STRAINED SOURCE/DRAIN STRUCTURES - A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions. | 07-31-2014 |
20140217468 | PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided. | 08-07-2014 |
20140217469 | Ga2O3 SEMICONDUCTOR ELEMENT | 08-07-2014 |
20140217470 | Ga2O3 SEMICONDUCTOR ELEMENT - Provided is a high-quality Ga | 08-07-2014 |
20140217471 | Ga2O3 SEMICONDUCTOR ELEMENT - Provided is a high-quality Ga | 08-07-2014 |
20140231872 | METHOD FOR INDUCING STRAIN IN FINFET CHANNELS - FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone. | 08-21-2014 |
20140239346 | MISHFET AND SCHOTTKY DEVICE INTEGRATION - A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate. | 08-28-2014 |
20140239347 | Structure and Method for Defect Passivation To Reduce Junction Leakage For FinFET Device - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species. | 08-28-2014 |
20140246697 | Semiconductor Device with Charge Compensation Structure - A semiconductor device is provided. The semiconductor device includes a semiconductor body having a main surface. In a vertical cross-section which is substantially orthogonal to the main surface the semiconductor body includes a vertical trench, an n-type silicon semiconductor region, and two p-type silicon semiconductor regions each of which adjoins the n-type silicon semiconductor region and is arranged between the n-type silicon semiconductor region and the main surface. The vertical trench extends from the main surface at least partially into the n-type silicon semiconductor region and includes a compound semiconductor region which includes silicon and germanium and is arranged between the two p-type silicon semiconductor regions. The compound semiconductor region and the two p-type silicon semiconductor regions include n-type dopants and p-type dopants. An integrated concentration of the n-type dopants of the compound semiconductor region is larger than an integrated concentration of the p-type dopants of the compound semiconductor region. | 09-04-2014 |
20140246698 | CHANNEL SiGe REMOVAL FROM PFET SOURCE/DRAIN REGION FOR IMPROVED SILICIDE FORMATION IN HKMG TECHNOLOGIES WITHOUT EMBEDDED SiGe - When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer. | 09-04-2014 |
20140252412 | Strained and Uniform Doping Technique for FINFETs - The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration of less than approximately 1% aids in control of the phosphorus dopant diffusion. Phosphorus dopant diffusion is also controlled by an anneal step which promotes uniform doping through both source and drain, as well as lightly-doped drain regions. | 09-11-2014 |
20140252413 | SILICON-GERMANIUM FINS AND SILICON FINS ON A BULK SUBSTRATE - A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin. | 09-11-2014 |
20140252414 | Passivated III-V or Ge Fin-Shaped Field Effect Transistor - A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device. | 09-11-2014 |
20140264443 | SIGE Surface Passivation by Germanium Cap - The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within a semiconductor body at a location between a source region and a drain region. A germanium cap layer is disposed onto the channel layer. A gate dielectric layer is separated from the channel layer by the germanium cap layer, and a gate region is disposed above the gate dielectric layer. Separating the gate dielectric layer from the channel layer allows for the germanium cap layer to prevent diffusion of atoms from the channel layer into the gate dielectric layer, thereby provide for a low interface trap density. | 09-18-2014 |
20140264444 | STRESS-ENHANCING SELECTIVE EPITAXIAL DEPOSITION OF EMBEDDED SOURCE AND DRAIN REGIONS - Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation (STI) spacer is formed on sidewalls of the shallow trench isolation structure around the periphery of the active area. After formation of a gate stack structure and a gate spacer, trenches are formed such that sidewalls of the trenches are vertically coincident with sidewalls of the gate spacer and the STI spacer. Epitaxial semiconductor material can be deposited into the trenches by selective epitaxy to form an embedded source region and an embedded drain region. Because all surfaces of the trenches are semiconductor surfaces, the entire trenches can be filled with the epitaxial semiconductor material, thereby enabling lateral confinement of stress within a channel region of a field effect transistor. | 09-18-2014 |
20140264445 | SOURCE/DRAIN STRUCTURE OF SEMICONDUCTOR DEVICE - The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface. | 09-18-2014 |
20140264446 | III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. | 09-18-2014 |
20140264447 | APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES - Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed. | 09-18-2014 |
20140284661 | MONOLITHIC INTEGRATED CIRCUIT (MMIC) STRUCTURE AND METHOD FOR FORMING SUCH STRUCTURE - A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer. | 09-25-2014 |
20140291727 | METHOD FOR FORMING SEMICONDUCTOR GATE STRUCTURE AND SEMICONDUCTOR GATE STRUCTURE - A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnO | 10-02-2014 |
20140299918 | SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR APPARATUS USING THE SAME AND FABRICATION METHOD THEREOF - A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity doping region. | 10-09-2014 |
20140299919 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask. | 10-09-2014 |
20140306269 | VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure. | 10-16-2014 |
20140312387 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a base layer of a group III-V compound, a channel layer disposed on the base layer and including a group IV element, a nitride layer disposed on the channel layer, a gate insulation layer disposed on the nitride layer and a gate electrode disposed on the gate insulation layer. The concentration of nitrogen atoms existing at a first interface between the nitride layer and the gate insulation layer is higher than that existing at a second interface between the nitride layer and the channel layer. | 10-23-2014 |
20140312388 | Apparatus and Method for Forming Semiconductor Contacts - A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure. | 10-23-2014 |
20140312389 | Reacted Conductive Gate Electrodes and Methods of Making the Same - A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material. | 10-23-2014 |
20140319581 | High Performance Strained Source-Drain Structure and Method of Fabricating the Same - A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour. | 10-30-2014 |
20140327044 | METHOD TO MAKE DUAL MATERIAL FINFET ON SAME SUBSTRATE - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure. | 11-06-2014 |
20140327045 | METHOD TO MAKE DUAL MATERIAL FINFET ON SAME SUBSTRATE - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure. | 11-06-2014 |
20140327046 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 11-06-2014 |
20140332851 | REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. | 11-13-2014 |
20140332852 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK - Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode. | 11-13-2014 |
20140353716 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE - A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins. | 12-04-2014 |
20140353717 | SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION - An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate. | 12-04-2014 |
20140353718 | SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON-GERMANIUM REGION - An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region. | 12-04-2014 |
20140353719 | Semiconductor Devices and Fabricating Methods Thereof - Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer. | 12-04-2014 |
20140353720 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode. | 12-04-2014 |
20140353721 | BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER - A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height. | 12-04-2014 |
20140361338 | REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins. | 12-11-2014 |
20140361339 | PMOS TRANSISTORS AND FABRICATION METHODS THEREOF - A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method includes forming sigma shape trenches in the semiconductor substrate at sides of the gate structures; and forming SiGe structures with a surface protruding from the surface of the semiconductor substrate in the sigma shape trenches. Further, the method also includes removing the sidewall spacers and a portion of the protection layer; and forming lightly doped drain regions in the semiconductor substrate at both sides of the gate structures. | 12-11-2014 |
20140361340 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. | 12-11-2014 |
20140374799 | FIN TUNNEL FIELD EFFECT TRANSISTOR (FET) - A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided. | 12-25-2014 |
20140374800 | OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin. | 12-25-2014 |
20150008484 | HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS - Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface. | 01-08-2015 |
20150014746 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE - A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a second source terminal of the power semiconductor chip. As a result, a gate drive path is separated from the path through which the main current flows, and therefore, the influence of induced electromotive force which is generated due to source parasitic inductance, on a gate-source voltage, is reduced. | 01-15-2015 |
20150021662 | III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS - A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers. | 01-22-2015 |
20150021663 | FINFET WITH INSULATOR UNDER CHANNEL - A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes. | 01-22-2015 |
20150021664 | Lateral/Vertical Semiconductor Device with Embedded Isolator - A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface. | 01-22-2015 |
20150028387 | III-V FET Device with Overlapped Extension Regions Using Gate Last - A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a gate last process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having at least one layer; forming a doped contact layer on the III-V compound semiconductor-containing heterostructure; and forming a gate structure having a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the doped contact layer. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure. | 01-29-2015 |
20150028388 | III-V Device with Overlapped Extension Regions Using Replacement Gate - A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure. | 01-29-2015 |
20150028389 | SEMICONDUCTOR DEVICES COMPRISING A FIN - A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the first semiconductive material; a first insulating material disposed around and lining the second semiconductive material; a conductive material disposed around the first insulating material; and a second insulating material disposed between the oxide of the first semiconductive material and a portion of the conductive material facing the workpiece, the second insulating material further lining sidewalls of the conductive material. | 01-29-2015 |
20150041855 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other. The silicon cap simultaneously surrounds the epitaxial structures. | 02-12-2015 |
20150041856 | Compound Semiconductor Integrated Circuit and Method to Fabricate Same - A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. | 02-12-2015 |
20150041857 | SEMICONDUCTOR STRUCTURE HAVING STRESSOR - A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate. | 02-12-2015 |
20150041858 | 3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT - A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region. | 02-12-2015 |
20150048419 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the channel layer, a trench passing through the barrier layer as far as a midway of the channel layer, and a gate electrode disposed byway of a gate insulation film in the inside of the trench. Then, the end of the bottom of the trench is in a rounded shape and the gate insulation film in contact with the end of the bottom of the trench is in a rounded shape. By providing the end of the bottom of the trench with a roundness as described above, a thickness of the gate insulation film situated between the end of the bottom of the gate electrode and the end of the bottom of the trench can be decreased. Thus, the channel is formed also at the end of the bottom of the trench to reduce the resistance of the channel. | 02-19-2015 |
20150054031 | TIN DOPED III-V MATERIAL CONTACTS - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures. | 02-26-2015 |
20150054032 | METHODS FOR MAKING A SEMICONDUCTOR DEVICE WITH SHAPED SOURCE AND DRAIN RECESSES AND RELATED DEVICES - A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack. | 02-26-2015 |
20150054033 | FINFET WITH SELF-ALIGNED PUNCHTHROUGH STOPPER - A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures. | 02-26-2015 |
20150060943 | NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATING THE SAME - A method of fabricating a nitride-based transistor includes sequentially forming a first nitride-based semiconductor layer doped with first type dopant, a second nitride-based semiconductor layer doped with at least one of a second type dopant, and a third nitride-based semiconductor layer doped with at least one of the first type dopants. A first trench is formed to penetrate the third and second nitride-based semiconductor layers and to extend into the first nitride-based semiconductor layer. A fourth nitride-based semiconductor layer doped with the first type dopants is formed to fill the first trench. A second trench is formed in the fourth nitride-based semiconductor layer. A gate electrode is formed in the second trench. A source electrode is formed to be electrically connected to at least one of the third and fourth nitride-based semiconductor layers, and a drain electrode is formed to be electrically connected to the first nitride-based semiconductor layer. | 03-05-2015 |
20150060944 | DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE - A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices. | 03-05-2015 |
20150060945 | TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM - Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm | 03-05-2015 |
20150069466 | STRAINED SOURCE AND DRAIN (SSD) STRUCTURE AND METHOD FOR FORMING THE SAME - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers. | 03-12-2015 |
20150069467 | DELTA DOPING LAYER IN MOSFET SOURCE/DRAIN REGION - A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer. | 03-12-2015 |
20150076561 | SILICON-ON-NOTHING FINFETS - A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to an un-doped layer of substantially similar composition. The doped sacrificial layer thickness may be between 10 nm and 250 nm and may be carbon doped silicon-germanium. The thicker sacrificial layer allows for a thicker insulator so as to provide adequate electrical isolation between the fin and the substrate. During formation of the void, the fin may be supported by a dummy gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the doped sacrificial layer. | 03-19-2015 |
20150084095 | METHOD FOR PRODUCING A TRANSISTOR - The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended to produce a conduction channel of the transistor, and a second layer of a second semiconductor material situated on the first layer and intended to at least partly produce the source and drain electrodes of the transistor, the formation of a mask defining a cavity of a gate pattern and the creation of lateral recesses at the periphery of the gate pattern in the second layer and under the mask by an isotropic etching of the second material, and in that it comprises a filling of the lateral recesses with a dielectric material so as to form gate spacers therein. | 03-26-2015 |
20150084096 | FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS - A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects. | 03-26-2015 |
20150091058 | VERTICAL TRANSISTOR DEVICES FOR EMBEDDED MEMORY AND LOGIC TECHNOLOGIES - Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate. | 04-02-2015 |
20150091059 | PROCESS FOR FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR (FinFET) STRUCTURE AND PRODUCT THEREOF - A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer. | 04-02-2015 |
20150097212 | SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS - A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed. | 04-09-2015 |
20150102386 | Passivated and Faceted for Fin Field Effect Transistor - A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed. | 04-16-2015 |
20150108544 | Fin Spacer Protected Source and Drain Regions in FinFETs - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The integrated circuit device further includes a gate stack on a top surface and sidewalls of the semiconductor fin, and a semiconductor region connected to an end of the semiconductor fin. The semiconductor region includes a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces, and a second semiconductor region underlying the first semiconductor region. The second semiconductor region has a higher germanium concentration than the first semiconductor region. A fin spacer is on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions. | 04-23-2015 |
20150108545 | FIN FIELD EFFECT TRANSISTORS INCLUDING MULTIPLE LATTICE CONSTANTS AND METHODS OF FABRICATING THE SAME - A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other. | 04-23-2015 |
20150108546 | METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE - An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption. | 04-23-2015 |
20150115322 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 04-30-2015 |
20150115323 | SEMICONDUCTOR DEVICE - A semiconductor device including a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap wider than that of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer to reach the middle of the first nitride semiconductor layer, a conductive film formed at a corner portion corresponding to an end portion of a bottom surface of the trench and a gate electrode disposed via a gate insulating film inside the trench including a region on the conductive film. | 04-30-2015 |
20150123166 | METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS - are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques. | 05-07-2015 |
20150123167 | METHOD AND GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS - A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region. | 05-07-2015 |
20150123168 | MISHFET AND SCHOTTKY DEVICE INTEGRATION - A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate. | 05-07-2015 |
20150129932 | SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE SEMICONDUCTOR-DEVICE LAYERS - A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the channel material is different from the lattice constant of the bulk substrate to introduce strain to the channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate. | 05-14-2015 |
20150129933 | TUCK STRATEGY IN TRANSISTOR MANUFACTURING FLOW - When forming field effect transistors with a semiconductor alloy layer, e.g., SiGe, embedded in the source/drain regions, a strategy called tucking has been developed in order to improve formation of the semiconductor alloy layer. An improved tucking strategy is hereby proposed, wherein the interface between the isolation region and the active region is not straight, but it rather defines an indentation, so that the active region protrudes into the isolation region in correspondence to the indentation. A gate is then formed on the surface of the device in such a way that a portion of the indentation is covered by the gate. An etching process is then performed, during which the gate acts as a screen. The etching thus gives rise to a cavity defined by a sidewall comprising portions exposing silicon, alternated to portions exposing the dielectric material of the isolation region. | 05-14-2015 |
20150129934 | METHODS OF FORMING SUBSTANTIALLY SELF-ALIGNED ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device. | 05-14-2015 |
20150137181 | STRESS INDUCING CONTACT METAL IN FINFET CMOS - A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer. | 05-21-2015 |
20150137182 | SEMICONDUCTOR DEVICE HAVING V-SHAPED REGION - Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm. | 05-21-2015 |
20150137183 | Controlling the Shape of Source/Drain Regions in FinFETs - An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness. | 05-21-2015 |
20150145002 | CMOS Devices with Reduced Leakage and Methods of Forming the Same - A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a ( | 05-28-2015 |
20150145003 | FINFET SEMICONDUCTOR DEVICES INCLUDING RECESSED SOURCE-DRAIN REGIONS ON A BOTTOM SEMICONDUCTOR LAYER AND METHODS OF FABRICATING THE SAME - FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side. | 05-28-2015 |
20150145004 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse. | 05-28-2015 |
20150295054 | Transistor with Elevated Drain Termination - According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature. | 10-15-2015 |
20150295070 | FINFET AND METHOD FOR MANUFACTURING THE SAME - A FinFET and a method for manufacturing the same. The method of manufacturing a FinFET includes: forming a punch-through stopper layer on a semiconductor substrate; forming a first semiconductor layer on the punch-through stopper layer; forming source and drain regions in the first semiconductor layer; forming a semiconductor fin from the first semiconductor layer, wherein the source and drain regions are in contact with the semiconductor fin at opposite ends of the semiconductor fin, respectively; and forming a gate stack intersecting the semiconductor fin and including a gate conductor and a gate dielectric interposed between the gate conductor and the semiconductor fin. | 10-15-2015 |
20150295086 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. | 10-15-2015 |
20150295087 | FINFET HAVING HIGHLY DOPED SOURCE AND DRAIN REGIONS - A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region. | 10-15-2015 |
20150303198 | METHOD AND STRUCTURE FOR FINFET DEVICE - The present disclosure provides a method for fabricating a fin-like field-effect transistor (FinFET). The method includes forming a first fin structures over a substrate, forming a patterned oxidation-hard-mask (OHM) over the substrate to expose the first fin structure in a first gate region of a n-type FET region, forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region, forming a second fin structure in a PFET region, forming dummy gates, forming source/drain (S/D) features, replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region and a second HK/MG in the PFET region. | 10-22-2015 |
20150303258 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 10-22-2015 |
20150303305 | FinFET Device with High-K Metal Gate Stack - The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region. | 10-22-2015 |
20150311207 | Structure and Method for FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a plurality of first fin structures over a substrate. The first fin structure includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer, being at least partially surrounded by a semiconductor oxide feature. The device also includes a third semiconductor material layer disposed over the second semiconductor material layer and a second fin structures over the substrate and adjacent to one of the first fin structures. The second fin structure includes the first semiconductor material layer and the third semiconductor material layer disposed over the dielectric layer. | 10-29-2015 |
20150311212 | Structure and Method for SRAM FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region. The device also includes a first and a second fin structures over the substrate in the NFET region and a third fin structure over the substrate in the PFET region. The device also includes a first high-k (HK)/metal gate (MG) stack in the NFET region, including wrapping over a portion of the first fin structure, a first subset of the first source/drain (S/D) features, adjacent to the first HK/MG stack, over the recessed first fin structure and a second subset of the first S/D features partially over the recessed second fin structure and partially over the recessed first fin structure. | 10-29-2015 |
20150311335 | STRUCTURE AND METHOD FOR FINFET DEVICE - The present disclosure provides a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first region, a second region and a third region. The first region includes a first fin structure, a first high-k (HK)/metal gate (MG) stack wrapping over an upper portion of the first fin structure and a first source/drain features, separated by the first HK/MG stack, over the recessed first fin structure. The second region includes a second fin structure, the first source/drain features over a portion of the recessed second fin structure. The third region includes a dummy gate stack over the second fin structure and the two first regions are separated by the second region, or by the third region. | 10-29-2015 |
20150311336 | Structure and Method for FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner. | 10-29-2015 |
20150318307 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 11-05-2015 |
20150318360 | REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICES - A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals. | 11-05-2015 |
20150318396 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a substrate having a well formed therein, the well including a first section and a second section, wherein the first section has a lower doping concentration and is closer to a surface of the substrate than the second section; a fin structure formed on the surface of the substrate; an isolation layer formed on the surface of the substrate, wherein the isolation layer exposes a portion of the fin structure, which serves as a fin for the semiconductor device; a gate stack formed on the isolation layer and intersecting the fin, wherein a Punch-Through Stopper (PTS) is formed in only a region directly under a portion of the fin where the fin intersects the gate stack | 11-05-2015 |
20150318397 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a fin formed on a substrate; a gate stack formed on the substrate and intersecting the fin, wherein the gate stack is isolated from the substrate by an isolation layer, and a Punch-Through Stopper (PTS) formed under the fin, including a first section directly under a portion of the fin where the fin intersects the gate stack and second sections on opposite sides of the first section, wherein the second sections each have a doping concentration lower than that of the first section. | 11-05-2015 |
20150325699 | FINFET AND METHOD FOR MANUFACTURING THE SAME - A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack. | 11-12-2015 |
20150333087 | MULTI-HEIGHT MULTI-COMPOSITION SEMICONDUCTOR FINS - A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions. | 11-19-2015 |
20150333172 | METHOD TO CONTROLLABLY ETCH SILICON RECESS FOR ULTRA SHALLOW JUNCTIONS - A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure. | 11-19-2015 |
20150333180 | SELECTIVE GERMANIUM P-CONTACT METALIZATION THROUGH TRENCH - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired. | 11-19-2015 |
20150340442 | Drain Extended Field Effect Transistors and Methods of Formation Thereof - In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region. | 11-26-2015 |
20150348971 | SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME - A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate. | 12-03-2015 |
20150349059 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a semiconductor column having a first portion comprising a first material, a second portion comprising a second material, and a third portion comprising a third material, where the second material is different than the first material and the third material. The first portion, the second portion, and the third portion have substantially equal widths. A first abrupt interface exists between a top surface of the first portion and a bottom surface of the second portion, and a second abrupt interface exists between a top surface of the second portion and a bottom surface of the third portion, in an embodiment. In an embodiment, the column forms part of a transistor where the first portions functions as a source or drain, the second portion functions as a channel, and the third portion functions as a drain or source. | 12-03-2015 |
20150349085 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers. | 12-03-2015 |
20150357412 | CONSTRAINED EPITAXIAL SOURCE/DRAIN REGIONS ON SEMICONDUCTOR-ON-INSULATOR FINFET DEVICE - A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconductor substrate, and forming a plurality of gate stacks on the insulator layer. Each gate stack wraps around a respective portion of the semiconductor fins. The method further includes forming a dielectric layer on the insulator layer. The dielectric layer fills voids between the semiconductor fins and gate stacks, and covers the semiconductor fins. The method further includes etching at least one portion of the semiconductor fins until reaching the insulator layer such that at least one cavity is formed. The cavity exposes seed regions of the semiconductor fins located between adjacent gate stacks. The method further includes epitaxially growing a semiconductor material from the seed regions to form source/drain regions corresponding to a respective gate stack. | 12-10-2015 |
20150357448 | BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME - A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region. | 12-10-2015 |
20150357468 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein the isolation layer exposes a portion of the fin structure, which serves as a fin for the semiconductor device; and a gate stack formed on the isolation layer and intersecting the fin, wherein a Punch-Through Stopper is formed in only a region directly under a portion of the fin where the fin intersects the gate stack. | 12-10-2015 |
20150357469 | Source/Drain Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises an isolation structure comprising a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface. | 12-10-2015 |
20150364492 | SINGLE-CHIP FIELD EFFECT TRANSISTOR (FET) SWITCH WITH SILICON GERMANIUM (SiGe) POWER AMPLIFIER AND METHODS OF FORMING - Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide. | 12-17-2015 |
20150364603 | FINFET AND NANOWIRE SEMICONDUCTOR DEVICES WITH SUSPENDED CHANNEL REGIONS AND GATE STRUCTURES SURROUNDING THE SUSPENDED CHANNEL REGIONS - A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer. | 12-17-2015 |
20150372139 | CONSTRAINING EPITAXIAL GROWTH ON FINS OF A FINFET DEVICE - A method includes forming at least one fin in a semiconductor substrate, forming a fin spacer on at least a first portion of the fin, the fin spacer having an upper surface, recessing the at least one fin to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer, and forming a first epitaxial material on the recessed fin, wherein a lateral extension of the epitaxial material is constrained by the fin spacer. | 12-24-2015 |
20150372142 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel. | 12-24-2015 |
20150372144 | Integrated Circuit Structure and Method with Solid Phase Diffusion - The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a channel region of a first type conductivity, defined in the fin active region and having a first carrier concentration; and an anti-punch through (APT) feature of the first type conductivity, wherein the APT feature is formed in the semiconductor substrate, is directly underlying the channel region, and has a second carrier concentration greater than the first carrier concentration. | 12-24-2015 |
20150380258 | METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE - Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights. | 12-31-2015 |
20150380410 | Structure and Method for SRAM FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer. | 12-31-2015 |
20150380412 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 12-31-2015 |
20150380489 | LOW RESISTANCE AND DEFECT FREE EPITAXIAL SEMICONDUCTOR MATERIAL FOR PROVIDING MERGED FinFETs - A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy. | 12-31-2015 |
20150380491 | METHOD FOR PRODUCING A MICROELECTRONIC DEVICE - A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: | 12-31-2015 |
20150380502 | METHOD TO FORM WRAP-AROUND CONTACT FOR FINFET - Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs. | 12-31-2015 |
20150380525 | Structure and Method for FinFET Device - A method for fabricating a fin-type field-effect transistor (FinFET) device includes forming a first fin structure over a substrate, forming a dielectric layer over the first fin structures, forming a trench with a vertical profile in the dielectric layer, depositing conformably a first semiconductor material layer over sidewalls and bottom of the trench, depositing a second semiconductor material layer over the first semiconductor material layer to filling in the remaining trench, recessing the dielectric layer to laterally expose the first semiconductor material layer and etching the exposed first semiconductor material layer to reveal the second semiconductor material layer. | 12-31-2015 |
20150380552 | TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A transistor structure is provided to reduce the sizes of a semiconductor device applying the transistor structure and maximize the performance of the semiconductor device, wherein the transistor structure comprises a substrate, a first semiconductor layer, a second semiconductor layer and a first gate structure. The first semiconductor layer that is formed on the substrate has a first space by which the first semiconductor layer is divided into a first region and a second region. The second semiconductor layer that is formed on the substrate and stacked on the first semiconductor layer comprises a first source region stacked on the first region, a first drain region stacked on the second region, a first floating structure crossing the first space and connected between the first source region and the first drain region. The first gate structure surrounds the first floating structure. | 12-31-2015 |
20150380554 | METHOD FOR FABRICATING A STRAINED STRUCTURE AND STRUCTURE FORMED - A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer. | 12-31-2015 |
20160005861 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device is provided with: a first conductivity type contact region; a second conductivity type body region; a first conductivity type drift region of; a trench formed through the contact region and body region from a front surface of the semiconductor substrate, wherein a bottom of the trench is positioned in the drift region; an insulating film covering an inner surface of the trench; a gate electrode accommodated in the trench in a state covered with the insulating film; and a second conductivity type floating region formed at a position deeper than the bottom of the trench, and adjacent to the bottom of the trench. The floating region includes a first layer adjacent to the bottom of the trench and a second layer formed at a position deeper than the first layer, wherein a width of the first layer is broader than a width of the second layer. | 01-07-2016 |
20160013265 | SEMICONDUCTOR DEVICE WITH FIELD THRESHOLD MOSFET FOR HIGH VOLTAGE TERMINATION | 01-14-2016 |
20160013296 | METHODS OF FORMING LOW DEFECT REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES | 01-14-2016 |
20160020274 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. | 01-21-2016 |
20160020275 | SHALLOW TRENCH ISOLATION STRUCTURE WITH SIGMA CAVITY - Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor. | 01-21-2016 |
20160020325 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor fabrication method. The method includes providing a semiconductor substrate having first regions and second regions; providing a first gate structure on a first region of the semiconductor substrate, and a second gate structure on a second region of the semiconductor substrate; and forming first trenches in the first region at both sides of the first gate structure. The method further includes forming a first stress layer in the first trenches and a first bumping stress layer on the first stress layer; forming second trenches in a second region at both sides of the second gate structure; and forming a second stress layer in the second trenches and a second bumping stress layer on the second stress layer. | 01-21-2016 |
20160027777 | FinFET DEVICE WITH DUAL-STRAINED CHANNELS AND METHOD FOR MANUFACTURING THEREOF - A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed. | 01-28-2016 |
20160027781 | III-V LAYERS FOR N-TYPE AND P-TYPE MOS SOURCE-DRAIN CONTACTS - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures. | 01-28-2016 |
20160035875 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 02-04-2016 |
20160043066 | APPARATUS AND METHOD OF MANUFACTURING THE SAME - Teaching disclosed herein is an apparatus comprising a support layer. The support layer may be adapted for supporting a heat generator, wherein the support layer includes a flow passage. The flow passage may seal working fluid therein. The flow passage may extend along a thickness direction of the support layer. | 02-11-2016 |
20160043208 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes the followings. A semiconductor multilayer structure is above a substrate and includes a first nitride semiconductor layer and a second nitride semiconductor layer. A source electrode, a drain electrode, and a gate electrode are on the semiconductor multilayer structure. A gate wiring line transmits a gate driving signal to gate electrodes. A first shield structure is on the semiconductor multilayer structure between the drain electrode and the gate electrode or between the drain electrode and the gate wiring line in a non-channel region where an actual current path from the drain electrode to the source electrode is not formed in the semiconductor multilayer structure. The first shield structure is a normally-off structure, suppresses a current flowing from the semiconductor multilayer structure, and is set to have a substantially same potential as a potential of the source electrode. | 02-11-2016 |
20160049464 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region. | 02-18-2016 |
20160049513 | TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS - Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded. | 02-18-2016 |
20160049515 | FINFET INCLUDING IMPROVED EPITAXIAL TOPOLOGY - A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins. | 02-18-2016 |
20160056274 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased. | 02-25-2016 |
20160056290 | Metal-Insensitive Epitaxy Formation - The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer. | 02-25-2016 |
20160056304 | NANOWIRE NANOELECTROMECHANICAL FIELD-EFFECT TRANSISTORS - A three-terminal nano-electro-mechanical field-effect transistor (NEMFET) includes a source electrode, a gate electrode, a drain electrode and a nanoelectromechanically suspended channel bridging the source electrode and the drain electrode. The nanoelectromechanically suspended channel includes a moveable nanowire and a dielectric coating on a surface of the nanowire facing the gate electrode. A thickness of a gap between the nanowire and the gate electrode is determined by a thickness of the dielectric coating. | 02-25-2016 |
20160064221 | METHOD OF FORMING TRANSISTOR - According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn. | 03-03-2016 |
20160064288 | DUAL CHANNEL MATERIAL FOR finFET FOR HIGH PERFORMANCE CMOS - Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion. | 03-03-2016 |
20160064379 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHODS THEREOF - A method for forming FinFETs includes, sequentially, providing a substrate; forming a plurality of fins on a surface of the substrate; forming a gate structure overlying on at least one of the plurality of fins; forming a barrier layer covering top and side surfaces of the gate structures, and top and side surfaces of the plurality of fins; performing a radical oxidation process to convert a top portion of the barrier layer to a passive layer to form a remaining barrier layer and to cause the top surfaces of the fins to be flat after subsequent etching processes; performing an etch-back process on the passive layer to form passive sidewalls on side surfaces of the portions of the remaining barrier on the side surfaces of the fins; and removing portions of the remaining barrier layer on the top surfaces of the fins by a wet etching process using the passive sidewalls as an etching mask. | 03-03-2016 |
20160064381 | Fin-Like Field Effect Transistor (FinFET) Device And Method Of Manufacturing Same - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer. | 03-03-2016 |
20160064493 | FIN STRUCTURE AND METHOD FOR FORMING THE SAME - According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core. | 03-03-2016 |
20160064522 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer. | 03-03-2016 |
20160064543 | FINFET WITH A SILICON GERMANIUM ALLOY CHANNEL AND METHOD OF FABRICATION THEREOF - A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. | 03-03-2016 |
20160064544 | FINFET SEMICONDUCTOR DEVICE WITH ISOLATED FINS MADE OF ALTERNATIVE CHANNEL MATERIALS - One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin. | 03-03-2016 |
20160064563 | PFET AND CMOS CONTAINING SAME - A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above. | 03-03-2016 |
20160064565 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region. | 03-03-2016 |
20160064566 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT - A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement. | 03-03-2016 |
20160071732 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME AND METHOD OF SUPPRESSING DECREASE OF FLAT BAND VOLTAGE - There is provided a semiconductor device comprising a semiconductor layer that is made of a gallium-containing group III-V compound; and a first insulating film that is in contact with the semiconductor layer and contains silicon. An average density of gallium in the first insulating film between an interface of the first insulating film and the semiconductor layer and a plane away from the interface by 30 nm is less than 1.0×10 | 03-10-2016 |
20160071934 | HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS - Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface. | 03-10-2016 |
20160071939 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor layer having a buffer layer, a spacer layer, and barrier layer sequentially stacked on the substrate, and first and second ohmic electrodes installed on an upper surface of the barrier layer in the substrate to be separated from each other. Each of the first and second ohmic electrodes includes a portion formed on the upper surface of the barrier layer and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, and the portion formed on the upper surface of the barrier layer and the electrode portions are integrally formed. | 03-10-2016 |
20160071970 | CONFINED SEMI-METAL FIELD EFFECT TRANSISTOR - Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal. | 03-10-2016 |
20160079282 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH AN ISOLATION REGION AND A DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures | 03-17-2016 |
20160079372 | DEVICE CONTACT STRUCTURES INCLUDING HETEROJUNCTIONS FOR LOW CONTACT RESISTANCE - A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV. | 03-17-2016 |
20160079424 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region. | 03-17-2016 |
20160086950 | SEMICONDUCTOR DEVICE HAVING CONTACT PLUG AND METHOD OF FORMING THE SAME - A semiconductor device includes an N-type fin and a P-type fin on a substrate, a first gate electrode configured to cross the N-type fin and cover a side surface of the N-type fin, a second gate electrode configured to cross the P-type fin and cover a side surface of the P-type fin, a first source/drain on the N-type fin adjacent to the first gate electrode, a second source/drain on the P-type fin adjacent to the second gate electrode, a buffer layer on a surface of the second source/drain and including a material different from the second source/drain, an interlayer insulating layer on the buffer layer and the first source/drain, a first plug connected to the first source/drain and passing through the interlayer insulating layer, and a second plug connected to the second source/drain and passing through the interlayer insulating layer and the buffer layer. | 03-24-2016 |
20160087041 | Method and Structure for FinFET Device - The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion. | 03-24-2016 |
20160087070 | METHOD AND APPARATIS FOR SOURCE-DRAIN JUNCTION FORMATION FINFET WITH QUANTUM BARRIER AND GROUND PLANE DOPING - A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region. | 03-24-2016 |
20160087100 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING FIN STRUCTURES WITH DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR STRUCTURES - Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states. | 03-24-2016 |
20160087101 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region. | 03-24-2016 |
20160087104 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region. | 03-24-2016 |
20160093726 | Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel - The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed on a substrate; a gate stack formed over the fin structure; source/drain regions over the substrate and disposed on opposing sides of the gate stack; a channel region defined in the fin structure and underlying the gate stack, wherein the channel region is un-doped; and a buried isolation layer disposed vertically between the channel region and the substrate, wherein the buried isolation layer includes a compound semiconductor oxide. | 03-31-2016 |
20160093737 | ETCHING METHOD FOR FORMING GROOVES IN Si-SUBSTRATE AND FIN FIELD-EFFECT TRANSISTOR - An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted | 03-31-2016 |
20160099336 | OPC ENLARGED DUMMY ELECTRODE TO ELIMINATE SKI SLOPE AT ESIGE - Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width. | 04-07-2016 |
20160099352 | FETS AND METHODS OF FORMING FETS - An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion. | 04-07-2016 |
20160104706 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material. | 04-14-2016 |
20160104772 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE - A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins. | 04-14-2016 |
20160111323 | MOSFETs with Channels on Nothing and Methods for Forming the Same - A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer. | 04-21-2016 |
20160111422 | METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES - Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins. | 04-21-2016 |
20160111496 | Method and Structure for III-V FinFET - A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the III-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension. | 04-21-2016 |
20160111501 | METHOD TO DEFINE THE ACTIVE REGION OF A TRANSISTOR EMPLOYING A GROUP III-V SEMICONDUCTOR MATERIAL - A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided. | 04-21-2016 |
20160111505 | Semiconductor Device with Breakdown Preventing Layer - A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film or a low conductive film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film or the low conductive film. The conducting elements can vary in at least one of composition, doping, conductivity, size, thickness, shape, and distance from the device channel along a lateral length of the insulating film or the low conductive film, or in a direction that is perpendicular to the lateral length. | 04-21-2016 |
20160111537 | CONTACT RESISTANCE REDUCTION TECHNIQUE - An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer. | 04-21-2016 |
20160111538 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region. | 04-21-2016 |
20160111544 | METHOD OF FABRICATING ELECTROSTATICALLY ENHANCED FINS AND STACKED NANOWIRE FIELD EFFECT TRANSISTORS - Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate. | 04-21-2016 |
20160118379 | CASCODE SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR - In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. | 04-28-2016 |
20160118384 | SELF-ALIGNED CONTACT METALLIZATION FOR REDUCED CONTACT RESISTANCE - Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures. | 04-28-2016 |
20160118463 | FLOATING BODY MEMORY WITH ASYMMETRIC CHANNEL - A semiconductor structure and formation thereof. The semiconductor structure has a fin of a first semiconductor material. The fin has a first side surface opposite a second side surface. The semiconductor structure has a portion of a second semiconductor material that has a third side surface opposite a fourth side surface. The fourth side surface of the second semiconductor material abuts and covers the first side surface of the fin. The semiconductor structure has a portion of a third semiconductor material that abuts and covers the second side surface of the fin. The semiconductor structure has a single gate structure that covers the fin, the portion of the second semiconductor material and the portion of the third semiconductor material. The fin manifests an asymmetry due to the portion of the second semiconductor material and the portion of the third semiconductor material. | 04-28-2016 |
20160118483 | MULTI-GATE FETS HAVING CORRUGATED SEMICONDUCTOR STACKS AND METHOD OF FORMING THE SAME - The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material. | 04-28-2016 |
20160118491 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first nitride semiconductor layer formed on the substrate, a p-type nitride semiconductor layer formed on the first nitride semiconductor layer, a recess having a bottom portion which reaches the first nitride semiconductor layer through a part of the p-type nitride semiconductor layer, a third nitride semiconductor layer formed to cover the bottom portion of the recess, a side portion of the recess, and a part of an upper surface of the p-type nitride semiconductor layer. The semiconductor device further includes a fourth nitride semiconductor layer formed on the third nitride semiconductor layer, a first electrode formed on another side of the substrate, a gate electrode formed on the upper surface of the p-type nitride semiconductor layer, and a second electrode that is in contact with the third nitride semiconductor layer or the fourth nitride semiconductor layer. The third nitride semiconductor layer has a bandgap different from a bandgap of the fourth nitride semiconductor layer. | 04-28-2016 |
20160126338 | TRANSISTOR AND FABRICATION METHOD THEREOF - A method for forming transistors is provided. The method includes providing a substrate having a base and at least a fin on the base; and forming a gate layer on the fin, the gate layer has first side surfaces parallel to a longitudinal direction of the fin and second side surfaces perpendicular to the fin. The method also includes forming a protective layer on the first side surfaces of the gate layer to protect a vertex of the top of the gate layer from having EPI particles; and forming sidewall spacers on side surfaces of the protective layer and the second side surfaces of the gate layer. Further, the method includes forming a stress layer in the fin at both sides of the sidewall spacers and the gate layer. | 05-05-2016 |
20160126343 | FinFETs with Source/Drain Cladding - A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors. | 05-05-2016 |
20160126353 | FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN - A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure. | 05-05-2016 |
20160133710 | REDUCING LEAKAGE CURRENT IN SEMICONDUCTOR DEVICES - A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals. | 05-12-2016 |
20160141288 | FIN SHAPE STRUCTURE - A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer. | 05-19-2016 |
20160141377 | LOW TEMPERATURE SPACER FOR ADVANCED SEMICONDUCTOR DEVICES - Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure. | 05-19-2016 |
20160148930 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region. | 05-26-2016 |
20160149050 | REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS - An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer. | 05-26-2016 |
20160155740 | CMOS Devices having Dual High-Mobility Channels | 06-02-2016 |
20160163848 | MISFET Device - Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode. | 06-09-2016 |
20160163859 | NITRIDE LAYER PROTECTION BETWEEN PFET SOURCE/DRAIN REGIONS AND DUMMY GATE DURING SOURCE/DRAIN ETCH - Methods of using a nitride to protect source/drain regions during dummy gate removal and the resulting devices are disclosed. Embodiments include forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; growing first and second eSiGe source/drain regions in the first and second source/drain cavities, respectively; and removing the first dummy gate and the second dummy gate stack. | 06-09-2016 |
20160163860 | SEMICONDUCTOR DEVICE HAVING STRESSOR AND METHOD OF FORMING THE SAME - A semiconductor device having a stressor is provided. A first trench and a second trench spaced apart from each other are formed in a substrate. A channel area is defined between the first trench and the second trench. A gate dielectric layer is formed on the channel area. A gate electrode is formed on the gate dielectric layer. The stressor includes a plurality of semiconductor layers formed in the first trench and the second trench and a plurality of interlayers formed between the semiconductor layers. Sidewalls of the first trench and the second trench are v-shaped (e.g., have a < or > shape). | 06-09-2016 |
20160163861 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode. | 06-09-2016 |
20160172454 | Reliable and Robust Electrical Contact | 06-16-2016 |
20160172462 | FIN REPLACEMENT IN A FIELD-EFFECT TRANSISTOR | 06-16-2016 |
20160172480 | GATE STRUCTURES FOR III-N DEVICES | 06-16-2016 |
20160172495 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | 06-16-2016 |
20160172498 | FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION | 06-16-2016 |
20160181250 | FINFET BASED ZRAM WITH CONVEX CHANNEL REGION | 06-23-2016 |
20160181277 | Multiple VT in III-V FETS | 06-23-2016 |
20160181364 | DUAL-CHANNEL FIELD EFFECT TRANSISTOR DEVICE HAVING INCREASED AMPLIFIER LINEARITY | 06-23-2016 |
20160181368 | STRUCTURES AND DEVICES INCLUDING A TENSILE-STRESSED SILICON ARSENIC LAYER AND METHODS OF FORMING SAME | 06-23-2016 |
20160181424 | METHODS OF FORMING LOW BAND GAP SOURCE AND DRAIN STRUCTURES IN MICROELECTRONIC DEVICES | 06-23-2016 |
20160181426 | METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN A TRENCH FORMED ABOVE A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES | 06-23-2016 |
20160181427 | SEMICONDUCTOR DEVICE | 06-23-2016 |
20160190017 | Structure and Method for Semiconductor Device - A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other. | 06-30-2016 |
20160190303 | SILICON GERMANIUM-ON-INSULATOR FINFET - A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration. | 06-30-2016 |
20160190312 | VERTICAL GATE ALL-AROUND TRANSISTOR - Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density. | 06-30-2016 |
20160190316 | CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN - A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure. | 06-30-2016 |
20160190317 | HETERO-CHANNEL FINFET - A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable. | 06-30-2016 |
20160190320 | SURFACE TENSION MODIFICATION USING SILANE WITH HYDROPHOBIC FUNCTIONAL GROUP FOR THIN FILM DEPOSITION - A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure. | 06-30-2016 |
20160197078 | STRUCTURE AND METHOD FOR ADVANCED BULK FIN ISOLATION | 07-07-2016 |
20160197188 | SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME | 07-07-2016 |
20160197189 | METHOD TO CONTROLLABLY ETCH SILICON RECESS FOR ULTRA SHALLOW JUNCTIONS | 07-07-2016 |
20160204203 | METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS | 07-14-2016 |
20160254366 | V-SHAPED SIGE RECESS VOLUME TRIM FOR IMPROVED DEVICE PERFORMANCE AND LAYOUT DEPENDENCE | 09-01-2016 |
20160254381 | Modulating Germanium Percentage in MOS Devices | 09-01-2016 |
20160379981 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS WITH SUPPRESSED DOPANT DIFFUSION - A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure includes fins having silicon germanium top portions and an epitaxial carbon-doped silicon germanium diffusion barrier that suppresses dopant diffusion from the underlying n-well into the silicon germanium fin region during device fabrication. The structure further includes an nFET region including silicon fins formed from the substrate. The carbon-doped silicon germanium diffusion barrier has the same or higher germanium content than the silicon germanium fins. | 12-29-2016 |
20160380089 | HIGH VOLTAGE DEVICE WITH MULTI-ELECTRODE CONTROL - A high-voltage transistor (HVT) structure adapts a low-voltage transistor (LVT) to high-voltage environments. The HVT structure includes a drain node, a source node, a control gate, and a field electrode. The drain node and the source node define a conductive channel, in which mobilized charges are regulated by the control gate. While being isolated from the control gate, the field electrode is configured to spread the mobilized charges in response to a field voltage. The field electrode is structured and routed to prevent charge sharing with any one of the drain node, source node, or control gate. Advantageously, the isolated field electrode minimizes the capacitance of the control gate as well as the drain and source nodes, such that the HVT can switch with less power loss and a more robust performance in a high-voltage environment. | 12-29-2016 |
20160380094 | FIELD EFFECT TRANSISTORS WITH STRAINED CHANNEL FEATURES - A method is provided for forming an integrated circuit. A doped silicon layer is formed on a silicon substrate. A silicon-germanium layer is subsequently formed on the doped silicon layer. The silicon-germanium layer is pattered to form a silicon-germanium feature. A silicon shell is formed on the silicon-germanium feature. At least a portion of the dopes silicon layer is converted to a porous silicon layer. Following the last step, the silicon shell is tensily stressed, making it a good candidate for use as a channel feature in an n-type field effect transistor. | 12-29-2016 |
20170236755 | TUNNELING FIN TYPE FIELD EFFECT TRANSISTOR WITH EPITAXIAL SOURCE AND DRAIN REGIONS | 08-17-2017 |
20170236841 | FIN WITH AN EPITAXIAL CLADDING LAYER | 08-17-2017 |
20180026097 | N-CHANNEL GALLIUM NITRIDE TRANSISTORS | 01-25-2018 |
20180026136 | SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS | 01-25-2018 |
20190148218 | MOSFETs with Channels on Nothing and Methods for Forming the Same | 05-16-2019 |
20190148491 | STRAIN COMPENSATION IN TRANSISTORS | 05-16-2019 |
20190148495 | GE BASED SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACURING THE SAME | 05-16-2019 |
20190148510 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 05-16-2019 |
20190148520 | Integrated Circuit Device Fins | 05-16-2019 |
20190148551 | METHOD OF FORMING SOURCE/DRAIN EPITAXIAL STACKS | 05-16-2019 |
20190148552 | FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN STRUCTURES | 05-16-2019 |