Class / Patent application number | Description | Number of patent applications / Date published |
257203000 | With particular chip input/output means | 49 |
20080203435 | Semiconductor device having elongated electrostatic protection element along long side of semiconductor chip - An electrostatic protection element is disposed commonly to a plurality of output circuits along a long side of an output circuit region. More preferably, the electrostatic protection element should be disposed between a Pch region and an Nch region of an output circuit. | 08-28-2008 |
20080203436 | Semiconductor device and layout method of decoupling capacitor thereof - A semiconductor device and a layout method of a decoupling capacitor thereof are disclosed. The semiconductor device includes a main power/ground voltage voltage supplying line arranged in a first direction; a plurality of decoupling capacitor cells to reduce power noise generated by the power voltage and the ground voltage in the first direction and in a second direction; a plurality of sub power voltage supplying lines arranged in the second direction in a border of the plurality of decoupling capacitor cells; and a plurality of sub ground voltage supplying lines arranged in a net form in the border of the plurality of decoupling capacitor cells, wherein the plurality of decoupling capacitor cells have a first active region arranged to receive the ground voltage and the second active region disposed to receive the power voltage and to avoid a region where an inversion is formed in the decoupling capacitor. | 08-28-2008 |
20080210979 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DESIGNING THE SAME - A semiconductor integrated circuit, including: a semiconductor chip; an internal integrated circuit area formed at a center side of the semiconductor chip; and an I/O area formed at a peripheral side of the semiconductor chip except where the internal integrated circuit area exists, the I/O area having a first power supply cell placed at a predetermined position therein. In a case in which an empty area adjacent to the first power supply cell exists, a second power supply cell is inserted therein and the first power supply cell and the second power supply cell are electrically connected with each other by a first wiring pattern added. | 09-04-2008 |
20080217656 | I/O CIRCUIT WITH ESD PROTECTING FUNCTION - For ensuring the complete turn-off state of an ESD protecting device and preventing leakage current from a chip, an alternative conducting path is formed in the chip for bypassing an external current. The chip further includes an internal circuit and a conducting circuit. | 09-11-2008 |
20080237645 | SEMICONDUCTOR DEVICE - A semiconductor device of an aspect of the present invention comprises a package substrate, one first power supply terminal provided on the package substrate, one second power supply terminal provided on the package substrate, a semiconductor chip disposed on the package substrate, first and second internal power supply circuits provided in the semiconductor chip, one first ESD protection element which is provided in the first internal power supply circuit and which is connected to the first power supply terminal, and a plurality of second ESD protection elements, the second ESD protection elements being provided in the second internal power supply circuit, the size of one second ESD protection element being smaller than that of the first ESD protection element, the second ESD protection elements being connected to the common second power supply terminal. | 10-02-2008 |
20080290375 | INTEGRATED CIRCUIT FOR VARIOUS PACKAGING MODES - The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The selection circuit is coupled between the core circuit and the pads for determining the connection state between the core circuit and the pads based on a control signal. When the control signal provides a first value, the core circuit and the pads will be in a first connection state, and the integrated circuit will be applied with a single-die package. However, when the control signal provides a second value, the core circuit and the pads will be in the second connection state, and the integrated circuit will be applied with a multi-die package. | 11-27-2008 |
20090050940 | SEMICONDUCTOR DEVICE - The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer. | 02-26-2009 |
20090078967 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE HAVING A PLURALITY OF SEMICONDUCTOR CHIPS - The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip of the present invention includes an internal circuit and a first electrode pad electrically connected to a ground bus line of the first semiconductor chip in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit, cannot be provided. | 03-26-2009 |
20090146189 | Pads and pin-outs in three dimensional integrated circuits - A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or below the substrate coupled to a said circuit to program the memory array. | 06-11-2009 |
20090152591 | Design Structure for an On-Demand Power Supply Current Modification System for an Integrated Circuit - A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line. | 06-18-2009 |
20090152592 | STRUCTURE FOR A LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA - A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits. | 06-18-2009 |
20090166679 | INTEGRATED CIRCUIT AND MANUFACTURING PROCESS FACILITATING SELECTIVE CONFIGURATION FOR ELECTROMAGNETIC COMPATIBILITY - An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic. | 07-02-2009 |
20090189194 | Electrostatic Discharge (ESD) Protection Circuit Placement in Semiconductor Devices - Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices. | 07-30-2009 |
20090189195 | Radio Frequency (RF) Circuit Placement in Semiconductor Devices - Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices. | 07-30-2009 |
20090273007 | Method Of Testing An Integrated Circuit Die, And An Integrated Circuit Die - In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing. | 11-05-2009 |
20100012979 | SUBSTRATE FOR ELECTRO-OPTICAL DEVICE WITH LIGHT SHIELDING SECTION HAVING VARIOUS WIDTHS, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - Disclosed is a substrate for an electro-optical device including: a substrate; a plurality of data lines and a plurality of scanning lines which intersect with other on the substrate; a pixel electrode formed in each of a plurality of pixels which configure a display region on the substrate and are defined in correspondence with intersections between the plurality of data lines and the plurality of scanning lines; a transistor provided in each of non-opening regions which discriminate between opening regions of the plurality of pixels and including a semiconductor layer including a channel region having a channel length in one direction of the display region, a data line side source/drain region electrically connected to the data line, a pixel electrode side source/drain region electrically connected to the pixel electrode, a first junction region formed between the channel region and the data line side source/drain region, and a second junction region formed between the channel region and the pixel electrode side source/drain region; and a light-shielding section which is formed above each of the semiconductor layers, extends along the one direction, and includes a first portion which covers the first junction region and a second portion which covers the second junction region and has a width larger than that of the first portion in a direction intersecting the one direction. | 01-21-2010 |
20100090252 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD. | 04-15-2010 |
20100096670 | SEMICONDUCTOR DEVICE WITH INTERFACE CIRCUIT AND METHOD OF CONFIGURING SEMICONDUCTOR DEVICES - Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell. | 04-22-2010 |
20100109053 | SEMICONDUCTOR DEVICE HAVING INTEGRATED CIRCUIT WITH PADS COUPLED BY EXTERNAL CONNECTING COMPONENT AND METHOD FOR MODIFYING INTEGRATED CIRCUIT - The present invention discloses a semiconductor device. The semiconductor device includes an integrated circuit and a connecting component. The integrated circuit includes a first pad; a second pad; a first current guiding circuit, coupled to the first pad and a first reference voltage, for selectively guiding a first specific electrical signal received from the first pad to the first reference voltage; and a second current guiding circuit, coupled to the second pad and a second reference voltage, for selectively guiding a second specific electrical signal received from the second pad to the second reference voltage; and the connecting component is external to the integrated circuit for coupling the first pad and the second pad. | 05-06-2010 |
20100148218 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME - The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted. | 06-17-2010 |
20100230725 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell. | 09-16-2010 |
20100327324 | SEMICONDUCTOR CHIP - In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit. | 12-30-2010 |
20110031535 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A finger length al of a transistor P | 02-10-2011 |
20110073914 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD. | 03-31-2011 |
20110073915 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to the present invention includes an I/O cell, a first PAD connected to the I/O cell, first and second PADs, a package wire which is connected to the first PAD and allows connection between the first PAD and an outside of the semiconductor integrated circuit, and a second package wire which is connected to the second PAD and allows connection between the second PAD and an outside of the semiconductor integrated circuit. A connection point between the first PAD and the fist package wire is located in an area where the I/O cell is placed. A connection point between the second PAD and the second package wire is located outside an area where the I/O cell is placed. | 03-31-2011 |
20110089470 | SEMICONDUCTOR DEVICE HAVING LAYOUT OF LOGIC CELL AND INTERFACE CELL WITH UNIFICATION OF TRANSISTOR ORIENTATION - In a semiconductor device, a plurality of interface cells is disposed on four sides of an LSI chip in connection with a logic circuit area including a plurality of logic cells. Each interface cell may include four functional blocks which are vertically or horizontally aligned without being rotated, thus forming an I/O buffer. The left I/O buffer has a vertical layout in which functional blocks are vertically aligned, whilst the upper I/O buffer has a horizontal layout in which functional blocks are horizontally aligned. This makes it possible to fix the same length direction of gates of transistors with respect to both the functional blocks of I/O buffers and the logic cells, so that engineers do not need to consider characteristic variations of transistors due to positional differences of transistors when designing the circuitry of an LSI chip. | 04-21-2011 |
20110133252 | SEMICONDUCTOR DEVICE WITH INTERFACE CIRCUIT AND METHOD OF CONFIGURING SEMICONDUCTOR DEVICES - Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell. | 06-09-2011 |
20110156101 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN APPARATUS OF SEMICONDUCTOR DEVICE - A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer. | 06-30-2011 |
20120025272 | SEMICONDUCTOR INTEGRATED CIRCUIT CHIP AND LAYOUT METHOD FOR THE SAME - A semiconductor integrated circuit chip mounted on a substrate by flip chip bonding includes: a plurality of electrode pads; a corner portion of a flat periphery of an inner layer; a first linear region adjoining one side of the corner portion; a second linear region adjoining another side of the corner portion; and a third linear region adjoining a side of the first linear region opposite to the side adjoining the corner portion. A circuit core placeable region is provided in at least part of the corner portion and the first linear region. A plurality of IO cells connected to the electrode pads are arranged in the second and third linear regions. The IO cells in the second linear region are connected to the electrode pads arranged inwardly in n rows×n columns from a corner of the chip above the corner portion. | 02-02-2012 |
20120112245 | ACCESSING OR INTERCONNECTING INTEGRATED CIRCUITS - Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and (programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools. | 05-10-2012 |
20120132963 | STANDARD CELL FOR INTEGRATED CIRCUIT - An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact. | 05-31-2012 |
20120223368 | Power Routing in Standard Cells - An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules. | 09-06-2012 |
20120267689 | Memory with Off-Chip Controller - An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together. | 10-25-2012 |
20120292667 | CROSSBAR STRUCTURE WITH MECHANISM FOR GENERATING CONSTANT OUTPUTS - Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed. | 11-22-2012 |
20130234211 | SEMICONDUCTOR DEVICE - A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G | 09-12-2013 |
20130240954 | SEMICONDUCTOR INTEGRATED CIRCUIT CHIP AND LAYOUT METHOD FOR THE SAME - A semiconductor integrated circuit chip mounted on a substrate by flip chip bonding includes: a plurality of electrode pads; a corner portion of a flat periphery of an inner layer; a first linear region adjoining one side of the corner portion; a second linear region adjoining another side of the corner portion; and a third linear region adjoining a side of the first linear region opposite to the side adjoining the corner portion. A circuit core placeable region is provided in at least part of the corner portion and the first linear region. A plurality of IO cells connected to the electrode pads are arranged in the second and third linear regions. The IO cells in the second linear region are connected to the electrode pads arranged inwardly in n rows×n columns from a corner of the chip above the corner portion. | 09-19-2013 |
20140209981 | Semiconductor Device - Disclosed is a semiconductor device including transistors B on an output side of a current mirror, arranged uniformly in a surrounding area of a transistor A on an input side of the current mirror. The transistors B are arranged at equal distances, adjacently to the transistor A, on both sides of the transistor A. | 07-31-2014 |
20140246701 | Flexible, space-efficient I/O circuitry for integrated circuits - Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding. | 09-04-2014 |
20140246702 | Flexible, space-efficient I/O circuitry for integrated circuits - Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding. | 09-04-2014 |
20140246703 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell. | 09-04-2014 |
20140264461 | METAL LAYER ENABLING DIRECTED SELF-ASSEMBLY SEMICONDUCTOR LAYOUT DESIGNS - Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells. | 09-18-2014 |
20140264462 | FILM TRANSFERABLE LOGIC CIRCUIT, AND METHODS FOR PROVIDING FILM TRANSFERABLE LOGIC CIRCUIT - A filmic circuit includes a circuit portion and a carrier layer. The circuit portion includes a logic circuit that includes, for example, plural logic gates configurable to receive an input and provide a corresponding logical output. The carrier layer is configured as a film. The circuit portion is affixed directly to the carrier layer or to an upper coat disposed adjacent to the carrier layer, and the carrier layer is configured to be releasable from the circuit portion after the filmic circuit assembly is affixed to a target. The circuit portion is configured to receive an adhesive layer configured to affix the filmic circuit assembly to the target. | 09-18-2014 |
20140353727 | I/O CELL ESD SYSTEM - An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network. | 12-04-2014 |
20160013192 | PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS | 01-14-2016 |
20160056173 | SEMICONDUCTOR DEVICE WITH SURROUNDING GATE TRANSISTORS IN A NAND CIRCUIT - A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit. | 02-25-2016 |
20160056174 | SEMICONDUCTOR DEVICE WITH SURROUNDING GATE TRANSISTORS IN A NOR CIRCUIT - A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit. | 02-25-2016 |
20160079231 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region. | 03-17-2016 |
20160163799 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including an active fin and an isolation layer thereon, a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern, a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type, and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type. | 06-09-2016 |
20160190156 | METAL ON ELONGATED CONTACTS - An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. | 06-30-2016 |