Entries |
Document | Title | Date |
20080197457 | SILICON WAFER AND ITS MANUFACTURING METHOD - A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according to the 90° light scattering method is formed in a region at a depth from the wafer surface of 25 μm or more but less than 100 μm, and a layer which has a light scattering defect density of 1×10 | 08-21-2008 |
20080277768 | SILICON MEMBER AND METHOD OF MANUFACTURING THE SAME - There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method for manufacturing the same. The silicon member having a resistivity of 0.1 Ω·cm or more and 100 Ω·cm or less is manufactured with steps which are manufacturing a P-type silicon single crystal doped with 13 group atoms of a periodic table having an intrinsic resistivity of 1 Ω·cm or more and 100 Ω·cm or less, and changing said P-type silicon single crystal into an N-type silicon single crystal by oxygen donors formed by annealing at a temperature of 300° C. or more and 500° C. or less. | 11-13-2008 |
20090032912 | Semiconductor component with buffer layer - A semiconductor component having at least one pn junction and an associated production method. The semiconductor component has a layer sequence of a first zone having a first dopant. The first zone faces a first main area. Adjacent to the first zone are a second zone having a low concentration of a second dopant, a subsequent buffer layer, the third zone, also having the second dopant and a subsequent fourth zone having a high concentration of the second dopant. The fourth zone faces a second main area. In this case, the concentration of the second doping of the buffer layer is higher at the first interface of the barrier layer with the second zone than at the second interface with the fourth zone. According to the invention, the buffer layer is produced by ion implantation. | 02-05-2009 |
20090039477 | SILICON NITRIDE SUBSTRATE, A MANUFACTURING METHOD OF THE SILICON NITRIDE SUBSTRATE, A SILICON NITRIDE WIRING BOARD USING THE SILICON NITRIDE SUBSTRATE, AND SEMICONDUCTOR MODULE - In the silicon nitride substrate concerning an embodiment of the invention, degree of in-plane orientation fa of β type silicon nitride is 0.4-0.8. Here, degree of in-plane orientation fa can be determined by the rate of the diffracted X-ray intensity in each lattice plane orientation in β type silicon nitride. As a result of research by the inventors, it turned out that both high fracture toughness and high thermal conductivity are acquired, when degree of in-plane orientation fa was 0.4-0.8. Along the thickness direction, both the fracture toughness of 6.0 MPa·m | 02-12-2009 |
20090039478 | Method For Utilizing Heavily Doped Silicon Feedstock To Produce Substrates For Photovoltaic Applications By Dopant Compensation During Crystal Growth - A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant and or dopants before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within an acceptable range for manufacturing high efficiency solar cells. | 02-12-2009 |
20090085176 | GLASS-BASED SOI STRUCTURES - Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer ( | 04-02-2009 |
20090267200 | METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE INCLUDING LASER ANNEALING - A method for manufacturing a semiconductor device by laser annealing. One embodiment provides a semiconductor substrate having a first surface and a second surface. The second surface is arranged opposite to the first surface. A first dopant is introduced into the semiconductor substrate at the second surface such that its peak doping concentration in the semiconductor substrate is located at a first depth with respect to the second surface. A second dopant is introduced into the semiconductor surface at the second surface such that its peak doping concentration in the semiconductor substrate is located at a second depth with respect to the second surface, wherein the first depth is larger than the second depth. At least a first laser anneal is performed by directing at least one laser beam pulse onto the second surface to melt the semiconductor substrate, at least in sections, at the second surface. | 10-29-2009 |
20090278239 | Silicon Wafer and Production Method Thereof - In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 μm and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×10 | 11-12-2009 |
20090283875 | Self-supported film and silicon wafer obtained by sintering - Self-supported film and silicon wafer obtained by sintering. A silicon wafer for a photovoltaic cell is produced by a debinding step of a self-supported film formed of at least one main thin layer comprising at least 50% volume of silicon particles, devoid of silicon oxide and encapsulated in a polymer matrix protecting them against oxidation, followed by a sintering step to form the silicon wafer. | 11-19-2009 |
20100006986 | Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions - A restricted layout region is defined to include a diffusion level layout that includes a plurality of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout of the restricted layout region. The plurality of diffusion region layout shapes include a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. A gate electrode level layout is defined include a number of rectangular-shaped layout features placed to extend in only a first parallel direction, and defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout. | 01-14-2010 |
20100038757 | SILICON WAFER, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR HEAT-TREATING THE SAME - A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T | 02-18-2010 |
20100078775 | SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned. | 04-01-2010 |
20100102420 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate | 04-29-2010 |
20100148323 | IMPURITY INTRODUCING METHOD USING OPTICAL CHARACTERISTICS TO DETERMINE ANNEALING CONDITIONS - A subject of the present invention is to realize an impurity doping not to bring about a rise of a substrate temperature. Another subject of the present invention is to measure optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized. An impurity doping method, includes a step of doping an impurity into a surface of a solid state base body, a step of measuring an optical characteristic of an area into which the impurity is doped, a step of selecting annealing conditions based on a measurement result to meet the optical characteristic of the area into which the impurity is doped, and a step of annealing the area into which the impurity is doped, based on the selected annealing conditions. | 06-17-2010 |
20100213582 | GLASS-BASED SOI STRUCTURES - Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer ( | 08-26-2010 |
20100224968 | HIGH RESISTIVITY SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME - This method for manufacturing a high resistivity silicon wafer includes pulling a single crystal such that the single crystal has a p-type dopant concentration at which a wafer surface resistivity becomes in a range of 0.1 to 10 kΩcm, an oxygen concentration Oi of 5.0×10 | 09-09-2010 |
20100295159 | Method for Formation of Tips - The present invention provides a method ( | 11-25-2010 |
20100308446 | SEMICONDUCTOR DEVICE - The first layer is located on the first electrode and has the first conductivity type. The second layer is located on the first layer and has the second conductivity type. The third layer is located on the second layer. The second electrode is located on the third layer. The fourth layer is located between the second layer and the third layer, and has the second conductivity type. The third layer includes the first portion and the second portion. The first portion has the second conductivity type and has a peak value of an impurity concentration higher than the peak value of the impurity concentration in the second layer. The second portion has the first conductivity type. The area of the second portion accounts for not less than 20% and not more than 95% of the total area of the first portion and the second portion. | 12-09-2010 |
20110042791 | METHOD FOR TREATING AN OXYGEN-CONTAINING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR COMPONENT - A method for treating an oxygen-containing semiconductor wafer, and semiconductor component. One embodiment provides a first side, a second side opposite the first side. A first semiconductor region adjoins the first side. A second semiconductor region adjoins the second side. The second side of the wafer is irridated such that lattice vacancies arise in the second semiconductor region. A first thermal process is carried out the duration of which is chosen such that oxygen agglomerates form in the second semiconductor region and that lattice vacancies diffuse from the first semiconductor region into the second semiconductor region. | 02-24-2011 |
20110068440 | Multi-Angle Rotation for Ion Implantation of Trenches in Superjunction Devices - A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall. | 03-24-2011 |
20110121437 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone. | 05-26-2011 |
20110133314 | METHOD FOR PRODUCING A SEMICONDUCTOR WAFER - A method for producing a semiconductor wafer includes pulling a single crystal of semiconductor material, slicing a semiconductor wafer from the single crystal and polishing the semiconductor wafer with the polishing pad and polishing agent. The polishing agent is free of solid materials having abrasive action and the polishing pad contains fixedly bonded solid materials with abrasive action. During polishing the polishing agent is supplied in a gap between the semiconductor wafer and polishing pad. The polishing agent has a pH value in a range of 9.5 to 12.5. | 06-09-2011 |
20110140246 | DELTA-DOPING AT WAFER LEVEL FOR HIGH THROUGHPUT, HIGH YIELD FABRICATION OF SILICON IMAGING ARRAYS - Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH | 06-16-2011 |
20110278702 | METHOD FOR PRODUCING A DOPANT PROFILE - A method for producing a dopant profile is provided. The method includes starting from a surface of a wafer-shaped semiconductor component by introducing dopant atoms into the semiconductor component. The dopant-containing layer is produced on or in a region of the surface in order to produce a provisional first dopant profile and then a plurality of semiconductor components having a corresponding layer is subjected to heat treatment on top of one another in the form of a stack in order to produce a second dopant profile having a greater depth in comparison to the first dopant profile. | 11-17-2011 |
20110298100 | SEMICONDUCTOR DEVICE PRODUCING METHOD AND SEMICONDUCTOR DEVICE - Disclosed are a semiconductor device producing method and a semiconductor device. The semiconductor device producing method is comprised of a step of forming a diffusion suppressing mask composed of at least two of a thick film portion, an opening portion, and a thin film portion, on a surface of a semiconductor substrate; a step of applying dopant diffusing agents containing dopants to the entirety of a surface of the diffusion suppression mask; and a step of diffusing the dopants obtained from the dopant diffusing agents onto the surface of the semiconductor substrate. In the semiconductor device, a high concentration first conductive dopant diffusion layer, a high concentration second conductive dopant diffusion layer, a low concentration first conductive dopant diffusion layer, and a low concentration second conducive dopant diffusion layer are provided on one of the surfaces of the semiconductor substrate. | 12-08-2011 |
20110316128 | Semiconductor Wafers Of Silicon and Method For Their Production - Semiconductor wafers of silicon are produced by pulling a single crystal growing on a phase boundary from a melt contained in a crucible and cutting of semiconductor wafers therefrom, wherein during pulling of the single crystal, heat is delivered to a center of the phase boundary and a radial profile of a ratio V/G from the center to an edge of the phase boundary is controlled, G being the temperature gradient perpendicular to the phase boundary and V being the pull rate. The radial profile of the ratio V/G is controlled so that the effect of thermomechanical stress in the single crystal adjoining the phase boundary, is compensated with respect to creation of intrinsic point defects. The invention also relates to defect-free semiconductor wafers of silicon, which can be produced economically by this method. | 12-29-2011 |
20120018856 | Semiconductor Device With Drift Regions and Compensation Regions - Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type. | 01-26-2012 |
20120146197 | Integrated Devices on a Common Compound Semiconductor III-V Wafer - A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs. | 06-14-2012 |
20120193769 | SILICON SUBSTRATES WITH DOPED SURFACE CONTACTS FORMED FROM DOPED SILICON INKS AND CORRESPONDING PROCESSES - The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells. | 08-02-2012 |
20120267767 | SEMICONDUCTOR OVERLAPPED PN STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities. | 10-25-2012 |
20120313225 | INTEGRATED CIRCUIT HAVING DOPED SEMICONDUCTOR BODY AND METHOD - An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced into the semiconductor body. | 12-13-2012 |
20130026611 | SEMICONDUCTOR SUBSTRATE INCLUDING DOPED ZONES FORMING P-N JUNCTIONS - A semiconductor substrate ( | 01-31-2013 |
20130049173 | WAFER STRUCTURE FOR ELECTRONIC INTEGRATED CIRCUIT MANUFACTURING - A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits. | 02-28-2013 |
20130049174 | WAFER STRUCTURE FOR ELECTRONIC INTEGRATED CIRCUIT MANUFACTURING - A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits. | 02-28-2013 |
20130049175 | WAFER STRUCTURE FOR ELECTRONIC INTEGRATED CIRCUIT MANUFACTURING - A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits. | 02-28-2013 |
20130049176 | METHOD FOR PRODUCING A SEMICONDUCTOR - A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction. | 02-28-2013 |
20130069208 | Group III-V Device Structure Having a Selectively Reduced Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 03-21-2013 |
20130069209 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device and a method for manufacturing the semiconductor device are provided. A semiconductor substrate has a surface on which an abrasion trace is formed, and a dopant diffusion region includes a portion extending in the direction at an angle within the range of −5° to +5° with respect to the direction in which the abrasion trace extends | 03-21-2013 |
20130075877 | SEMICONDUCTOR DEVICE HAVING LATERAL ELEMENT - A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×10 | 03-28-2013 |
20130093065 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer. | 04-18-2013 |
20130113087 | SEMICONDUCTOR COMPONENT - A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity. | 05-09-2013 |
20130119522 | Semiconductor Device and Substrate with Chalcogen Doped Region - A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first side to a depth into the semiconductor material and includes chalcogen dopant atoms which provide a base doping concentration for the first region. The second region extends from the first region to the second side and is devoid of base doping. Further, a power semiconductor component is provided. | 05-16-2013 |
20130154065 | PROCESS FOR TREATING A SUBSTRATE USING A LUMINOUS FLUX OF DETERMINED WAFELENGTH, AND CORRESPONDING SUBSTRATE - A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer, layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and grows as the temperature rises. The luminous flux may be applied in several places of the surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer. | 06-20-2013 |
20130175674 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a p-type doped layer, an n-type doped layer, and an internal electrical connection layer that is deposited and electrically coupled between the p-type doped layer and the n-type doped layer. In one embodiment, the internal electrical connection layer includes a group IV element and a nitrogen element, and the number of atoms of the group IV element and the nitrogen element is greater than 50% of the total number of atoms in the internal electrical connection layer. In another embodiment, the internal electrical connection layer includes carbon element with a concentration greater than 10 | 07-11-2013 |
20130214395 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone. | 08-22-2013 |
20130221498 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a trench gate structure is formed by self alignment. The manufacturing method of the semiconductor device includes: forming a control electrode in an interior of trenches, etching a semiconductor layer between adjacent trenches to form an opening having a depth that is about level with an upper end of the control electrode with a portion of the semiconductor layer remaining between the opening and the control electrode, forming a first semiconductor region of the second conductive type from the surface of the semiconductor layer to a depth above the lower end of the control electrode, forming a single crystallized conductive layer from the first semiconductor region and the portion of the semiconductor layer, and forming a second semiconductor region, the second semiconductor region including the portion of the semiconductor layer and the single crystallized portion of the conductive layer. | 08-29-2013 |
20130228902 | SEMICONDUCTOR LAMINATE, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREOF - Provided is a method for manufacturing a semiconductor device. Also provided are: a semiconductor device which can be obtained by the method; and a dispersion that can be used in the method. A method for manufacturing a semiconductor device ( | 09-05-2013 |
20130228903 | Method of Producing a Vertically Inhomogeneous Platinum or Gold Distribution in a Semiconductor Substrate and in a Semiconductor Device - Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer. | 09-05-2013 |
20130256846 | Semiconductor Overlapped PN Structure and Manufacturing Method Thereof - The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities. | 10-03-2013 |
20130299954 | COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer. | 11-14-2013 |
20130320511 | SEMICONDUCTOR DEVICE - A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure. | 12-05-2013 |
20130320512 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body. The method further includes doping a part of the semiconductor body via sidewalls of the trench by plasma doping. | 12-05-2013 |
20140021590 | Method of Manufacturing Semiconductor Devices Using Ion Implantation - A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics. | 01-23-2014 |
20140027886 | METHOD OF FABRICATING A DEVICE WITH A CONCENTRATION GRADIENT AND THE CORRESPONDING DEVICE - A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate. | 01-30-2014 |
20140042598 | COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer. | 02-13-2014 |
20140061875 | SEMICONDUCTOR DEVICE - According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode. | 03-06-2014 |
20140070377 | COMPOUND SEMICONDUCTOR EPITAXIAL STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer. | 03-13-2014 |
20140070378 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND APPARATUS FOR FABRICATING A SEMICONDUCTOR DEVICE - An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device, including measuring a physical amount related to an impurity concentration of a semiconductor wafer having a first thickness, deciding a second thickness of the semiconductor wafer based on a measurement value of the physical amount, the second thickness being thinner than the first thickness, and reducing the first thickness of the semiconductor wafer to approximately the same thickness as the second thickness. | 03-13-2014 |
20140070379 | Diode and Power Conversion System - A diode includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of a second conductive type arranged adjoining to the first semiconductor layer; a third semiconductor layer of the first conductive type arranged on a side, opposite to the second semiconductor layer, of the first semiconductor layer, and contains a dopant of the first conductive type at a higher concentration than the first semiconductor layer; a first electrode ohmically connected to the second semiconductor layer; a second electrode ohmically connected to the third semiconductor layer; and a fourth semiconductor layer arranged at a position adjoining to the third semiconductor layer between the first and third semiconductor layers, contains a dopant of a type being the same as a type of the dopant of the first conductive type contained in the third semiconductor layer, and has a carrier lifetime shorter than the third semiconductor layer. | 03-13-2014 |
20140117512 | SURFACE PROFILE FOR SEMICONDUCTOR REGION - One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region. | 05-01-2014 |
20140117513 | Production and Distribution of Dilute Species in Semiconducting Materials - Technologies are described effective to implement systems and methods of producing a material. The methods comprise receiving a tertiary semiconductor sample with a dilute species. The sample has two ends. The first end of the sample includes a first concentration of the dilute species lower than a second concentration of the dilute species in the second end of the sample. The method further comprises heating the sample in a chamber. The chamber has a first zone and a second zone. The first zone having a first temperature higher than a second temperature in the second zone. The sample is orientated such that the first end is in the first zone and the second end is in the second zone. | 05-01-2014 |
20140124904 | EPITAXIAL LAYER AND METHOD OF FORMING THE SAME - A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer. | 05-08-2014 |
20140151858 | INCREASING THE DOPING EFFICIENCY DURING PROTON IRRADIATION - A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion. | 06-05-2014 |
20140175619 | STRIPLINE AND REFERENCE PLANE IMPLEMENTATION FOR INTERPOSERS USING AN IMPLANT LAYER - An integrated circuit system includes an interposer substrate with an electrical reference plane, or “ground plane,” formed by a conductive semiconductor layer. The conductive semiconductor layer may be formed in a surface region of the interposer substrate, and in some embodiments is formed by performing an ion implant process on the surface region to increase the electrical conductivity of the surface region. Because the surface region is electrically coupled to an electrical ground of the integrated circuit system, the surface region functions as a ground plane that helps contain electric fields produced by signals routed through interconnects of the interposer substrate. Consequently, a ground plane can be formed on a surface of the interposer substrate without forming a metalization layer. | 06-26-2014 |
20140175620 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, the method including: forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate. | 06-26-2014 |
20140231969 | SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned. | 08-21-2014 |
20140284774 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone. | 09-25-2014 |
20140306326 | Tunable Semiconductor Component Provided with a Current Barrier - Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source. | 10-16-2014 |
20150014825 | ESD PROTECTION DEVICE - An ESD protection device includes a substrate having a first conductive type. A doped well having a second conductive type is disposed in the substrate. A first doped region having the first conductive type is disposed in the doped well. A second doped region having the first conductive type is disposed in the substrate, wherein part of the second doped region is in the doped well, and the remaining part of the second doped region is separate from the doped well. A front terminal electrically connects the first doped region. A back terminal is disposed on a back side of the substrate. | 01-15-2015 |
20150014826 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a second electrode opposite to a first electrode, a first semiconductor layer provided above the first electrode, the first semiconductor layer having first semiconductor regions of a first conductivity type alternating with second semiconductor regions of a second conductivity type in a direction generally parallel to the first electrode A second semiconductor layer of the second conductivity type is provided on the first semiconductor layer Third extend into the first semiconductor layer from the second semiconductor layer. At least one first semiconductor region includes a first portion containing hydrogen ions and a second portion between the first portion and the second semiconductor layer that has a dopant concentration lower than that of the first portion. | 01-15-2015 |
20150021747 | DIODE - A p-type anode layer ( | 01-22-2015 |
20150041965 | Power Semiconductor Device and Method - A power semiconductor device includes a semiconductor body having a first side, a second side opposite the first side and an outer rim. The semiconductor body includes an active region, an edge termination region arranged between the active region and the outer rim, a first doping region in the active region and connected to a first electrode arranged on the first side, a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side, a drift region between the first doping region and the second doping region, the drift region including a first portion adjacent to the first side and a second portion arranged between the first portion and the second doping region, and an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region. | 02-12-2015 |
20150041966 | Methods and Systems for Dopant Activation Using Microwave Radiation - Systems and methods are provided for activating dopants in a semiconductor structure. For example, a semiconductor structure including a plurality of dopants is provided. One or more microwave-absorption materials are provided, the microwave-absorption materials being capable of increasing an electric field density associated with the semiconductor structure. Microwave radiation is applied to the microwave-absorption materials and the semiconductor structure to activate the plurality of dopants for fabricating semiconductor devices. The microwave-absorption materials are configured to increase the electric field density in response to the microwave radiation so as to increase the semiconductor structure's absorption of the microwave radiation to activate the dopants. | 02-12-2015 |
20150048489 | EDGE TERMINATION TECHNIQUE FOR HIGH VOLTAGE POWER DEVICES - Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same are disclosed. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (e.g., trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device. | 02-19-2015 |
20150108620 | Superjunction Semiconductor Device and Method for Producing Thereof - A method of forming a superjunction device includes forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a semiconductor mesa region adjoining the at least one trench. A second semiconductor layer is formed at least on sidewalls and a bottom of the at least one trench. The second semiconductor layer is etched by filling the at least one trench with an etchant, and applying a voltage between the first semiconductor layer and the etchant such that a space charge region expands in the second semiconductor layer and in the first semiconductor layer. The voltage is adjusted such that there is a first region in the semiconductor mesa region that is free of the space charge region when the voltage is applied. | 04-23-2015 |
20150332921 | CARRIER CHANNEL WITH ELEMENT CONCENTRATION GRADIENT DISTRIBUTION AND FABRICATION METHOD THEREOF - The present disclosure provides a carrier channel with an element concentration gradient distribution. The carrier channel includes a substrate and a carrier channel structure. The carrier channel structure is stacked on the substrate, wherein a ratio of a height and a width of the carrier channel is greater than 1, and the carrier channel is crystallized from the contact surface by a rapid melting growth process, thus the carrier channel structure has the element concentration gradient distribution. | 11-19-2015 |
20150340447 | SURFACE PROFILE FOR SEMICONDUCTOR REGION - One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region. | 11-26-2015 |
20150349066 | Semiconductor Device, Silicon Wafer and Silicon Ingot - A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors. | 12-03-2015 |
20150371871 | Method of Reducing an Impurity Concentration in a Semiconductor Body, Method of Manufacturing a Semiconductor Device and Semiconductor Device - A method of reducing an impurity concentration in a semiconductor body includes irradiating the semiconductor body with particles through a first side of the semiconductor body. The method further includes removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C. | 12-24-2015 |
20160013278 | METHOD OF PRODUCING EPITAXIAL SILICON WAFER, EPITAXIAL SILICON WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE | 01-14-2016 |
20160056142 | SEMICONDUCTOR DEVICE - According to one embodiment, semiconductor device includes a first semiconductor region; a second semiconductor region; a first insulating layer; a second insulating layer; a third semiconductor region; and an interconnect layer. The second semiconductor region is provided on the first semiconductor region, and second semiconductor region is connected to the first semiconductor region. The first insulating layer surrounds a first portion of the second semiconductor region. The second insulating layer surrounds a second portion of the second semiconductor region. The third semiconductor region is provided on the second portion of the second semiconductor region, the third semiconductor region is connected to the second portion, and the third semiconductor region is surrounded by the second insulating layer. And the interconnect layer is provided on the second semiconductor region and the third semiconductor region, and the interconnect layer is electrically connected to the second semiconductor region and the third semiconductor region. | 02-25-2016 |
20160056247 | PROCESS FOR TREATING A SUBSTRATE USING A LUMINOUS FLUX OF DETERMINED WAVELENGTH, AND CORRESPONDING SUBSTRATE - A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and rises as the temperature rises. The luminous flux may be applied in several places of a surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer. | 02-25-2016 |
20160064206 | Method for Processing an Oxygen Containing Semiconductor Body - A method for processing a semiconductor body is disclosed. In an embodiment, the method includes reducing an oxygen concentration in a silicon wafer in a first region adjoining a first surface of the silicon wafer by a first heat treatment, creating vacancies in a crystal lattice of the wafer at least in a second region adjoining the first region by implanting particles via the first surface into the wafer and forming oxygen precipitates in the second region by a second heat treatment. | 03-03-2016 |
20160087049 | EPITAXIAL SILICON WAFER - An epitaxial silicon wafer includes: a silicon wafer; and a silicon epitaxial layer formed on the silicon wafer, in which a W concentration obtained by a metal analysis of a surface of the silicon epitaxial layer using an inductively coupled plasma mass spectrometry is 1×10 | 03-24-2016 |
20160104781 | INTEGRATED FLOATING DIODE STRUCTURE AND METHOD THEREFOR - In one embodiment, a floating diode structure includes a p-type semiconductor substrate. An n-type doped region is disposed between the semiconductor substrate and a p-type doped region of the first conductivity type adjacent the first doped region. An n-type cathode region is disposed within the p-type doped region and a p-type anode region is disposed within the cathode region. An anode electrode is connected to the anode region and a cathode electrode is connected to the cathode region. In one embodiment, the cathode electrode is further connected to the p-type doped region. The n-type doped region is configured as a floating region that facilitates the diode operating in both a forward and reverse bias mode and both below ground and above ground with respect to the p-type semiconductor substrate. | 04-14-2016 |
20160111289 | Semiconductor Device and Method for Forming a Semiconductor Device - A method includes forming an emitter at the first side of a semiconductor substrate by doping, wherein the dopant concentration is higher in the emitter than in the edge region; growing an oxide layer on the first side by annealing, wherein the oxide layer has a first thickness in a first region covering the emitter, and a second thickness in a second region covering the edge region. The first thickness is larger than the second thickness. Heavy metal ions are implanted through the first side with a first energy, and with a second energy, wherein the first energy and the second energy are different, such that the implanted heavy metal concentration in the edge region is higher than in the emitter due to an absorption of the oxide layer covering the emitter, resulting in a lower charge carrier lifetime in the edge region than in the emitter. | 04-21-2016 |
20160118466 | SEMICONDUCTOR CHIP ARRANGEMENT - A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier. | 04-28-2016 |
20160126099 | SILICON-BASED SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×10 | 05-05-2016 |
20160141369 | SEMICONDUCTOR AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern. Thus, the examples relate to a semiconductor and manufacture device with even doping, and high breakdown voltage obtainable as a result of such doping. | 05-19-2016 |
20160148964 | METHOD OF PRODUCING EPITAXIAL SILICON WAFER, EPITAXIAL SILICON WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE - Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. | 05-26-2016 |
20160172208 | CHEMICAL MECHANICAL PLANARIZATION TOPOGRAPHY CONTROL VIA IMPLANT | 06-16-2016 |
20160172447 | SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS | 06-16-2016 |
20190148500 | SEMICONDUCTOR DEVICE | 05-16-2019 |