Entries |
Document | Title | Date |
20080197463 | Electronic Component And Method For Manufacturing An Electronic Component - An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead. | 08-21-2008 |
20080197464 | Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device - A semiconductor device package ( | 08-21-2008 |
20080197465 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Variations in fastening positions of semiconductor elements are eliminated by forming protrusions on a die pad so as to enclose the semiconductor elements before an adhesive that fastens the semiconductor elements to the die pad is wetted and spread. | 08-21-2008 |
20080197466 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor chip; a plurality of pellet-like electrically conductive members connected to electrodes of the semiconductor chip; and an encapsulation resin that encapsulates the semiconductor chip and the electrically conductive members. The electrically conductive members are embedded into the encapsulation resin. Surfaces of the electrically conductive members are exposed from the encapsulation resin so that the electrically conductive members serve as external connection terminals of the semiconductor device. | 08-21-2008 |
20080203551 | MULTI-CHIP MODULE AND SINGLE-CHIP MODULE FOR CHIPS AND PROXIMITY CONNECTORS - A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure. | 08-28-2008 |
20080211070 | Flip chip contact (FCC) power package - This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames. | 09-04-2008 |
20080211071 | Memory IC Package Assembly Having Stair Step Metal Layer and Apertures - Disclosed is a low cost memory IC package assembly having a first metal layer bonded to the die and a dielectric insulating layer with circuits and with apertures to expose the first metal layer bonded thereto. | 09-04-2008 |
20080211072 | Testing and burn-in using a strip socket - A method and apparatus are provided for using a strip socket in testing or burn-in of semiconductor devices in a strip. In one example of the method, processing of semiconductor devices involves assembling the semiconductor devices into a strip, isolating a portion of each of the semiconductor devices of the strip, and performing operations on the strip using a strip socket, wherein the strip socket is designed to make electrical contact substantially simultaneously with each semiconductor device in the strip. | 09-04-2008 |
20080224287 | OPTOELECTRONIC DEVICE ALIGNMENT IN AN OPTOELECTRONIC PACKAGE - Using one or more reference indicators in die attaching an optoelectronic device to a lead during the assembly of an optoelectronic package. One example method of assembling an optoelectronic package includes detecting a reference indicator included in a first component of an optoelectronic package. The method also includes die attaching a second component to the optoelectronic package at a die attach location. The die attach location is substantially aligned with the reference indicator along a line that intersects the reference indicator and is parallel to either an x-axis or a y-axis of an x-y coordinate system associated with the optoelectronic package. | 09-18-2008 |
20080224288 | Portable Object Connectable Package - A portable object connectable package | 09-18-2008 |
20080224289 | Multi-chip stack structure and fabrication method thereof - A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented. | 09-18-2008 |
20080224290 | LOW COST LEAD-FREE PREPLATED LEADFRAME HAVING IMPROVED ADHESION AND SOLDERABILITY - A leadframe with a structure made of a base metal ( | 09-18-2008 |
20080230881 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD SUPPORT - An integrated circuit package system is provided including forming a paddle having an integrated circuit die thereover, an outer lead, and an inner lead between the paddle and the outer lead. The integrated circuit package system is also provided including placing a lead support over the inner lead without traversing to an inner body bottom side of the inner lead, connecting the integrated circuit die and the inner lead, and encapsulating the inner lead having the lead support thereover and the inner lead exposed. | 09-25-2008 |
20080230882 | CHIP PACKAGE STRUCTURE - A chip package structure includes a die pad of which at least a notch is formed on at least one side and opposite to a mold gate. The die pad contributes to accelerating the injection of an encapsulating material, so as to exhaust the air in the mold in time, before the encapsulating material solidifies during the molding step, thereby overcoming or at least improving the problem of defects such as air bubbles in the encapsulation. | 09-25-2008 |
20080237818 | METHODS AND APPARATUS FOR MULTI-STAGE MOLDING OF INTEGRATED CIRCUIT PACKAGE - Methods and apparatus for providing an integrated circuit using a multi-stage molding process to protect wirebonds. In one embodiment, a method includes attaching a die to a leadframe having a lead finger, attaching a wirebond between the die and the leadfinger, applying a first mold material over at least a portion of the wirebond and the die and the leadfinger to form an assembly, waiting for the first mold material to at least partially cure, and applying a second mold material over the assembly. | 10-02-2008 |
20080237819 | Bipolar Carrier Wafer and Mobile Bipolar Electrostatic Wafer Arrangement - The present invention relates to a bipolar carrier wafer and a mobile, bipolar electrostatic wafer arrangement. Carrier wafers and wafer arrangements of this type can be used in particular in the field of handling technology of semiconductor wafers. The carrier wafer according to the invention serves for mounting a disc-shaped semiconductor component. It has a first surface ( | 10-02-2008 |
20080246132 | Semiconductor device and method of manufacturing semiconductor device - This semiconductor device includes a semiconductor chip, and a lead arranged around the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to a package board, wherein a joint surface to the package board and an end surface orthogonal to the joint surface are formed on the end of the lead farther from the semiconductor chip, and a metal plating layer made of a pure metal is formed on the end surface. | 10-09-2008 |
20080251900 | Conductor Frame For an Electronic Component and Method For the Production Thereof - Disclosed is a leadframe for at least one electronic component, comprising at least two electrical lead elements, each of which comprises at least one electrical lead tab and at least one retention tab. Provided between the at least one retention tab and the lead element is a score defining a parallel offset between the retention tab and the adjacent region of lead element. An additional parallel offset is defined between the lead element and the electrical lead tab, such that the retention tab and the electrical lead tab are located in a common plane. The score enables the retention tab to be removed easily without the need for a disadvantageous punched gap between the lead element and the retention tab. | 10-16-2008 |
20080251901 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system is provided providing a lead frame having a die paddle, attaching a first integrated circuit on the die paddle of the lead frame, connecting first electrical interconnects between the first integrated circuit and the lead frame, encapsulating the first integrated circuit and the first electrical interconnects with the lead frame directly on a bottom mold and clamped by a top mold, attaching a second integrated circuit on the die paddle of the first integrated circuit, connecting second electrical interconnects between the second integrated circuit and the lead frame, and encapsulating the second integrated circuit and the second electrical interconnects. | 10-16-2008 |
20080251902 | Plastic package and method of fabricating the same - A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals. | 10-16-2008 |
20080258276 | Non-Leaded Semiconductor Package and a Method to Assemble the Same - A method to assemble a non-leaded semiconductor package ( | 10-23-2008 |
20080258277 | Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same - A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and external terminals to one another. | 10-23-2008 |
20080258278 | Partially patterned lead frames and methods of making and using the same in semiconductor packaging - A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation. | 10-23-2008 |
20080258279 | LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME - A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins. | 10-23-2008 |
20080258280 | Lead frame, semiconductor device using the lead frame, and methods of manufacturing the same - Provided are a lead frame, semiconductor device, and methods of manufacturing the same. The lead frame may include a die pad having at least three pair of sides parallel with each other, and a plurality of inner leads spaced apart from a circumference of the die pad, arranged in a radial shape with respect to a center of the die pad, and having the ends form inner lead connection surfaces parallel with at least one pair of sides of the die pad. In addition, there may be provided a semiconductor device having the lead frame. Accordingly, a semiconductor chip may be positioned on a die pad. The plurality of inner leads may be electrically connected to the semiconductor chip through wires. The semiconductor device may further include a molding resin for surrounding top and bottom surfaces of the lead frame and filling in an interior thereof. | 10-23-2008 |
20080265386 | SEMICONDUCTOR DEVICE - To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire. | 10-30-2008 |
20080277770 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame having an element support and a lead portion. The lead frame has an area from the element support to inner leads of the lead portion, which is formed flat. First and second semiconductor elements are stacked in order on a lower surface of the lead frame. Electrode pads of the first semiconductor element are connected to the inner leads via first metal wires. Ends of the first metal wires, which are connected to the first semiconductor element, are embedded in the second adhesive layer of the second semiconductor element. | 11-13-2008 |
20080283985 | CIRCUIT SUBSTRATE, MOLDING SEMICONDUCTOR DEVICE, TRAY AND INSPECTION SOCKET | 11-20-2008 |
20080290485 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RELIEF - An integrated circuit package system including: providing a die pad with a top, sides, and a bottom, the bottom having a relief with a flat surface and defining a wall and a center pad; mounting a barrier under the bottom of the die pad; mounting an integrated circuit die on the top of the die pad; encapsulating the integrated circuit die and the top and sides of the die pad with the wall preventing encapsulation from flowing along the barrier to reach the center pad; and mounting an external interconnect on the center pad. | 11-27-2008 |
20080290486 | LEADFRAME PACKAGE - A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads. | 11-27-2008 |
20080303125 | THREE-DIMENSIONAL PACKAGE STRUCTURE - A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The shielding layer is disposed between the control component and at least part of the magnetic body to inhibit or reduce EMI (Electro-Magnetic Interference) from the energy storage element and to get a tiny package structure. The three-dimensional package structure is applicable to a POL (Point of Load) converter. | 12-11-2008 |
20080303126 | MICROELECTROMECHANICAL SYSTEM PACKAGE AND THE METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a microelectromechanical system package is provided. A plurality of cavities is first formed on a surface of a silicon wafer. The surface of the silicon wafer is then bonded to the microelectromechanical system wafer in such a manner that the active areas of the chips on the microelectromechanical system wafer are corresponding to the cavities on the silicon wafer. The structure assembly of the two wafers is finally singulated to form individual microelectromechanical system chips whose active areas are covered by the cavities. In this way, the profile of the microelectromechanical system package may be reduced accordingly. | 12-11-2008 |
20080303127 | CAP-LESS PACKAGE AND MANUFACTURING METHOD THEREOF - A cap-less package comprises: a metallic die pad part; a submount mounted on the die pad part; an optical semiconductor element mounted on the submount; an insulating member fixed to the die pad part; a lead electrode inserted in the insulating member; and a wire connecting the lead electrode to the semiconductor optical element, wherein the submount, the optical semiconductor element, a portion of the lead electrode closer to the optical semiconductor element than to the insulating member, and the wire are located opposite the die pad part. | 12-11-2008 |
20080303128 | LEADFRAME WITH DIE PAD AND LEADS CORRESPONDING THERETO - A leadframe includes a die pad and a plurality of leads corresponding to the die pad. The die pad for supporting a die is formed with a plurality of sides, each of the sides having at least one recess portion and at least one protrusion portion. The leads are substantially coplanar to the die pad. The leads include a plurality of first leads and a plurality of second leads. The first leads extend into the recess portions respectively, and the second leads are aligned with the protrusion portions. The length of the first leads is greater than that of the second leads. The length of wires electrically connecting the die to the leads or the die pad can be adjusted by the sides of the leadframe with the recess portion and the protrusion portion having a dimension corresponding to the leads, so as to save the manufacture cost of the leadframe. | 12-11-2008 |
20080308917 | EMBEDDED CHIP PACKAGE - An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure. | 12-18-2008 |
20080315380 | INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING PERIMETER PADDLE - An integrated circuit package system comprising: forming a paddle having a hole and an external interconnect; mounting an integrated circuit device having an active side to the paddle with the active side facing the paddle and the hole; connecting a first internal interconnect between the active side and the external interconnect through the hole; and encapsulating the integrated circuit device, the paddle, the first internal interconnect, and the external interconnect with the external interconnect partially exposed. | 12-25-2008 |
20080315381 | Lead frame, semiconductor device using same and manufacturing method thereof - The present invention provides a semiconductor device which comprises a lead frame including a die pad having one or two or more openings, a substrate mounted over the die pad so as to expose a plurality of semiconductor chip connecting second electrode pads from the openings of the die pad, a plurality of semiconductor chips mounted over the die pad and the substrate, bonding wires that connect chip electrode pads of the semiconductor chip and their corresponding semiconductor chip connecting first and second electrode pads of the substrate, and a sealing portion which covers these and is provided so as to expose parts of leads. | 12-25-2008 |
20080315382 | MULTIPLE DIE INTEGRATED CIRCUIT PACKAGE - A multiple die package and removable storage card is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be electrically coupled via anisotropically conductive areas of the leadframes. | 12-25-2008 |
20090001533 | MULTI-CHIP PACKAGING IN A TSOP PACKAGE - A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include a leadframe having one or more semiconductor die and one or more passive components affixed thereon. The one or more passive components may be affixed by soldering with a solder material. In embodiments, in order to prevent bleeding of the solder material during a solder reflow process, barricades are formed on the surface of the leadframe, at least partially surrounding the one or more passive components. | 01-01-2009 |
20090001534 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 01-01-2009 |
20090001535 | Semiconductor Module for a Switched-Mode Power Supply and Method for Its Assembly - Semiconductor module for a Switched-Mode Power Supply comprises at least one semiconductor power switch, a control semiconductor chip and a leadframe comprising a die pad and a plurality of leads disposed on one side of the die pad. The die pad comprises at least two mechanically isolated regions wherein the semiconductor power switch is mounted on a first region of the die pad and the control semiconductor chip is mounted on a second region of the die pad. Plastic housing material electrically isolates the first region and the second region of the die pad and electrically isolates the semiconductor power switch from the control semiconductor chip. | 01-01-2009 |
20090001536 | Electronic Component and a Method of Fabricating an Electronic Component - An electronic component includes a lead frame assembly, an insert, a semiconductor chip and an encapsulation compound. The lead frame assembly includes a mounting hole, a die pad, a plurality of bonding fingers and a plurality of lead fingers. The insert includes a hollow center and is provided at the mounting hole of the lead frame assembly. The semiconductor chip is arranged on the die pad and includes contact areas on its surface. A plurality of electrical contacts respectively links the contact areas of the semiconductor chip to the bonding fingers of the lead frame assembly. An encapsulating compound encloses the insert, the semiconductor chip, and the electrical contacts, however, leaves the hollow center of the insert uncovered. | 01-01-2009 |
20090008755 | STRUCTURE AND METHOD FOR MANUFACTURING SMD DIODE FRAME - A structure of an SMD (surface mount device) diode frame is provided that comprises a plastic seat and a plurality of metal pins. One side of the plastic seat has a concave functional area and the other side of the plastic seat corresponding to the functional area has a plurality of concave reserved holes. The functional area and the reserved holes are respectively formed via a forming bolt and a positioning bolt in a mold. If the forming bolt and the positioning bolt abut against the metal pins respectively, the preciseness of the size of the functional area is increased and the overflow of the material of the plastic seat is decreased. Furthermore, the yield of the manufacturing processes is improved. | 01-08-2009 |
20090008756 | Multi-Chip Electronic Package with Reduced Stress - An electronic component includes lead fingers and a die paddle. A tape pad is mounted below the lead fingers and the die paddle. A first semiconductor chip is bonded onto the tape pad by a layer of first adhesive and a second semiconductor chip is bonded onto the die paddle by a layer of second adhesive. Electrical contacts are disposed between the contact areas of the semiconductors chips and the lead fingers. An encapsulating compound covers part of the lead fingers, the tape pad, the semiconductor chips and the electrical contacts. | 01-08-2009 |
20090008757 | METHOD OF FABRICATING SUBSTRATE FOR PACKAGE OF SEMICONDUCTOR LIGHT-EMITTING DEVICE - In the invention, a substrate and fabrication thereof for a package of at least one semiconductor device, such as semiconductor light-emitting devices, are disclosed. In particular, a base together with a frame supporting the base of the substrate according to the invention is formed of a thick-walled metal material, a special-shaped metal plate or a normal-shaped metal plate. The at least one semiconductor device is to mounted on a top surface of the base. Moreover, the base serves as a heat sink. | 01-08-2009 |
20090008758 | USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE - A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length. | 01-08-2009 |
20090008759 | Semiconductor device, lead frame, and manufacturing method for the lead frame - Provided is a semiconductor device having an element covered with a resin mold and a metal lead protruding from the resin mold in which a lead-tip portion thereof is entirely covered by solder plating and in which a lead-tip end surface, which is not covered by solder plating, has an area less than half of a cross-sectional area of the metal lead, whereby solder wettability of the metal lead is improved and a bonding strength to a circuit board is also improved. | 01-08-2009 |
20090014851 | FUSION QUAD FLAT SEMICONDUCTOR PACKAGE - A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body. | 01-15-2009 |
20090014852 | Flip-Chip Packaging with Stud Bumps - A method for forming a package structure is provided. The method includes providing a semiconductor die; providing a package substrate; forming stud bumps on the package substrate; and bonding the semiconductor die to the package substrate, wherein the stud bumps electrically connect the semiconductor die and the package substrate. | 01-15-2009 |
20090014853 | Integrated circuit package for semiconductior devices with improved electric resistance and inductance - A semiconductor integrated circuit package having a leadframe ( | 01-15-2009 |
20090014854 | Lead frame, semiconductor package including the lead frame and method of forming the lead frame - Provided are a lead frame and a semiconductor package including the same. The lead frame includes a first lead frame portion including a plurality of first leads; an adhesive member disposed such that the first leads are adhered to one surface of the adhesive member; and a second lead frame portion including a plurality of second leads disposed such that the second leads are adhered to the other surface of the adhesive member, wherein the second leads are arranged so as not to overlap with the first leads. The lead frame may optionally include a die pad on which a semiconductor chip is installed. | 01-15-2009 |
20090020861 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 01-22-2009 |
20090020862 | DEVICE STRUCTURE WITH PREFORMED RING AND METHOD THEREFOR - A device structure with preformed ring includes a sensor chip and a ring disposed and surrounded on periphery of sensitive area of an active surface thereof. The device structure with preformed ring may batchly bind and electrically connect to a carrier by a way of two-dimension array, and then a packaging process is performed. During the packaging process, the top portion of the ring can be used to against the inner side of a packaging mold, so as to stop the packaging material covering the device at outside of the ring and stick with the ring. Therefore, an opening is formed on the sensitive area surface of the device. Depending on the ring, the extra process for eliminating the packaging material on the sensitive area surface can be avoided in the conventional process. | 01-22-2009 |
20090026591 | SEMICONDUCTOR PACKAGE ADAPTED FOR HIGH-SPEED DATA PROCESSING AND DAMAGE PREVENTION OF CHIPS PACKAGED THEREIN AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball. | 01-29-2009 |
20090026592 | SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle. | 01-29-2009 |
20090026593 | THIN SEMICONDUCTOR DIE PACKAGES AND ASSOCIATED SYSTEMS AND METHODS - Thin semiconductor die packages and associated systems and methods are disclosed. A package in accordance with a particular embodiment includes a semiconductor die having die bond sites, a conductive structure positioned proximate to the semiconductor die and having first bond sites and second bond sites spaced apart from the first bond sites, and conductive couplers connected between the first bond sites of the conductive structure and the die bond sites of the semiconductor die. A cover can be positioned adjacent to the semiconductor die, and can include a recess in which the conductive couplers are received. | 01-29-2009 |
20090026594 | Thin Plastic Leadless Package with Exposed Metal Die Paddle - A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips. | 01-29-2009 |
20090026595 | SEMICONDUCTOR DEVICE PACKAGE - A surface of a lead frame of a semiconductor device package, on which a semiconductor chip is mounted, is formed to have a mesh structure, whereby a connecting area between the lead frame and a molding resin can be increased to have strong bonding. Further, only filler particles having a small diameter than the mesh are taken into the vicinity of the lead frame, suppressing the effect of stresses to reduce deformation of the lead frame. | 01-29-2009 |
20090026596 | LEAD FRAME, SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - In certain embodiments, a lead frame includes a paddle, a plurality of inner leads, first outer leads, and a second outer lead. The plurality of inner leads can be arranged at a side face of the paddle. The first outer leads can extend from the inner leads along a first direction and can be arranged at a substantially central portion of the side face of the paddle. Furthermore, each of the first outer leads can have a first area. The second outer lead can be arranged at an edge portion of the side face of the paddle and can be supported by the paddle. The second outer lead can have a second area that is larger than the first area. | 01-29-2009 |
20090026597 | STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM - A stacked integrated circuit leadframe package system including forming a leadframe, packaging a top integrated circuit on a one side of the leadframe, packaging a bottom integrated circuit on an opposite side of the leadframe, and forming external electrical interconnects on the leadframe. | 01-29-2009 |
20090032918 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICES - An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated circuit device over the die-attach paddle; attaching an external interconnect under the outer interconnect; and attaching a circuit device under the die-attach paddle and extended laterally beyond opposite sides of the die-attach paddle. | 02-05-2009 |
20090032919 | Semiconductor device and lead frame - A semiconductor device which can surely prevent a wire bonded to an island from breaking due to, for instance, thermal shock and temperature cycle upon mounting. The semiconductor device includes a semiconductor chip; an island die bonded with the semiconductor chip on the surface; and a wire for electrically connecting the electrode formed on the surface of the semiconductor chip with the island. The semiconductor device is further characterized in that the island has a die bonding region where the semiconductor chip is die bonded, a wire bonding region where the wire is wire bonded, and a continuous groove reaching a circumference of the island are formed between the die bonding region and the wire bonding region of the island. | 02-05-2009 |
20090032920 | LASER RELEASE PROCESS FOR VERY THIN SI-CARRIER BUILD - A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided. | 02-05-2009 |
20090032921 | PRINTED WIRING BOARD STRUCTURE AND ELECTRONIC APPARATUS - According to one embodiment, a printed wiring board structure includes first and second semiconductor packages each including a substrate, and a printed wiring board including first and second component mounting surfaces having a relationship given as front and back surfaces and an inter-chip connection part provided at one portion thereof, the inter-chip connection part being provided with a plurality of arrayed through conductors penetrating through the first and second component mounting surfaces, wherein the substrates of the first and second semiconductor packages are arranged on the printed wiring board in a positional relationship such that the substrates mounted on the component mounting surfaces are partially overlapped via the printed wiring board, the external connection electrodes provided on the substrates are arrayed on the overlapped portion and are conductively connected to the through conductors arrayed in the inter-chip connection part. | 02-05-2009 |
20090032922 | Semiconductor Package, Printed Wiring Board Structure and Electronic Apparatus - According to one embodiment, a semiconductor package comprises a substrate having one surface mounted with a semiconductor chip, and the other surface mounted with a plurality of arrayed external connection electrodes, a differential line pair provided on the surface of the substrate mounted with the semiconductor chip, and making a connection between the semiconductor chip and a predetermined pair of electrodes included in the external connection electrodes, and a coupling capacitor pair inserted between the differential lines. | 02-05-2009 |
20090032923 | METHOD AND APPARATUS FOR STACKING ELECTRICAL COMPONENTS USING VIA TO PROVIDE INTERCONNECTION - An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces. | 02-05-2009 |
20090039484 | Semiconductor device with semiconductor chip and method for producing it - A semiconductor chip has at least one first contact and one second contact on its top side and has connecting elements which are arranged jointly on a structure element and which connect the first contact and the second contact of the top side of the semiconductor chip to the external contacts. | 02-12-2009 |
20090039485 | THERMALLY ENHANCED BALL GRID ARRAY PACKAGE FORMED IN STRIP WITH ONE-PIECE DIE-ATTACHED EXPOSED HEAT SPREADER - Methods, systems, and apparatuses for integrated circuit packages, such as ball grid array packages, and processes for assembling the same, are provided. A first strip includes an array of package substrate sections. An IC die is mounted to each package substrate section of the first strip. A second strip includes an array of leadframe sections. The second strip is positioned adjacent to the first strip to couple a planar protruding area of each leadframe section to a corresponding IC die mounted to the first strip. An encapsulating material is applied to the adjacently positioned first and second strips to fill a space between the first and second strips and to fill a cavity in a top surface of each leadframe section. A planar region of the first strip surrounding each centrally located cavity is not covered by the encapsulating material. The adjacently positioned first and second strips are singulated into a plurality of IC packages. | 02-12-2009 |
20090039486 | CIRCUIT MEMBER, MANUFACTURING METHOD FOR CIRCUIT MEMBERS, SEMICONDUCTOR DEVICE, AND SURFACE LAMINATION STRUCTURE FOR CIRCUIT MEMBER - A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed. | 02-12-2009 |
20090039487 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a source frame having a die pad; a linear gate frame having a bonding pad; a semiconductor chip mounted on the die pad; wires which electrically connect a source terminal of the semiconductor chip to the die pad and electrically connect a gate terminal of the semiconductor chip to the bonding pad; and resin which seals the die pad, the bonding pad, the semiconductor chip, and the wires. The die pad is spaced from the bonding pad and diagonal to an extending direction of the gate frame, in the vicinity of the bonding pad. | 02-12-2009 |
20090039488 | Semiconductor package and method for fabricating the same - A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant. | 02-12-2009 |
20090045493 | SEMICONDUCTOR COMPONENT AND METHOD OF PRODUCING - A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial bonding area. The constraints of the standard package dimensions and the component assembly method are taken into account. | 02-19-2009 |
20090051019 | Multi-chip module package - A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers. | 02-26-2009 |
20090051020 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor memory device includes: A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of:
| 02-26-2009 |
20090051021 | SEMICONDUCTOR CHIP STACK-TYPE PACKAGE AND METHOD OF FABRICATING THE SAME - Embodiments of the inventive concept provide a semiconductor chip stack-type package. The package comprises a lead frame including a die paddle part and a lead part, a first semiconductor chip group and a second semiconductor chip group stacked sequentially and mounted on one surface of the die paddle part, a first wiring board between the first semiconductor chip group and the second semiconductor chip group, and second semiconductor chip group bonding wires for electrically connecting the second semiconductor chip group to the first wiring board. End portions of the first wiring board are electrically connected to inner leads of the lead part, which is adjacent to the die paddle part. | 02-26-2009 |
20090057854 | SELF LOCKING AND ALIGNING CLIP STRUCTURE FOR SEMICONDUCTOR DIE PACKAGE - A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure. | 03-05-2009 |
20090057855 | SEMICONDUCTOR DIE PACKAGE INCLUDING STAND OFF STRUCTURES - A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure. The stand-off structures can support the conductive structure, and the conductive structure is attached to the second surface of the semiconductor die. | 03-05-2009 |
20090057856 | BONDING-PATTERNED DEVICE AND ELECTRONIC COMPONENT - A bonding-patterned device comprises: a bonding layer provided on a bonding surface to be bonded to a mounting member. The bonding-patterned device has a planar shape which is generally a parallelogram. The bonding-patterned device is separated and cut out from a plate material along a plurality of evenly spaced straight lines, the surface of the plate material provided with the bonding layer being partitioned into a plurality of compartments by a plurality of evenly spaced straight lines parallel to each of the two pairs of opposite sides of the generally parallelogram shape. The plurality of compartments are classified into first compartments and second compartments alternately arranged in a checkerboard configuration, where the bonding layer is provided inside the first compartments, and the bonding layer is not provided in the second compartments and on the contours thereof. x=2nα and y=(2m−1)β, or y=2nβ and x=(2m−1)α where x and y are the lengths of the two pairs of opposite sides of the generally parallelogram shape, α and β are the lengths of two pairs of opposite sides of the compartment parallel to said x and y, respectively, and n and m are natural numbers, planar shapes of each bonding layer provided inside each of the first compartments are congruent each other, and locations of each bonding layer in each of the first compartment are identical. | 03-05-2009 |
20090057857 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame according to one aspect of the present invention is used for a resin-sealed-type semiconductor device and includes a first lead frame having a frame body part and a lead part, and a second lead frame having a frame body part and a lead part. The lead part of the first lead frame and the lead part of the second lead frame do not contact with each other and an inner lead part formed in the lead part of the first lead frame and an inner lead part formed in the lead part of the second lead frame are provided in substantially the same plane when the frame body part of the first lead frame and the frame body part of the second lead frame are laminated together. | 03-05-2009 |
20090065914 | SEMICONDUCTOR DEVICE WITH LEADERFRAME INCLUDING A DIFFUSION BARRIER - A semiconductor device includes a leadframe having a first face and an opposing second face, a portion of the first face defining a die pad, a diffusion barrier deposited on at least a portion of the die pad, and at least one chip coupled to the diffusion barrier. | 03-12-2009 |
20090065915 | SINGULATED SEMICONDUCTOR PACKAGE - A semiconductor device includes a singulated semiconductor package having a leadframe, a chip electrically coupled to the leadframe, encapsulating material covering the chip and a portion of the leadframe, and a material layer disposed over opposing ends of the leadframe. The leadframe includes a first face and an opposing second face, the first and second faces extending between opposing ends of the leadframe, where the second face configured to electrically couple with a circuit board. The chip is electrically coupled to the first face. The encapsulating material covers the chip and the first face of the leadframe. The material layer is configured to improve solderability of the singulated semiconductor package to the circuit board. | 03-12-2009 |
20090065916 | SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING - A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support. | 03-12-2009 |
20090072363 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH LEADS - An integrated circuit package-in-package system includes: forming an integrated circuit package system including: connecting a first integrated circuit die and a lead, and forming an inner encapsulation covering the first integrated circuit die and a portion of the lead; mounting a second integrated circuit die to the integrated circuit package system; connecting the second integrated circuit die and the lead; and forming a package encapsulation covering the integrated circuit package system and the second integrated circuit die with the lead exposed. | 03-19-2009 |
20090072364 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADS SEPARATED FROM A DIE PADDLE - An integrated circuit package system is provided including forming a leadframe having a frame and a die paddle having leads thereon. The leads are held with respect to the die paddle. The leads are separated from the die paddle, and a die is attached to the die paddle. Bond wires are bonded between the leads and the die. The die and bond wires are encapsulated. The leadframe is singulated to separate the frame and the die paddle. | 03-19-2009 |
20090072365 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTERNAL INTERCONNECTS AT HIGH DENSITY - An integrated circuit package system includes: connecting an integrated circuit die and external interconnects; forming an encapsulation over the integrated circuit die and a portion of the external interconnects; and forming an isolation hole between the external interconnects and into a side of the encapsulation exposing the external interconnects. | 03-19-2009 |
20090072366 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY - An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side at an opposing side to the first side, surrounding the integrated circuit die with the terminal pad exposed at the first side and the external interconnect extending below the second side. | 03-19-2009 |
20090072367 | LEADFRAME - Particular embodiments of the present invention provide a leadframe suitable for use in packaging IC dice that enables stress reduction in and around the die, die attach material, die attach pad and mold interfaces. More particularly, various leadframes are described that include recesses in selected regions of the top surface of the die attach pad. | 03-19-2009 |
20090072368 | PACKAGE FOR MONOLITHIC COMPOUND SEMICONDUCTOR (CSC) DEVICES FOR DC TO DC CONVERTERS - A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame. | 03-19-2009 |
20090072369 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device. In the semiconductor device, a rectangular header with two mounting regions is folded, and two semiconductor chips are then fixed respectively to the mounting regions facing each other. Thereby, a stacked structure of the semiconductor chips is achieved while a mounting area of a package remains the same as the area for one semiconductor chip of a conventional type. Furthermore, characteristics of the two semiconductor chips can be obtained. Accordingly, compared with a case in which one semiconductor chip is used, on-resistance is decreased due to an increase in the number of transistor cells. Thereby, the semiconductor device can be driven at a low voltage. In addition, a larger current capacity can be achieved. Moreover, compared with a case in which two semiconductor chips are mounted next to each other on the header, a mounting area of a package outline can be reduced. | 03-19-2009 |
20090072370 | MULTILAYER WIRING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - There is provided a multilayer wiring substrate on which at least one semiconductor element is mounted. The multilayer wiring substrate includes: a baseboard; a first wiring layer formed on the baseboard and having a plurality of first wiring portions; an insulating layer formed on the baseboard; a second wiring layer formed on the insulating layer and having a plurality of second wiring portions, the second wiring portions being electrically connected to each other via a conductor wire, the conductor wire being arranged within the insulating layer three-dimensionally in a curved manner; and conductor portions configured to pass through the insulating layer and connecting the first wiring portions and the second wiring portions. | 03-19-2009 |
20090079049 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP - An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer on the backside of the semiconductor chip; and mounting the semiconductor chip over electrical interconnects. | 03-26-2009 |
20090079050 | AIR CAVITY PACKAGE FOR FLIP-CHIP - According to an example embodiment, there is method ( | 03-26-2009 |
20090079051 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The outflow of die bond material is prevented and the quality and the reliability of a semiconductor device are improved. A tab, a plurality of leads arranged around the tab, silver paste arranged on the chip supporting surface of the tab, and a semiconductor chip mounted via silver paste on the tab are included. Further, a plurality of wires which electrically connect a pad of the semiconductor chip, and a lead, and a sealing body which does the resin seal of the semiconductor chip and the wires are included. By forming a step part whose height is lower than the chip supporting surface in the edge part of the chip supporting surface of the tab, the silver paste protruded from the tab can be stopped to this step part. As a result, an outflow to the back surface of the sealing body of silver paste can be prevented. | 03-26-2009 |
20090085181 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DIE - An integrated circuit package system includes providing die; forming leads adjacent the die; forming a die paddle adjacent the leads with the die thereover; and forming a cavity for isolating one of the die and a die attach segment of the die paddle. | 04-02-2009 |
20090091012 | THERMOPLASTIC RESIN COMPOSITION FOR SEMICONDUCTOR, ADHESION FILM, LEAD FRAME, AND SEMICONDUCTOR DEVICE USING THE SAME, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - The object of the present invention is to provide an adhesion film for semiconductor that is capable of bonding a semiconductor chip to a lead frame tightly at an adhesion temperature lower than that of the adhesion film of a traditional polyimide resin without generation of voids and that can also be used for protection of lead frame-exposed area, a thermoplastic resin composition for semiconductor for use in the adhesive agent layer therein, and a lead frame having the adhesive film and a semiconductor device; and, to achieve the object, the present invention provides a thermoplastic resin composition for semiconductor, comprising a thermoplastic resin obtained in reaction of an amine component containing an aromatic diamine mixture (A) containing 1,3-bis(3-aminophenoxy)benzene, 3-(3′-(3″-aminophenoxy)phenyl)amino-1-(3′-(3″-aminophenoxy)phenoxy)benzene and 3,3′-bis(3″-aminophenoxy)diphenylether, and an acid component (C), an adhesion film for semiconductor using the same, a lead frame having the adhesion film and a semiconductor device using the same. | 04-09-2009 |
20090091013 | LEAD FRAME, ELECTRONIC COMPONENT INCLUDING THE LEAD FRAME, AND MANUFACTURING METHOD THEREOF - A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal. | 04-09-2009 |
20090096073 | SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME - A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. | 04-16-2009 |
20090096074 | Semiconductor device - Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming in contact partially with the semiconductor chip; a mounting material provided on a contact surface between each of the island and hanging leads and the semiconductor chip so as to adhere the semiconductor chip to the island and the hanging leads; and sealing resin for sealing the semiconductor chip. The modulus of elasticity of the mounting material is lower than that of the sealing resin. The mounting material is further coated on the back surfaces of the contact surfaces of the island and the hanging leads. | 04-16-2009 |
20090102031 | METHOD FOR CONNECTING A DIE ATTACH PAD TO A LEAD FRAME AND PRODUCT THEREOF - Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs. | 04-23-2009 |
20090102032 | Electronic Device - An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness. | 04-23-2009 |
20090102033 | INTEGRATED CIRCUIT PACKAGE - Package for an integrated circuit (IC), includes a housing ( | 04-23-2009 |
20090102034 | Packaged Microchip with Spacer for Mitigating Electrical Leakage Between Components - A packaged microchip has a base, at least one spacer coupled to the base, and first and second microchips mounted to the at least one spacer. The at least one spacer is configured to substantially prevent leakage current between the first and second microchips. | 04-23-2009 |
20090108424 | LEADFRAME FOR LEADLESS PACKAGE - A leadframe for a leadless package comprises a plurality of package areas, a plurality of first slots, a plurality of first side rails, a plurality of second side rails, and tape. Each of the package areas comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of first side rails and the plurality of second side rails are connected and surround the plurality of the package areas. The tape fixes the plurality of package areas, the plurality of first side rails, the plurality of second side rails, the die pads, and the plurality of leads in place. | 04-30-2009 |
20090115039 | High Bond Line Thickness For Semiconductor Devices - Die attach methods used in making semiconductor devices and the semiconductor devices resulting from those methods are described. The methods include providing a leadframe with a die attach pad, using boundary features to define a perimeter on the die pad, depositing a conductive material (such as solder) within the perimeter, and then bonding a die containing an integrated circuit to the die pad by using the conductive material. The boundary features allow an increased thickness of conductive material to be used, resulting in an increased bond line thickness and increasing the durability and performance of the resulting semiconductor device. | 05-07-2009 |
20090121330 | Clip Mount For Integrated Circuit Leadframes - A leadframe having a die thereon connects a high current conductive area on the die to a leadframe contact using copper clip that include a structure portion that is received with a recess-like “tub” that is formed in the leadframe contact which tub is shaped to conform to the geometric shape of the clip. In the preferred embodiment, a leadframe structure fabricated by etching includes at least one contact that is a half-etch recess or “tub” that receives one end of the clip structure and is retained in the tub by an adhesive. The end of the clip that is received in the tub is held in place during subsequent handling until the clip and leadframe undergo solder reflow to effect an electrical connection sufficient to handle the current load and a also effect a reliable mechanical connection. | 05-14-2009 |
20090121331 | Self-Aligning Structures and Method For Integrated Circuits - A lead frame having a die thereon connects a high current conductive area on the die to a lead frame contact using a copper clip that includes a structure portion that is received with a recess-like “tub” formed in the lead frame contact. In the preferred embodiment, a lead frame structure fabricated by etching includes at least one contact that is a half-etch recess or “tub” that receives one end of the clip structure and is retained in the tub by solder paste or an adhesive. The end of the clip that is received in the tub is held in place during subsequent handling until the clip and leadframe undergo solder reflow to effect an electrical connection sufficient to handle the current load and a also effect a reliable mechanical connection. One or more solder-holding pockets are formed a surface portion of the tub and/or the end of the clip that is received in the tub so that a volume of liquefied solder formed during the solder reflow step will effect alignment of any mis-aligned parts by “drawing” at least one of the parts against a “stop” surface. | 05-14-2009 |
20090121332 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring. | 05-14-2009 |
20090127682 | CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a chip package structure is provided. A metallic plate having a first surface, a second surface, and a first patterned metallic layer formed on the first surface thereof is provided. A half-etching process is performed to form first recesses on the first surface of the metallic plate, wherein leads are defined on the metallic plate by the first recesses. A first insulating material fills in each of the first recesses. A second patterned metallic layer is formed on the second surface of the metallic plate. A half-etching process is performed to form second recesses on the second surface of the metallic plate. The second recesses correspond to the first recesses, respectively, and expose the first insulating material inside the first recesses, such that the leads are electrically isolated from one another. A chip is placed on the metallic plate and electrically connected thereto. | 05-21-2009 |
20090127683 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INSULATOR - An integrated circuit package system includes: providing a connection array; attaching a base integrated circuit adjacent the connection array; attaching a package integrated circuit over the base integrated circuit; attaching a package die connector to the package integrated circuit and the connection array; and applying a wire-in-film insulator over the package integrated circuit, the package die connector, the base integrated circuit, and the connection array, wherein the connection array is partially exposed. | 05-21-2009 |
20090127684 | LEADFRAME FOR LEADLESS PACKAGE - A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, an insulating layer, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The insulating layer is filled in a plurality of slots between the package areas. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place. | 05-21-2009 |
20090127685 | Power Device Packages and Methods of Fabricating the Same - Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip. | 05-21-2009 |
20090140403 | ELECTRONIC DEVICE - Embodiments provide an electronic device including a leadframe, a chip attached to the leadframe, and encapsulation material disposed over a portion of the leadframe. The leadframe includes a first main face opposite a second main face and a plurality of edges extending between the first and second main faces. At least one of the plurality of edges includes a first profiled element and a second profiled element different than the first profiled element. The encapsulation material is disposed over the chip and the plurality of edges of the leadframe. | 06-04-2009 |
20090146278 | Chip-stacked package structure with asymmetrical leadframe - The present invention provides a chip-stacked package structure, comprising: a lead-frame, composed of a plurality of inner leads and a plurality of outer leads, wherein the inner leads comprise a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, and the ends of the first inner leads and the second inner leads are arranged opposite each other at a distance. The first inner leads is provided with a down-set structure, which results in different vertical heights of the position of the end of first inner leads and the position of the end of second inner leads. A chip-stacked package structure is then fixedly connected to the first inner leads, and the metallic bonding pads on the same side edge are electrically connected to the first inner leads and the second inner leads through a plurality of metal wires; and an encapsulant with a top surface and a bottom surface is provided to cover the chip-stacked package structure and the inner leads. | 06-11-2009 |
20090146279 | Method for attaching a semiconductor die to a leadframe, and a semiconductor device - A semiconductor device comprising a leadframe ( | 06-11-2009 |
20090146280 | CIRCUIT MEMBER, MANUFACTURING METHOD OF THE CIRCUIT MEMBER, AND SEMICONDUCTOR DEVICE INCLUDING THE CIRCUIT MEMBER - A circuit member | 06-11-2009 |
20090152696 | SEMICONDUCTOR DEVICE - A semi-conductor device ( | 06-18-2009 |
20090152697 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post. | 06-18-2009 |
20090166823 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD LOCKING STRUCTURE - A mountable integrated circuit package system includes: providing a base; depositing a photoresist on the base; patterning the photoresist with an opening; filling the opening with a metal; depositing a further metal on the metal to form a lead pad; removing the photoresist; attaching a die over the base; bonding wires between the die and the lead pad; encapsulating the die and the lead pad in an encapsulation formed into a lead pad lock adjacent the lead pad; and removing the base. | 07-02-2009 |
20090166824 | LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS - A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer. | 07-02-2009 |
20090166825 | System and Apparatus for Wafer Level Integration of Components - In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits on the substrate. The interconnect structure includes a wire bond between a contact pad on the substrate and a contact pad on the KGU, a redistribution layer on a back surface of the substrate, opposite the active surface, a through hole via (THV) through the substrate that electrically connects the redistribution layer and wire bond, and solder bumps formed in electrical contact with the redistribution layer. The KGU includes a KGU substrate for supporting the KGU, a semiconductor die disposed over the KGU substrate, and an encapsulant formed over the semiconductor die. | 07-02-2009 |
20090166826 | LEAD FRAME DIE ATTACH PADDLES WITH SLOPED WALLS AND BACKSIDE GROOVES SUITABLE FOR LEADLESS PACKAGES - Disclosed are die paddle structures for leadframes and methods of attaching die to the die paddles. An exemplary die paddle comprises a sloped wall disposed around an attachment area for a die, where the sloped wall has an obtuse angle of inclination with respect to the attachment area. In one exemplary die-attachment process, solder material is disposed on the attachment area and/or the metalized back surface of a die, the die is placed over the attachment area and substantially within the opening defined by the sloped wall, and the solder is reflowed while the die is allowed to float over the reflowed solder free of external forces from a die-placement tool and to align itself to the sloped wall. Die paddles and attachment methods of the invention reduce the alignment tolerances needed to place the die. | 07-02-2009 |
20090166827 | MECHANICAL ISOLATION FOR MEMS DEVICES - A device according to the present invention includes a MEMS device supported on a first side of a die. A first side of an isolator is attached to the first side of the die. A package is attached to the first side of the isolator, with at least one electrically conductive attachment device attaching the die to the isolator and attaching the isolator to the package. The isolator may include isolation structures and a receptacle. | 07-02-2009 |
20090166828 | ETCHED SURFACE MOUNT ISLANDS IN A LEADFRAME PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package. | 07-02-2009 |
20090166829 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element group in an arrangement direction of the electrode pads;
| 07-02-2009 |
20090174045 | Bump Pad Metallurgy Employing An Electrolytic Cu / Electorlytic Ni / Electrolytic Cu Stack - An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers. | 07-09-2009 |
20090174046 | SEMICONDUCTOR PACKAGE WITH AN EMBEDDED PRINTED CIRCUIT BOARD AND STACKED DIE - A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module. | 07-09-2009 |
20090174047 | Semiconductor Die Packages Having Overlapping Dice, System Using the Same, and Methods of Making the Same - Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance. | 07-09-2009 |
20090174048 | DIE PACKAGE INCLUDING SUBSTRATE WITH MOLDED DEVICE - A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate. | 07-09-2009 |
20090174049 | ULTRA THIN IMAGE SENSOR PACKAGE STRUCTURE AND METHOD FOR FABRICATION - An image sensor package having at least one chip supporting bar secured to a top surface of an image sensor chip. The thickness of the chip supporting bar is absorbed within a vertical dimension of wire loops that connect bonding pads to leads so that the chip supporting bar does not contribute to the thickness of the image sensor package. An exposed back surface of the image sensor chip enhances thermal dissipation. | 07-09-2009 |
20090179315 | Semiconductor Die Packages Having Solder-free Connections, Systems Using the Same, and Methods of Making the Same - Disclosed are spring structures that provide solderless electrical connections in semiconductor die packages. An exemplary spring structure comprises a first portion adapted to make an electrical connection to a conductive region of a semiconductor die, a second portion adapted to make an electrical connection to a conductive region of a leadframe, and a third portion disposed between the first and second portions. During a molding process, the third portion is compressively strained to impart forces to the first and second portions that maintain these portions in contact with the conductive regions of the die and leadframe. After the molding material sets, the third portion remains in a state of compressive strain, and imparts forces on the first and second portions that maintain the electrical connections. The spring structure may be made of less expensive materials, and does not require cleaning, fluxing, or reflowing, thereby reducing manufacturing cost and time. | 07-16-2009 |
20090179316 | FLEXIBLE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A flexible semiconductor device and a fabrication method thereof are disclosed. The method includes the steps of providing a CMOS (complementary metal-oxide semiconductor) chip having a silicon substrate, wherein an IC (integrated circuit) is formed on the silicon substrate; mounting the chip on a carrier board via the IC-laden side of the chip, wherein the IC-laden side of the chip is in contact with the carrier board; thinning the silicon substrate; forming a resilient plastic layer made of PDMS (polydimethylsiloxane) on the thinned silicon substrate; and removing the carrier board. The chip is flexible enough to expose testing pads on the front of the chip so as to facilitate wire bonding and probing. The resilient plastic layer enables uniform distribution of stress exerted on the chip and thereby guards the chip from cracking. | 07-16-2009 |
20090184406 | SEMICONDUCTOR PACKAGE HAVING INSULATED METAL SUBSTRATE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns. | 07-23-2009 |
20090189261 | Ultra-Thin Semiconductor Package - Semiconductor packages with a reduced-height die pad and associated methods for making and using these semiconductor packages are described. The semiconductor packages include a lead frame with die pad of reduced height so the die pad has a height that is less than that of the lead frame. The semiconductor packages may comprise an isolated and/or a fused lead finger with a portion of an upper surface of the isolated lead finger that is removed to form a concavity to which one or more bond wires may be bonded. The upper surface of the isolated lead finger may be removed so the isolated lead finger has a height that is less than the height of the lead frame. And a perimeter of a bottom surface of the fused lead finger may be removed. Other embodiments are described. | 07-30-2009 |
20090189262 | MULTIPHASE SYNCHRONOUS BUCK CONVERTER - Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding. | 07-30-2009 |
20090189263 | Wiring device for semiconductor device, composite wiring device for semiconductor device, and resin-sealed semiconductor device - A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal. | 07-30-2009 |
20090189264 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead). | 07-30-2009 |
20090194857 | Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same - Disclosed are semiconductor die packages, methods of making them, and systems incorporating them. An exemplary package comprises a first substrate, a second substrate, a semiconductor die disposed between the first and second substrates, and an electrically conductive member disposed between the first and second substrates. The semiconductor die has a conductive region at its first surface that is electrically coupled to a first conductive region of the first substrate, and another conductive region at its second surface that is electrically coupled to a first conductive region of the second substrate. The conductive member is electrically coupled between the first conductive region of the second substrate and a second electrically conductive region of the first substrate. This configuration enables terminals on both surfaces of the semiconductor die to be coupled to the first substrate. | 08-06-2009 |
20090194858 | HYBRID CARRIER AND A METHOD FOR MAKING THE SAME - The present invention relates to a hybrid carrier and a method for making the same. The hybrid carrier has a plurality of interconnection leads, so that a wire bondable semiconductor device or a flip chip die apparatus can be placed on the hybrid carrier, and is electrically connected to die paddle and bond fingers. Also, it is easy to dispose a semiconductor device on the hybrid carrier and easy to electrically bond the hybrid carrier and the semiconductor device. Therefore, the hybrid carrier and the method for making the same can be applied to an area array metal CSP easily, and the method of the present invention is simple, so the production cost can be reduced. | 08-06-2009 |
20090194859 | SEMICONDUCTOR PACKAGE AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer layer component may include a material formed by adding alumina Al | 08-06-2009 |
20090200649 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in which the semiconductor chip is resin molded. By further stepwise shortening the chip-side tip end portions of the leads as the first edge or side of the principal surface of the semiconductor chip goes away from the middle portion toward the both end portions thereof, and shortening the tip end portions of those of first leads corresponding to the middle portion of the first edge or side of the principal surface which are adjacent to second leads located closer to the both end portions of the first edge or side, the distances between second wires connected to the second leads and the tip end portions of the first leads adjacent to the second leads can be increased. As a result, it is possible to prevent the wire short-circuit defect even when wire sweep occurs due to the flow resistance of a mold resin. | 08-13-2009 |
20090206458 | FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES - A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink. | 08-20-2009 |
20090206459 | QUAD FLAT NON-LEADED PACKAGE STRUCTURE - A quad flat non-leaded package structure including a die pad, a plurality of leads, a chip, and a molding compound is provided. The die pad has a top surface and an opposite bottom surface, and the leads are disposed around the die pad. A concave portion is disposed at the end of each leads. The chip is disposed on the top surface of the die pad and is electrically connected to the leads. The molding compound encapsulates the chip, a portion of the leads and the die pad, and fills the gaps between the leads. | 08-20-2009 |
20090218665 | POWER DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a power device package, which can be made compact by mounting semiconductor chips in recesses formed in a substrate and improve operational reliability by rapidly dissipating heat generated during operation to the outside, and a method of fabricating the power device package. The power device package includes: a substrate having a first surface and a second surface opposite to each other, and one or more recesses formed in the first surface; a wiring pattern formed on the first surface of the substrate; one or more power semiconductor chips placed in the recesses and electrically connected to the wiring pattern; a lead frame electrically connected to the wiring pattern; one or more control semiconductor chips electrically connected to the power semiconductor chips to control the power semiconductor chips; and an optional sealing member sealing the substrate, the wiring pattern, the power semiconductor chips, the control semiconductor chips, and at least a part of the lead frame so as to expose the second surface of the substrate. | 09-03-2009 |
20090224384 | CHIP PACKAGE - A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad. | 09-10-2009 |
20090230522 | Method for producing a semiconductor device and the semiconductor device - In a method of manufacturing a semiconductor device which has rear electrodes extended from a front surface to a rear surface of a substrate, the rear electrodes are formed from a side of the front surface by forming a groove on the front surface, by forming a metal film on the groove, and by removing the substrate from a rear surface until the metal film is exposed on a bottom of the groove. | 09-17-2009 |
20090230523 | ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A CAVITY STRUCTURE AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. | 09-17-2009 |
20090230524 | SEMICONDUCTOR CHIP PACKAGE HAVING GROUND AND POWER REGIONS AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment the semiconductor package includes a die pad, a plurality of leads, a semiconductor chip, and a package body. The die pad includes a first part that includes a lower surface and a first peripheral edge region comprising a ground region. The die pad further includes a second part that is spaced apart from the first part and that includes a lower surface and a second peripheral edge region comprising a power region. The plurality of leads is disposed around the die pad. The semiconductor chip is disposed on the die pad and is electrically coupled to the ground region, the power region, and the plurality of leads. The package body is formed over the semiconductor chip and the plurality of leads. | 09-17-2009 |
20090230525 | ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING MARKING AND CORNER LEAD FEATURES AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body. | 09-17-2009 |
20090230526 | ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A PROTECTIVE LAYER TO ENHANCE SURFACE MOUNTING AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead. | 09-17-2009 |
20090230527 | Multi-chips package structure and the method thereof - A multi-chips package structure is provided, which includes a chip-placed frame having a plurality of chip-placed areas thereon, and two adjacent chip-placed areas is connected by a plurality of leads; a plurality of chips, each chip has a plurality of pads on an active surface thereon, and is provided on the chip-placed area; a package body is covered around the four sides of the chip-placed frame, and the pads of the chip is to be exposed; one end of a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended to cover the surface of the patterned first protection layer; a patterned second protective layer is covered on the patterned metal traces and another end of the patterned metal traces is to be exposed; a plurality of patterned UMB layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UMB layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 09-17-2009 |
20090230528 | Support Mounted Electrically Interconnected Die Assembly - Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder. | 09-17-2009 |
20090230529 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ETCHED RING AND DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring. | 09-17-2009 |
20090236709 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is disclosed. The semiconductor chip package comprises a lead frame having a chip carrier, wherein the chip carrier has a first surface and an opposite second surface. A semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier. A package substrate comprises a central region attached to the second surface, having an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a marginal region of the package substrate. | 09-24-2009 |
20090236710 | COL SEMICONDUCTOR PACKAGE - A Chip-On-Lead (COL) semiconductor package is revealed, primarily comprising a plurality of leadframe's leads each having a carrying bar, a finger and a connecting portion connecting the carrying bar to the finger. A chip has a back surface attached to the carrying bars and is electrically connected to the fingers by a plurality of bonding wires. Therein, at least one of the bonding wires overpasses one of the connecting portions without electrical relationship. An insulation tape is attached onto the connecting portions in a manner to be formed between the overpassing section of the bonding wire and the overpast connecting portion so that electrical short can be avoided during wire-bonding processes of the COL semiconductor package. Therefore, the carrying bars under the chip have more flexibility in the layout design of COL semiconductor packages to use die pad(s) with smaller dimensions or even eliminate die pad. | 09-24-2009 |
20090236711 | METHOD OF MAKING AND DESIGNING LEAD FRAMES FOR SEMICONDUCTOR PACKAGES - A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired. | 09-24-2009 |
20090236712 | IC PACKAGE HAVING REDUCED THICKNESS - An IC package having reduced thickness includes a lead frame, a chip, and a plurality of bonding wires. The lead frame includes a front side, a rear side, a plurality of pins located on the front side, and a hollow portion formed on the lead frame. The chip is larger than the rear side of the lead frame. The chip includes a plurality of electrodes and is adhered to the rear side of the lead frame. The electrodes correspond to the hollow portion. The bonding wires pass through the hollow portion to be connected with the pins and the electrodes. Accordingly, the IC package can effectively take good use of the space below the lead frame, reducing the height of the bonding wires and saving the packaging space above the lead frame, and reduce the thickness of the IC package without addition of the cost and equipment. | 09-24-2009 |
20090236713 | SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT - In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits. | 09-24-2009 |
20090236714 | ROBUST LEADED MOLDED PACKAGES AND METHODS FOR FORMING THE SAME - A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region. | 09-24-2009 |
20090243060 | Lead frame and package of semiconductor device - A lead frame including a stage and a plurality of terminals is embedded in a mold resin including a base portion for mounting a semiconductor chip (e.g. a microphone chip), a peripheral wall disposed in the periphery of the base portion, and an extension portion extended outside of the peripheral wall, thus forming a package base. A plurality of holes is formed in the peripheral wall so as to expose the internal connection surface of the stage and the internal connection surfaces of the terminals. An extension portion of the stage is exposed on the extension portion of the mold resin in which the surfaces of the terminals are embedded. An extension portion (e.g. a brim) of a cover composed of a conductive material is attached to the extension portion of the mold resin of the package base, thus completely producing a semiconductor device. | 10-01-2009 |
20090243061 | Complex Semiconductor Packages and Methods of Fabricating the Same - Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips. | 10-01-2009 |
20090250794 | METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND STRUCTURE THEREFOR - In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package. | 10-08-2009 |
20090250795 | LEADFRAME FOR PACKAGED ELECTRONIC DEVICE WITH ENHANCED MOLD LOCKING CAPABILITY - A packaged electronic device ( | 10-08-2009 |
20090250796 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 10-08-2009 |
20090250797 | Multi-Chip Package - A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing area. | 10-08-2009 |
20090250798 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT SUPPORT - An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support. | 10-08-2009 |
20090256247 | SEMICONDUCTOR DEVICE AND METHOD INCLUDING FIRST AND SECOND CARRIERS - A semiconductor device and method. One embodiment provides an integral array of first carriers and an integral array of second carries connected to the integral array of first carriers. First semiconductor chips are arranged on the integral array of first carriers. The integral array of second carriers is arranged over the first semiconductor chips. | 10-15-2009 |
20090261463 | Chip mounting device and chip package array - A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. The side rail includes at least one identifying element. A chip package array with the above-mentioned chip mounting device is also disclosed. The chip mounting device and chip package array includes the identifying element configured on the side rail to improve the identification of semi-finished packaged chips during chip package process to be read automatically by machines instead of operators, and further decrease the loss caused by misjudgments of operators. | 10-22-2009 |
20090273066 | SEMICONDUCTOR DEVICE AND METHOD - An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of semiconductor chips is placed over a carrier with the electrically conductive particles facing the carrier. The electrically conductive particles are heated until the at least one semiconductor chip adheres to the carrier. | 11-05-2009 |
20090278241 | SEMICONDUCTOR DIE PACKAGE INCLUDING DIE STACKED ON PREMOLDED SUBSTRATE INCLUDING DIE - A semiconductor die package. The semiconductor includes a premolded substrate. The premolded substrate includes (i) a leadframe structure, (ii) a first semiconductor die comprising a first die surface and a second die surface, attached to the leadframe structure, and (iii) a molding material covering at least a portion of the leadframe structure and the first semiconductor die. The premolded substrate includes a first premolded substrate surface and a second premolded substrate surface. A second semiconductor die is stacked on the second premolded substrate surface of the premolded substrate. A housing material is on at least a portion of the second semiconductor die and the second premolded substrate surface of the premolded substrate. One of the first semiconductor die and the second semiconductor die includes a transistor while the other includes an integrated circuit. | 11-12-2009 |
20090278242 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip. | 11-12-2009 |
20090278243 | STACKED TYPE CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed on the die pads respectively, and are electrically connected to the leads by wire bonding. The third chip traverses the first chip and the second chip, and is electrically connected to the first chip and the second chip respectively. The insulating material is disposed on the chip carrier for encapsulating the first chip, the second chip and the third chip, and fills among the die pads and the leads. | 11-12-2009 |
20090278244 | IC DEVICE HAVING LOW RESISTANCE TSV COMPRISING GROUND CONNECTION - A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame. | 11-12-2009 |
20090278245 | PACKAGED ELECTRONIC DEVICES WITH FACE-UP DIE HAVING TSV CONNECTION TO LEADS AND DIE PAD - A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad. | 11-12-2009 |
20090283881 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-DOWN ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving face-down electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers, and one side of each first conductive layer is electrically connected with the corresponding conductive pad. The second conductive unit has a plurality of second conductive layers respectively formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers. | 11-19-2009 |
20090283882 | QFN SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner terminal leads to the semiconductor die; at least one row of extended, outer terminal leads disposed along periphery of the QFN semiconductor package; at least one row of intermediary terminals disposed between the inner terminal leads and the extended, outer terminal leads; second wires bonding respective the intermediary terminals to the semiconductor die; and third wires bonding respective the intermediary terminals to the extended, outer terminal leads. | 11-19-2009 |
20090283883 | Semiconductor device using lead frame - A semiconductor device includes: a semiconductor chip configured to process a signal in a radio frequency band; two conductive antenna connection pins connected with two external antenna conductors, respectively; an island for the semiconductor chip to be mounted thereon; a suspending pin connected with the island; and an antenna connection conductor configured to connect the two antenna connection pins without connection with the island and the suspending pin. A series connection of one of the two external antenna conductors, one of the two antenna connection pins, the antenna connection conductor section, the other of the two antenna connection pins and the other of the two external antenna conductors in this order, functions as an antenna by connecting the series connection with the semiconductor chip. | 11-19-2009 |
20090283884 | LEAD FRAME, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE LEAD FRAME AND THE SEMICONDUCTOR PACKAGE - Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns. | 11-19-2009 |
20090289336 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other. | 11-26-2009 |
20090289337 | Lead Frame - A lead frame comprises a die pad and leads arranged around the die pad. Through holes are provided in the die pad, and the through holes are located in the peripheries, i.e., margin area of the die pad. The through holes serve to be passed through by the metal wires connected with the leads. By means of the above-described lead frame, the subsequent packaging process of the semiconductor chip; including dual chips and/or multi-chips assembly, is simplified and the effect of the manufacturing process is improved, at the same time, the manufacturing cost is reduced. | 11-26-2009 |
20090294938 | FLIP-CHIP PACKAGE WITH FAN-OUT WLCSP - A flip-chip package includes a package carrier; a semiconductor die having a die face and a die edge, the semiconductor die being assembled face-down to a chip side of the package carrier, and contact pads are situated on the die face; a rewiring laminate structure between the semiconductor die and the package carrier, the rewiring laminate structure including a re-routed metal layer, and at least a portion of the re-routed metal layer projects beyond the die edge; and bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier. | 12-03-2009 |
20090294939 | LEAD FRAME AND SEMICONDUCTOR DEVICE UTILIZING THE SAME - A lead frame and semiconductor device providing improved bond strength from wave bonding such as of wires in lead frames manufactured with depressed inner leads. The lead frame comprises an outer lead, an inner lead, a step difference section formed between the outer lead and inner lead, and an extended section extending from the inner lead towards the outer lead side. The extended section is provided to be adjacent to the step difference section. An acceptor clamp jig set on the lead frame includes a body, an inner lead support section and extended section support section respectively corresponding to the outer lead, the inner lead and the extended section. The outer lead is pressed from above by a retainer clamp jig. The extended section of the inner lead and the extension support section of the acceptor clamp jig prevent the tip of the inner lead from floating upward by acting together to accept and resist the tensile stress applied on the step difference section of the lead. Ultrasonic waves are in this way applied more efficiently and ultrasonic wave loss in the bond part between the inner lead and the wire is reduced. | 12-03-2009 |
20090309199 | CHIP PACKAGE FOR SEMICONDUCTOR DEVICES - A chip package for semiconductor devices is provided. The chip package includes a flange configured to mount thereon a semiconductor device. The chip package further includes an inverted bridge lead frame above the flange and having a recessed area below a top portion. The inverted bridge lead frame provides semiconductor device terminal connections to at least one lead. | 12-17-2009 |
20090309200 | Body to be plated, method of determining plated film thickness, and method of manufacturing semiconductor device - A structure to be plated includes a body to be plated 11 on which plating is formed, and plated film thickness determining member | 12-17-2009 |
20090309201 | LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING LEAD FRAME AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame has a die pad on which a semiconductor chip is mounted, a plurality of leads, a first recess provided so as to sink in from the front surface of the die pad, and second recesses and third recesses (through holes) provided so as to sink in from the front surface and the rear surface of the leads, respectively. The inner wall surfaces of the first recess, the second recesses and the third recesses (through holes) are made uneven, respectively. | 12-17-2009 |
20090315162 | Micro-Modules with Molded Passive Components, Systems Using the Same, and Methods of Making the Same - Semiconductor die packages, methods of making said packages, and systems using said packages are disclosed. An exemplary package comprises at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, and at least one passive electrical component disposed on the other surface of a leadframe and electrically coupled to at least one conductive region of the leadframe. Molding material is disposed over the at least one passive electrical component to provide a molded passive component. | 12-24-2009 |
20090315163 | Semiconductor Die Packages with Stacked Flexible Modules Having Passive Components, Systems Using the Same, and Methods of Making the Same - Disclosed are semiconductor die packages comprising flexible modules having passive components, with the flexible modules and one or more semiconductor dice disposed in a stacked relationship, systems using the same, and methods of making the same. In one exemplary package embodiment, one or more semiconductor dice are disposed on a leadframe that is disposed in a stacked relationship with the flexible module. In another embodiment, one or more semiconductor dice are attached to a surface of a flexible module. | 12-24-2009 |
20100001384 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD-FRAME PADDLE SCHEME FOR SINGLE AXIS PARTIAL SAW ISOLATION - An integrated circuit package system includes: providing a die-pad with a predefined slot and an integrated circuit attached to the die-pad; connecting the integrated circuit to the die-pad with a bond wire; encapsulating the integrated circuit and the bond wire with an encapsulation; and partitioning the die-pad with partial saw isolation grooves along a single axis, and into a side pad, and a die attach pad. | 01-07-2010 |
20100001385 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BUMPED LEAD AND NONBUMPED LEAD - An integrated circuit package system includes: forming an external interconnect; forming a terminal having a cavity adjacent to and downset from a portion the external interconnect; connecting a first integrated circuit with the external interconnect; and forming an encapsulation over the first integrated circuit with cavity filled with the encapsulation, the terminal extending from the encapsulation, and the external interconnect partially exposed from the encapsulation. | 01-07-2010 |
20100001386 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device and a manufacturing method therefor wherein a wire for coupling an inner lead and a semiconductor chip with each other can be prevented from being electrically short-circuited to any other conductive part are provided. An inner lead portion has a tip arranged outside the outer circumferential end of the semiconductor chip as viewed on a plane. A power supply bar has a jutted portion extended between the outer circumferential end of the semiconductor chip and the tip of the inner lead portion as viewed on a plane. The upper face of the jutted portion is in a position lower than the upper face of the tip of the inner lead portion. A bonding wire for electrically coupling the semiconductor chip and the inner lead portion with each other has a bent portion outside the outer circumferential end of the semiconductor chip as viewed on a plane. | 01-07-2010 |
20100006992 | Fine-pitch routing in a lead frame based system-in-package (SIP) device - In an example embodiment, there is a package substrate ( | 01-14-2010 |
20100006993 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CHIP ON LEAD - An integrated circuit package system includes: providing a lead having a lead connection surface for connectivity to a next level system; attaching an integrated circuit over the lead having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and attaching a die connector to the integrated circuit and the lead. | 01-14-2010 |
20100006994 | Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier - An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a lead frame interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the lead frame interconnect structure and encapsulant. The package interconnect structure and lead frame interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the lead frame interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the lead frame interconnect structure. | 01-14-2010 |
20100006995 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device comprises a semiconductor chip including a silicon substrate, a die pad to which the semiconductor chip is secured through a first solder layer, a resin-encapsulating layer encapsulating the semiconductor chip, and lead terminals electrically connected to the semiconductor chip and including inner lead portion covered with the resin-encapsulating layer. The lead terminals are made of copper or a copper alloy. The die pad is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals. | 01-14-2010 |
20100006996 | CARRIER FOR BONDING A SEMICONDUCTOR SHIP ONTO AND A METHOD OF CONTRACTING A SEMICONDUCTOR CHIP TO A CARRIER - A carrier ( | 01-14-2010 |
20100006997 | Chip-Stacked Package Structure with Leadframe Having Multi-Piece Bus Bar - The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces. | 01-14-2010 |
20100013068 | CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF - A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad. | 01-21-2010 |
20100013069 | SEMICONDUCTOR DEVICE, LEAD FRAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device and a lead frame capable of preventing development of defective mounting resulting from a burr and a method of manufacturing a semiconductor device with the lead frame are provided. The semiconductor device includes a semiconductor chip and a lead arranged on the periphery of the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, so that at least an end portion on the side farther from the semiconductor chip is bonded to a mounting substrate. A groove opened on a surface bonded to the mounting substrate and an end face on the side farther from the semiconductor chip is formed in the lead over the full width in the width direction orthogonal to the thickness direction and along the end face. An embedded body made of solder is embedded in the groove. | 01-21-2010 |
20100013070 | POWER MODULE PACKAGE HAVING EXCELLENT HEAT SINK EMISSION CAPABILITY AND METHOD FOR MANUFACTURING THE SAME - A power module package includes a power circuit element, a control circuit element, a lead frame, an aluminum oxide substrate having a heat sink and an insulation layer, and a sealing resin. The control circuit element is electrically connected with the power circuit element to control chips within the power circuit element. The lead frame has external connection terminal leads in its edge and has a first surface to which the power circuit element and the control circuit element are attached and a second surface which is used as a heat transmission path. The heat sink is a plate made of metal such as aluminum and the electrical insulation layer is formed at least on an upper surface of the heat sink and made of aluminum oxide. The electrical insulation layer may be formed over an entire surface of the heat sink. Here, the insulation layer is attached to the second surface by an adhesive, on a region below where the power circuit element is attached, to the first surface of the lead frame. In addition, the sealing resin encloses the power circuit element and the control circuit element, the lead frame, and the metal oxide substrate and exposes the external connection terminals of the lead frame. | 01-21-2010 |
20100019362 | ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES - Semiconductor packages that contain isolated stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using differing arrays of metal strips that serve as interposers between the first and second dies. This configuration provides a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described. | 01-28-2010 |
20100019363 | SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described. | 01-28-2010 |
20100025829 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a foil formed of an insulating material, where the foil includes at least one electrically conducting element, providing a chip having contact elements on a first face of the chip, and applying the foil over the contact elements of the chip. | 02-04-2010 |
20100032817 | SEMICONDUCTOR DEVICE WITH PLASTIC PACKAGE MOLDING COMPOUND, SEMICONDUCTOR CHIP AND LEADFRAME AND METHOD FOR PRODUCING THE SAME - A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device. | 02-11-2010 |
20100032818 | LEAD FRAME PACKAGE - A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of the bonding wires. | 02-11-2010 |
20100032819 | Compact Co-packaged Semiconductor Dies with Elevation-adaptive Interconnection Plates - A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes:
| 02-11-2010 |
20100038759 | Leadless Package with Internally Extended Package Leads - A DFN package includes internally extended package leads. One or more package pads are physically and electrically extended from a first edge of the package to a second, opposite edge of the package. These extended package leads can terminate at the edges of the leadframe. The package pads and the extended package leads where the IC die is attached can have full leadframe thickness. Other extended package lead features can have a reduced leadframe thickness (e.g., about half the leadframe thickness). Leadframe features can be physically and electrically connected to a tie-bar feature which can be an integral part of a leadframe matrix. The tie-bar can stabilize the leadframe features during assembly. The tie-bar can also provide electrical connectivity for post assembly leadframe plating. The tie-bar can be removed during package singulation by sawing or punching techniques to free the leadframe features both physically and electrically. | 02-18-2010 |
20100038760 | Metal Leadframe Package with Secure Feature - A fabrication method for a BGA or LGA package includes a low-cost metal leadframe with internally extended leads. I/O attach lands can be placed at any location on the metal leadframe, including the center of the package. An I/O attach land can be fabricated at any position upon an extended lead (e.g., near the center of the package). During fabrication of the package, an isolation saw cut to the bottom of the package can be used to electrically disconnect the leadframe circuit from the peripheral extension traces to prevent tampering with the IC die by probing the edge metal traces. | 02-18-2010 |
20100038761 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: mounting a first integrated circuit over a carrier; mounting an interposer, having an opening, over the first integrated circuit and the carrier with the interposer having an overhang over the carrier; connecting an internal interconnect, through the opening, between the carrier and the interposer; and forming an encapsulation over the first integrated circuit, the internal interconnect, and the carrier. | 02-18-2010 |
20100044842 | SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a chip coupled to the carrier, a dielectric layer coupled to the carrier and the chip, and conducting elements connected to both the carrier and contacts of the chip. The chip includes a first face with a first contact spaced apart from a second contact. The dielectric layer includes a photoinitiator that configures the dielectric layer to be selectively opened to expose the first and second contacts and the carrier. A first conducting element is connected to the first contact, a second conducting element is connected to the second contact, and a third conducting element is connected to the carrier. | 02-25-2010 |
20100044843 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection. | 02-25-2010 |
20100044844 | LEAD FRAME, RESIN PACKAGE, SEMICONDUCTOR DEVICE AND RESIN PACKAGE MANUFACTURING METHOD - A pressure loss section H | 02-25-2010 |
20100052122 | WIRE BODNING PACKAGE STRUCTURE - A chip package structure employing a die pad integrated with the ground/voltage pad is provided. The die pad for carrying the chip is split into at least two separate sections for accommodating the ground and the voltage. Due to the design of the die pad, the signal fingers may be extended under the chip to be connected with vias, and thermal/ground vias may be arranged under the die pad for thermal or electrical connections. Through such arrangement, all the fingers are located closer to the die, thus decrease the length of bonding wires and reducing the package dimensions. | 03-04-2010 |
20100052123 | LOW STRESS CAVITY PACKAGE - The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity. | 03-04-2010 |
20100052124 | RESIN SEALING TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND RESIN SEALING TYPE ELECTRONIC DEVICE - The invention provides a resin sealing type electronic device having high reliability by eliminating a solder burr formed when a tie bar is cut. The invention also prevents a welding failure between a lead of the resin sealing type electronic device and an external electrode, and provides a large area for bonding an electronic component to the lead to prevent a connection failure. In the method of manufacturing the resin sealing type semiconductor device of the invention, in a case that a tie bar is cut after a semiconductor die and so on are mounted on a lead frame and these are resin-sealed, the cutting of the tie bar is performed from the side of the lead frame where a lead burr is formed by presswork. Furthermore, in the resin sealing type electronic device of the invention, a die capacitor is bonded to burr formation surfaces of a lead and an island using conductive paste. Since the burr formation surface has a larger surface area than a rounded surface, a large bonding area is obtained. A welding surface of the lead to a control electrode is the rounded surface that is opposite to the burr formation surface. | 03-04-2010 |
20100052125 | RESIN SEALING TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LEAD FRAME - The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc. | 03-04-2010 |
20100052126 | APPARATUS AND METHOD FOR USE IN MOUNTING ELECTRONIC ELEMENTS - Some embodiments provide surface mount devices that include a first electrode comprising a chip carrier part, a second electrode disposed proximate to the chip carrier part, and a casing encasing a portion of the first and second electrodes. The first electrode can extend from the chip carrier part toward a perimeter of the casing, and the second electrode can extend away from the chip carrier part and projects outside of the casing. In extending away from the chip carrier part the first electrode divides into a plurality of leads separated by an aperture that join into a single first joined lead portion with a first width before projecting outside of the casing and maintains the first width outside of the casing. The second electrode can attain a second width prior to projecting outside of the casing and maintains the second width outside the casing. | 03-04-2010 |
20100052127 | FLIP CHIP MLP WITH CONDUCTIVE INK - A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package. | 03-04-2010 |
20100059871 | LEADFRAME - A leadframe including a chip supporting plate, a lead forming plate, and solder points is provided. A notch is formed on an edge of the chip supporting plate. The thickness of the lead forming plate is less than the thickness of the chip supporting plate. The lead forming plate has a main body, inner leads, and a connecting rod. The inner leads and the connecting rod are extended from an edge of the main body. The connecting rod has an end portion fitting the notch. The solder points are located at the boundary between the end portion and the notch for structurally connecting the connecting rod and the chip supporting plate. | 03-11-2010 |
20100065951 | Method of Manufacturing A Semiconductor Device - The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding. Accordingly, when cutting the suspending leads, corner portions of the back surface of the sealing body can be supported by a flat portion of a holder portion in a cutting die which flat portion has an area sufficiently wider than a cutting allowance of the suspending leads, whereby it is possible to prevent chipping of the resin and improve the quality of the semiconductor device (QFN). | 03-18-2010 |
20100072588 | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same - The present invention discloses a structure of device package comprising a first substrate with a die metal pad, a first wiring circuit on top surface of said first substrate and a second wiring circuit on bottom surface of said first substrate. A die is disposed on the die metal pad. A second substrate has a die opening window for receiving the die, a third wiring circuit on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. | 03-25-2010 |
20100072589 | SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD - A semiconductor package system includes: providing a leadframe with a lead; making a die support pad separately from the leadframe; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the lead; and connecting a bonding pad on the semiconductor die to the lead using a bonding wire. | 03-25-2010 |
20100072590 | Stacking Quad Pre-Molded Component Packages, Systems Using the Same, and Methods of Making the Same - Pre-molded component packages that may be as thin as a leadframe for a semiconductor die, systems using the same, and methods of making the same are disclosed. The leads of an exemplary package are exposed at both surfaces at the leadframe. The packages may be stacked upon one another and electrically coupled at the exposed portions of their leads. | 03-25-2010 |
20100072591 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ANTI-PEEL PAD - An integrated circuit package system includes: forming an anti-peel pad having both a concave ring and an external terminal with the concave ring, having a peripheral wall, surrounding the external terminal; connecting an integrated circuit with the anti-peel pad; and forming an encapsulation over the integrated circuit, the concave ring, and the external terminal with the encapsulation under the peripheral wall. | 03-25-2010 |
20100072592 | LIGHT SOURCE USING A LIGHT-EMITTING DIODE - A light source is described herein. An embodiment of the light source comprises a mounting surface and a first lead frame. The first lead frame extends from the mounting surface. The first lead frame comprises a first portion extending from the mounting surface; a cup portion having a cup portion first side and a cup portion second side, the cup portion first side configured to receive a light-emitting diode, the cup portion second side being located opposite the cup portion first side; and a second portion extending between the first portion and the cup portion second side. | 03-25-2010 |
20100072593 | Semiconductor package and method for manufacturing the same - A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected. | 03-25-2010 |
20100078783 | DEVICE INCLUDING TWO MOUNTING SURFACES - A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed. | 04-01-2010 |
20100078784 | DEVICE INCLUDING A POWER SEMICONDUCTOR CHIP - A device including a power semiconductor chip. One embodiment provides a power semiconductor chip having a first electrode on a first surface and a second and a third electrode on a second surface opposite to the first surface. A leadframe includes a carrier and a first lead, the power semiconductor chip placed over the carrier with the first surface of the power semiconductor chip facing the carrier. A metallic layer includes a first surface and a second surface opposite to the first surface. The metallic layer is placed over the second surface of the power semiconductor chip with the first surface of the metallic layer facing the power semiconductor chip. The second surface of the metallic layer and a surface of the first lead lie within a common mounting plane. | 04-01-2010 |
20100078785 | Lead frame and method of manufacturing the same - A lead frame includes a base material having a front surface for mounting of a semiconductor chip and a back surface for connection with an external board, and an Ni layer having a thick section and thin section. The thick section is formed on the back surface of the base material, whereas the thin section is formed on all or a part of the front surface of the base material. It is preferable that the thick section has a thickness ranging from 2.5 to 5 μm, and the thin section is 0.5-2 μm thinner than the thick section. The lead frame can be manufactured with improved productivity by forming an Ni layer on both front and back surfaces of the base material, and then etching only the Ni layer formed on the front surface of the base material. | 04-01-2010 |
20100084750 | MODULE HAVING A STACKED PASSIVE ELEMENT AND METHOD OF FORMING THE SAME - A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material. | 04-08-2010 |
20100090322 | Packaging Systems and Methods - Packaging systems and methods for semiconductor devices are disclosed. In one embodiment, a packaging system includes a first plate having a first coefficient of thermal expansion (CTE). An integrated circuit is mountable to the first plate. The packaging system includes a second plate coupleable over the first plate over the integrated circuit. The second plate has a second CTE that is substantially a same CTE as the first CTE. A plurality of solder balls is coupleable to the first plate or the second plate and to the integrated circuit. | 04-15-2010 |
20100096735 | CLAMPING ASSEMBLY - A clamping assembly for clamping a lead frame with pre-attached semiconductor device, comprising of: a first member, to hold the lead frame, said first member having a surface profile in contact with a surface profile of the semiconductor device, a second member for allowing the mounting of the first member thereon, an attachment means to secure the first member onto the second member, wherein the attachment means is adjustable to conform the surface profile of the first member to the surface profile of the lead frame. | 04-22-2010 |
20100102423 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND WIRING BOARD - A semiconductor device manufacturing method includes (a) bonding a first surface of a metal plate to a substrate, (b) forming a plurality of metal posts that are arranged in vertical and lateral directions in a plan view and include a first metal post and a second metal post, by partially etching the metal plate bonded to the substrate from a second surface of the metal plate, (c) fixing an integrated circuit (IC) element to the second surface of the first metal post, (d) coupling the second metal post and a pad terminal of the integrated circuit element via a conductive material, (e) resin-sealing the integrated circuit element, the metal posts, and the conductive material by providing a resin onto the substrate, and (f) removing the substrate from the resin and the first surfaces of the metal posts sealed using the resin. | 04-29-2010 |
20100109135 | SEMICONDUCTOR DIE PACKAGE INCLUDING LEAD WITH END PORTION - A semiconductor die package, and methods of making the same. The package includes a leadframe and a clip structure. The clip structure is formed, such that a portion of the clip structure points towards the semiconductor die and is coplanar with the leadframe. The semiconductor die package further includes a housing material covering at least a portion of the leadframe, the semiconductor die, and the clip structure. The housing material has an external recess that holds a portion of the clip structure. | 05-06-2010 |
20100109136 | Semiconductor device including semiconductor chip mounted on lead frame - A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires. | 05-06-2010 |
20100117207 | BOND PAD ARRAY FOR COMPLEX IC - An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers. | 05-13-2010 |
20100123228 | PACKAGE INCLUDING PROXIMATELY-POSITIONED LEAD FRAME - Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed. | 05-20-2010 |
20100123229 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal. | 05-20-2010 |
20100123230 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a first terminal having a cavity; mounting a first integrated circuit over the first terminal and connected in the cavity; forming a second terminal adjacent to the first terminal; connecting a second integrated circuit, over the first integrated circuit, and the second terminal; and forming a first encapsulation over the first integrated circuit with the first terminal exposed. | 05-20-2010 |
20100123231 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A wiring board has a mounting region allowed for mounting of the semiconductor element, a solder layer is provided to the mounting region so as to bond the semiconductor element with the wiring board, and a divisional ridge which divides the solder layer into a plurality of regions in a plan view and surrounds the solder layer, is provided to the wiring board. A portion of the solder layer bonded to the semiconductor element has a thickness larger than the height of the divisional ridge. | 05-20-2010 |
20100127365 | LEADFRAME-BASED CHIP SCALE SEMICONDUCTOR PACKAGES - Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described. | 05-27-2010 |
20100127366 | Integrated Leadframe And Bezel Structure And Device Formed From Same - An integrated leadframe and bezel structure includes a planar carrier frame, a plurality of bonding leads, a die pad region, and a bezel structure. The bezel structure includes a bending portion shaped and disposed to facilitate a portion of said bezel structure being bent out of the plane of said carrier frame. A sensor IC may be secured to the die pad region, and wire bonds made to permit external connection to the sensor IC. The bezel structure includes portions which are bent such that their upper extent is in or above a sensing surface. The assembly is encapsulated, exposing on the top surface part of the bezel portions and the upper surface of the sensor IC, and on the bottom surface the contact pads. Two or more bezel portions may be provided, one or more on each side of the sensor IC. | 05-27-2010 |
20100127367 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a number of first bonding wires, a number of second bonding wires, and a number of third bonding wires. The chip is disposed on the circuit substrate. The B-staged adhesive layer is disposed on the circuit substrate. The leadframe is disposed on the circuit substrate and includes a number of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. The first bonding wires are electrically connected between the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the leads. The third bonding wires are electrically connected between the leads and the circuit substrate. In addition, a manufacturing method of a chip package is also provided. | 05-27-2010 |
20100127368 | LEAD FRAME - A lead frame includes a plurality of units arranged in a matrix manner. Each unit has an external frame defining an accommodation area, a die mount pad disposed in the accommodation area of the external frame, a plurality of leads connected with the external frame and arranged around the die mount pad, a short bar having two ends respectively electrically connected with the die mount pad and one of the leads, and a plurality of support bars each having a straight section connected with the external frame, and a continuous curved section connected with the die mount pad. By means of the continuous curved sections of the support bars, thermal deformation and/or displacement of the lead frame can be prevented. | 05-27-2010 |
20100127369 | LEAD FRAME, METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE - A lead frame includes a lead frame body | 05-27-2010 |
20100127370 | WIRING BOARD, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ELEMENT - On a semiconductor element loading face, wiring patterns are drawn out from those formed in the vicinity of the edge of the semiconductor element of the loading pads formed to correspond to the electrode terminals of the semiconductor element, and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in the central region of the semiconductor element and its vicinity are electrically connected to external connecting terminal pads formed in the central region on the other side of the wiring board and its vicinity, through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias. | 05-27-2010 |
20100133671 | Flip-chip package structure and the die attach method thereof - A flip-chip package structure comprises a carrier, a block bump, and a die. The carrier is a lead frame or substrate that comprises a lead pattern side, and an electrode pin is disposed on the lead pattern side. The die comprises an active side, and a bond pad is disposed on the active side. The block bump is bonded to the electrode pin; the bond pad of the die is attached on the carrier through the block bump, so that the die and the carrier joint together to form the flip chip package structure. Besides, the block bump is formed by the wedge bonding, and therefore in bumping size and shapes can easily form larger bump, which will increase the compactness between the die and the carrier. | 06-03-2010 |
20100133672 | DUAL-SIDED SUBSTATE INTEGRATED CIRCUIT PACKAGE INCLUDING A LEADFRAME HAVING LEADS WITH INCREASED THICKNESS - An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a distal end. The proximal end has a second thickness less than the first thickness. The distal end is disposed between the first and second inner surfaces. The distal end is undulated such that the distal end has an effective thickness greater than the second thickness. | 06-03-2010 |
20100140763 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle and a terminal adjacent to the package paddle; mounting a stack paddle over the package paddle with the stack paddle at a non-center offset with the package paddle; mounting a stack integrated circuit over the stack paddle; and encapsulating the stack integrated circuit and the stack paddle. | 06-10-2010 |
20100140764 | WIRE-ON-LEAD PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a wire-on-lead package system includes: providing a die attach paddle with paddle extensions distributed along the periphery of the die attach paddle, providing leadfingers surrounding the die attach paddle, attaching a semiconductor die to the die attach paddle wherein the semiconductor die is larger than the die attach paddle, and connecting bond wires between the semiconductor die and the leadfingers and between the semiconductor die and the paddle extensions. | 06-10-2010 |
20100140765 | LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate. | 06-10-2010 |
20100140766 | LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR - A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers. | 06-10-2010 |
20100148330 | Leadless package housing - A leadless package for semiconductor elements has at least two semiconductor elements which are situated on a connection region of a lead frame of the leadless package in such a way that when deformations of the semiconductor elements occur, the deformations of the semiconductor elements compensate one another. | 06-17-2010 |
20100148331 | SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR DICE IN LATERALLY OFFSET STACKED ARRANGEMENT - A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device. | 06-17-2010 |
20100155915 | STACKED POWER CONVERTER STRUCTURE AND METHOD - A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad. | 06-24-2010 |
20100155916 | CHIP PACKAGE STRUCTURE AND THE METHOD THEREOF WITH ADHERING THE CHIPS TO A FRAME AND FORMING UBM LAYERS - A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 06-24-2010 |
20100164079 | METHOD OF MANUFACTURING AN ASSEMBLY AND ASSEMBLY - The assembly ( | 07-01-2010 |
20100164080 | SEMICONDUCTOR DEVICE - A semiconductor device includes a circuit base including an inner lead portion and an outer lead portion. The inner lead portion has a plurality of inner leads. At least part of the inner leads is routed inside a chip mounting area. On both upper and lower surfaces of the circuit base, a first and a second semiconductor chip are mounted. At least part of electrode pads of the first semiconductor chip are electrically connected to electrode pads of the second semiconductor chip via the inner leads. | 07-01-2010 |
20100171201 | CHIP ON LEAD WITH SMALL POWER PAD DESIGN - Embodiments of a semiconductor device and method provide a quad flat no-lead semiconductor package which can have an arrangement of both chip-on-lead (COL) style leads and a die pad for supporting a die, and can also provide non-COL leads, both COL leads and a leadframe power pad, COL leads which have varying lengths to reduce stress resulting from thermal mismatch between a semiconductor die and leads, and a die pad with a curved, meandering edge to reduce stress resulting from thermal mismatch between the semiconductor die and the die pad. | 07-08-2010 |
20100176499 | Semiconductor device with lead frame having lead terminals with wide portions of trapezoidal cross section - A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion. | 07-15-2010 |
20100176500 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of electrodes formed on a semiconductor chip, and a plurality of wires each connecting each of the electrodes to an inner lead, and each having a plurality of bending points. A first wire of the plurality of the wires has a slope extending upwardly from a first bending point toward a second bending point, where the first bending point is being located at an upper end of a rising portion. The second bending point of the first wire is the highest bending point in the first wire. A second wire of the plurality of the wires has a slope extending downwardly from a first bending point toward a second bending point, where the first bending point is located at an upper end of a rising portion. The second bending point of the second wire is the lowest bending point in the second wire. | 07-15-2010 |
20100181658 | Semiconductor device which exposes die pad without covered by interposer and its manufacturing method - A semiconductor device, includes a lead frame including a die pad of which back side surface is exposed to the back side of a package, as well as a plurality of land terminals, a resin filled between the die pad and each of the land terminals so as to enable the die pad and each of the land terminals to be fastened mutually, and a semiconductor chip having a plurality of pads and being mounted on a top side of the die pad. The semiconductor device further includes an interposer having a bonding stitch on its top side, being disposed on the top side surface of the lead frame, and relaying an electrical connection of at least any one of the plurality of pads to at least any one of the land terminals, and a first bonding wire bonded to the bonding stitch of the interposer and one of the plurality of pads of the semiconductor chip. | 07-22-2010 |
20100181659 | Lead frames with improved adhesion to plastic encapsulant - A lead frame and an electronic package having improved adhesion between the lead frame and an encapsulating plastic material is disclosed. The lead frame can be pre plated having an outer layer comprising a precious metal such as palladium or gold to which is adhered a self-assembled monolayer (SAM), such as a SAM derived from an organophosphorus acid. The organophosphorus acid preferably is a mixture in which the organo groups are fluoro substituted hydrocarbons and hydrocarbons containing ethylenically unsaturated groups. | 07-22-2010 |
20100187665 | Integral metal structure with conductive post portions - A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination. | 07-29-2010 |
20100187666 | LEAD FRAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a welding portion to be welded to other lead frame, and a frame, wherein the welding portion has an island portion provided like an island, and a plurality of connection members which connect the island portion and the frame with each other; and one connection member is provided so that a straight line which connects a connection point of the island portion and one connection member, and a connection point of one connection member and the frame, inclines away from a portion of the outer circumference (edge, for example) of the island portion where the connection member is connected, and also from a portion of the inner circumference (edge, for example) of the frame where the connection member is connected. | 07-29-2010 |
20100193920 | SEMICONDUCTOR DEVICE, LEADFRAME AND METHOD OF ENCAPSULATING - A semiconductor device is disclosed having a leadframe comprising a first chip island and a second chip island. Each chip island of the leadframe has a first face and a second face. A first chip is attached to the first face of the first chip island and a second chip attached to the first face of the second chip island. A layer of encapsulation material forming an encapsulation material layer covers the second faces of the first and second chip islands where the thickness of the encapsulation material layer along the second face of the first chip island is different from the thickness of the encapsulation material layer along the second face of the second chip island. | 08-05-2010 |
20100193921 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly. | 08-05-2010 |
20100193922 | Semiconductor chip package - A semiconductor chip package is disclosed comprising a semiconductor chip, a lead frame comprising at least one lead, and an encapsulating layer at least partially encapsulating the semiconductor chip and the lead frame. The lead comprises a first portion defining a lead frame pad at least partially exposed at an exterior surface of the package and a second portion extending from the first portion towards the semiconductor chip electrically connecting a surface portion of the semiconductor chip to the lead frame pad. The first portion has a first thickness and the second portion comprises a thinned portion, the thinned portion having a thickness smaller than the first thickness. The lead further comprises a bent portion, and wherein the thinned portion comprises at least part of the bent portion. | 08-05-2010 |
20100193923 | Semiconductor Device and Manufacturing Method Therefor - The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part. | 08-05-2010 |
20100193924 | SEMICONDUCTOR DEVICE - A lead frame includes an inner lead area overlapping with a chip mounting area, an outer lead portion having outer leads disposed outside the inner lead area, and an inner lead portion having inner leads disposed in the inner lead area. A semiconductor chip is mounted on the chip mounting area of the lead frame. Electrode pads of the semiconductor chip are electrically connected to inner leads via metal wires. Portions of the inner leads located on an area in the inner lead area except the chip mounting area are depressed. | 08-05-2010 |
20100193925 | LEADFRAME FOR SEMICONDUCTOR PACKAGES - A leadframe for semiconductor packages. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. Each lead has a corresponding lead relative to a predetermined center line. A predetermined pair of corresponding leads are substantial asymmetrical with each other in appearance relative to the predetermined center line. | 08-05-2010 |
20100193926 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 08-05-2010 |
20100200972 | BGA package with leads on chip - A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas, and the laterals of the leads between the top surfaces and the bottom surfaces. A plurality of cavities are formed in the bottom of the encapsulant to expose the corresponding and embedded ball-placement areas. The lips have a plurality of internal sides exposed inside the cavities. The solder balls are disposed on the ball-placement areas and on the internal sides of the cavities to make the solder balls partially embedded in the corresponding cavities to offer non-planar ball pads. It is effective to resolve the solderability of the solder balls and to enhance the reliability of wire bonding and the stability of solder ball placement. | 08-12-2010 |
20100200973 | LEADFRAME STRUCTURE FOR ELECTRONIC PACKAGES - A leadframe structure ( | 08-12-2010 |
20100213588 | WIRE BOND CHIP PACKAGE - A wire bond chip package includes a chip carrier; a semiconductor die having a die face and a die edge, the semiconductor die being mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution bond pads; a plurality of bond wires interconnecting the redistribution bond pads with the chip carrier; and a mold cap encapsulating at least the semiconductor die and the bond wires. | 08-26-2010 |
20100213589 | MULTI-CHIP PACKAGE - A multi-chip package includes a chip carrier; a semiconductor die mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution pads for the I/O pads; at least one bond wire interconnecting at least one of the redistribution pads with the chip carrier; a chip package mounted on at least another of the redistribution pads; and a mold cap encapsulating at least a portion of the bond wire. | 08-26-2010 |
20100219517 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND MOLDING DIE - Provided is a method for manufacturing a semiconductor device in which movement of an island in resin sealing is prevented. A molding die includes an upper die and a lower die. The upper and lower dies are fitted together to form cavities and runners. In the lower die, a pod is provided. After heating and melting of a tablet made of a solid resin and housed in the pod, the melted sealing resin is pressurized by a plunger, and is supplied to each of the cavities. Specifically, a liquid sealing resin is supplied from the pod to the cavities, sequentially, from the upstream of the flow of the sealing resin supplied from the pod. The cavities communicate with each other through the runners. Furthermore, the runners through which the cavities communicate are provided to be tilted with respect to a path for supplying the sealing resin. | 09-02-2010 |
20100219518 | QUAD FLAT NON-LEADED PACKAGE - A quad flat non-leaded package including a leadframe, a chip, a plurality of first bonding wires and a molding compound is provided. The leadframe includes a plurality of first leads, and each first lead has a first portion and a second portion that extend along an axis. The length of the first portion is greater than the length of the second portion. The thickness of the first portion is greater than the thickness of the second portion. The chip is disposed on the leadframe and covers a portion of the first portions. The first bonding wires are connected between the chip and another portion of the first portions or the chip and the second portions, such that the chip is electrically connected to the first leads through the first bonding wires. The molding compound encapsulates a portion of the first leads, the chip and the first bonding wires. | 09-02-2010 |
20100219519 | COMPLETE POWER MANAGEMENT SYSTEM IMPLEMENTED IN A SINGLE SURFACE MOUNT PACKAGE - A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink. | 09-02-2010 |
20100219520 | LEAD FRAME - A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability. | 09-02-2010 |
20100224970 | LEADLESS INTEGRATED CIRCUIT PACKAGE HAVING STANDOFF CONTACTS AND DIE ATTACH PAD - A leadless integrated circuit (IC) package comprising an IC chip mounted on a die attach pad and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die attach pad are all covered with a molding material, with portions of the electrical contacts and die attach pad protruding from a bottom surface of the molding material. | 09-09-2010 |
20100224971 | LEADLESS INTEGRATED CIRCUIT PACKAGE HAVING HIGH DENSITY CONTACTS - A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts protruding from a bottom surface of the encapsulation compound. | 09-09-2010 |
20100224972 | LEADLESS INTEGRATED CIRCUIT PACKAGE HAVING STANDOFF CONTACTS AND DIE ATTACH PAD - A leadless integrated circuit (IC) package comprising an IC chip mounted on a die attach pad and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die attach pad are all covered with a molding material, with portions of the electrical contacts and die attach pad protruding from a bottom surface of the molding material. | 09-09-2010 |
20100230792 | Premolded Substrates with Apertures for Semiconductor Die Packages with Stacked Dice, Said Packages, and Methods of Making the Same - Disclosed are premolded substrates for semiconductor die packages and methods of making such substrates. An exemplary premolded substrate comprises a leadframe having a first surface, a second surface, a central portion disposed between the first and second surfaces, and a plurality of electrically conductive leads disposed about the central portion; a body of electrically insulating material disposed in a portion of the central portion of the leadframe and between the leads of the leadframe; and an aperture disposed in the leadframe's central portion and between the leadframe's first and second surfaces. | 09-16-2010 |
20100237480 | SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD - A semiconductor device has a first layer pressing portion that is formed by crushing a ball neck formed by bonding an initial ball onto a first layer pad of a first layer semiconductor die and pressing the side of a wire folded onto the crushed ball neck, a first wire extended in the direction of a lead from the first layer pressing portion, and a second wire that is looped from a second layer pad of a second layer semiconductor die toward the first layer pressing portion and joined onto the second layer pad side of the first layer pressing portion. Thereby, the connection of wires is performed at a small number of times of bonding, while reducing damages caused on the semiconductor dies. | 09-23-2010 |
20100244212 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a bottom package including a first device over a first substrate and a second substrate over the first device; forming an encapsulation material over the bottom package with an opening over the second substrate; and forming a conductive post within the opening. | 09-30-2010 |
20100244213 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a lead frame | 09-30-2010 |
20100244214 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To improve the heat dissipation characteristics of a semiconductor device. | 09-30-2010 |
20100258921 | ADVANCED QUAD FLAT-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads electively have a plurality of locking grooves for enhancing the adhesion between the inner leads and the surrounding molding compound. | 10-14-2010 |
20100258922 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened. | 10-14-2010 |
20100258923 | PRE-MOLDED CLIP STRUCTURE - A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed. | 10-14-2010 |
20100258924 | PRE-MOLDED CLIP STRUCTURE - A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed. | 10-14-2010 |
20100258925 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 10-14-2010 |
20100258926 | RELAY BOARD AND SEMICONDUCTOR DEVICE HAVING THE RELAY BOARD - A relay board provided in a semiconductor device includes a first terminal, and a plurality of second terminals connecting to the first terminal by a wiring. The wiring connecting to the first terminal is split on the way so that the wiring connects to each of the second terminals. | 10-14-2010 |
20100264529 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle. | 10-21-2010 |
20100264530 | Stacked Chip Package Structure with Leadframe Having Bus Bar - The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad. | 10-21-2010 |
20100264531 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, ADHESIVE SHEET USED THEREIN, AND SEMICONDUCTOR DEVICE OBTAINED THEREBY - The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175° C. is 2000 Pa or more. | 10-21-2010 |
20100270665 | Leadframe - A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a method for making a leadframe includes patterning a sheet of metal to form a die paddle and leads, and forming a fillister in the back side of the die paddle. | 10-28-2010 |
20100270666 | Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes a semiconductor chip, a solid plate to which the semiconductor chip is bonded, and a bonding member made of a BiSn-based material interposed between the semiconductor chip and the solid plate, while the bonding member has a heat conduction path made of Ag for improving heat conductivity between the semiconductor chip and the solid plate. | 10-28-2010 |
20100276793 | HIGH PIN DENSITY SEMICONDUCTOR SYSTEM-IN-A-PACKAGE - Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The packages also contain multiple chips that are stacked vertically. The chips are connected through stud bumps, printed interconnect structures, and conductive pillars formed with the package. The packages also contain two different moldings layers that together operate as an encapsulation material. The semiconductor packages contain a full land pad array at both the bottom and the top of the package, allowing the packages to be used in a package-on-package configuration. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described. | 11-04-2010 |
20100283135 | LEAD FRAME FOR SEMICONDUCTOR DEVICE - A lead frame including a lead frame structure having a die support area and a plurality of electrical contact areas has shallow recesses formed on a surface of the lead frame structure. | 11-11-2010 |
20100283136 | QFN SEMICONDUCTOR PACKAGE - A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead. | 11-11-2010 |
20100283137 | QFN SEMICONDUCTOR PACKAGE - A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a trace interconnecting the intermediary terminal to the extended, outer terminal lead. | 11-11-2010 |
20100289129 | COPPER PLATE BONDING FOR HIGH PERFORMANCE SEMICONDUCTOR PACKAGING - A bonding plate forms high-performance, low-resistance interconnections between integrated circuit die and an electronic package lead frame. The bonding plate is made from copper, aluminum, or metalized silicon and is processed using standard semiconductor fabrication techniques to apply solder bumps and, optionally, copper pillars. The bonding plates are singulated from a wafer and applied to the die package using standard pick-and-place and solder reflow equipment and processes. This achieves high performance interconnect at low cost without the need for specialized tooling. | 11-18-2010 |
20100295161 | Method for Semiconductor Leadframes in Low Volume and Rapid Turnaround - A method for fabricating a leadframe for a QFN/SON semiconductor device by selecting ( | 11-25-2010 |
20100295162 | Semiconductor device - Portions of a wiring layer extending like cantilevers from an inner peripheral edge of an opening in a substrate are joined to respective terminals of a semiconductor chip mounted on the substrate. A junction portion between each portion of the wiring layer and the corresponding terminal is sealed with resin. | 11-25-2010 |
20100301464 | ASTERISK PAD - A method and structure for a semiconductor device can include a chip support having a one or more elongated structures formed in the chip support The elongated structures, which have a width and a length greater than the width, receive chip attach material such as epoxy during a chip attach process. Because each elongated feature is oriented such that an axis through a center of the length of each elongated feature points to a center of the chip support, the chip attach adhesive flows into the feature with minimal trapping of air. Trapped air can cause delamination of the chip from the chip support, or cracking of the chip and device failure. | 12-02-2010 |
20100301465 | LEAD FRAME, LEAD FRAME FABRICATION, AND SEMICONDUCTOR DEVICE - Lead frames and their fabricating method which reduce generation of defects in the process of fabricating semiconductor devices, in particular connection defects in wire bonding, thereby improving the product yield and reliability, and semiconductor devices using the lead frames and their fabricating method are provided. A method for fabricating a lead frame is characterized in including a process of forming a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface included in the convex portion and a second portion that extends from the first portion and does not overlap the first surface, and a process of bending the metal layer such that the second portion of the metal layer overlaps a second surface included in the convex portion that intersects the first surface. | 12-02-2010 |
20100308447 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least a die carried by a substrate, a plurality of bond pads disposed on the die, a plurality of conductive components, and a plurality of bond wires respectively connected between the plurality of bond pads and the plurality of conductive components. The plurality of bond pads respectively correspond to a plurality of signals, and include a first bond pad configured for transmitting/receiving a first signal and a second bond pad configured for transmitting/receiving a second signal. The plurality of conductive components include a first conductive component and a second conductive component. The first conductive component is bond-wired to the first bond pad, and the second conductive component is bond-wired to the second bond pad. The first conductive component and the second conductive component are separated by at least a third conductive component of the plurality of conductive components, and the first signal is asserted when the second signal is asserted. | 12-09-2010 |
20100308448 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device has a tab having a semiconductor chip fixed thereto, a plurality of inner leads, a plurality of outer leads formed integrally with the inner leads, a plurality of wires coupling the electrode pads of the semiconductor chip to the inner leads, and a molded body having the semiconductor chip molded therein. Over a surface of each of the outer leads protruding from the molded body, an outer plating including lead-free platings is formed. The outer plating has, in a thickness direction thereof, a first lead-free plating and a second lead-free plating, the first and second lead-free platings having the same composition and meeting at an interface. The first and second lead-free platings are formed under different conditions and may have different physical properties. | 12-09-2010 |
20100314730 | Stacked hybrid interposer through silicon via (TSV) package - An integrated circuit (IC) device is provided. The IC device includes a first die having a surface with a first pad formed thereon, a second die having a surface with a second pad formed thereon, and a substrate interposer that couples the first pad to the second pad. The substrate interposer is coupled to the surface of the first die and the surface of the second die. | 12-16-2010 |
20100314731 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HIGH LEAD COUNT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead. | 12-16-2010 |
20100314732 | ENHANCED INTEGRATED CIRCUIT PACKAGE - A semiconductor including a selectively plated lead frame is disclosed. The lead frame contains a die pad and a plurality of lead fingers, where each lead finger is formed with a bonding pad on the center portion of the lead finger by selective plating. The surface area of the lead finger material is increased so the adhesion to molding material is improved. The edges of the lead finger tips are half etched to further increase the surface area of lead finger material. A method of manufacturing the lead frame is also provided. | 12-16-2010 |
20100320579 | Metallic Leadframes Having Laser-Treated Surfaces for Improved Adhesion to Polymeric Compounds - A leadframe for the assembly of a semiconductor chip has regions ( | 12-23-2010 |
20100320580 | EQUIPOTENTIAL PAD CONNECTION - A conduction member is used to connect in-chip equipotential pads | 12-23-2010 |
20110001226 | LEAD FRAME, AND ELECTRONIC PART USING THE SAME - A lead frame includes a die pad on which at least one IC chip is mounted, a plurality of leads that electrically connect the IC chip and at least one external element, and a plurality of projections that are formed in at least one edge of the die pad. The projections are used as at least one bonding point that connect with at least one free terminal of the IC chip or as references of positioning when the IC chip is arranged on the die pad. | 01-06-2011 |
20110001227 | Semiconductor Chip Secured to Leadframe by Friction - A semiconductor device ( | 01-06-2011 |
20110001228 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in which the semiconductor chip is resin molded. By further stepwise shortening the chip-side tip end portions of the leads as the first edge or side of the principal surface of the semiconductor chip goes away from the middle portion toward the both end portions thereof, and shortening the tip end portions of those of first leads corresponding to the middle portion of the first edge or side of the principal surface which are adjacent to second leads located closer to the both end portions of the first edge or side, the distances between second wires connected to the second leads and the tip end portions of the first leads adjacent to the second leads can be increased. As a result, it is possible to prevent the wire short-circuit defect even when wire sweep occurs due to the flow resistance of a mold resin. | 01-06-2011 |
20110006410 | Semiconductor wiring assembly, semiconductor composite wiring assembly, and resin-sealed semiconductor device - A semiconductor composite wiring assembly includes a wiring assembly and a lead frame. A copper wiring layer of the wiring assembly includes first terminals, second terminals, and wiring sections connecting the terminals. The second terminals and the lead frame are electrically connected by connecting members. The lead frame includes a die pad for mounting the wiring assembly, and lead sections located at outer positions. The die pad includes a central area in which a semiconductor chip is mounted via the wiring assembly, and a peripheral area connected to the central area with spaces formed therebetween that serve as resin-seal inflow spaces. The wiring assembly is positioned over the central area and the peripheral area so as to cover the central area completely and the peripheral area partially, and at least the central area and the peripheral area of the die pad are glued to the wiring assembly by resin paste. | 01-13-2011 |
20110006411 | Simplified multichip packaging and package design - A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated circuit die can face in the same direction, and can be wire bonded to the same surfaces of the leads. This avoids wire bonding complications that are often encountered in multichip integrated circuit package designs. | 01-13-2011 |
20110012242 | LEAD FRAME BASED CERAMIC AIR CAVITY PACKAGE - A ceramic semiconductor package provides for being surface mounted on a printed circuit board or other mounting surface. A ceramic frame is directly attached to a lead frame to define a cavity in which the base of a semiconductor device is mounted to the portion of the lead frame exposed at the bottom of the cavity. Interface terminals of the semiconductor device are attached to electrical contacts on the ceramic frame inside the cavity. The ceramic package provides a hermetic insulated path through which the signals can be routed from the device to the external leads. Additionally, because the semiconductor device is directly attached to the lead frame, power dissipation, i.e., heat dissipation, is more effectively provided by this direct connection without intervening layers of ceramic or conductor. | 01-20-2011 |
20110012243 | Leadframe Having Delamination Resistant Die Pad - A lead frame ( | 01-20-2011 |
20110012244 | Semiconductor Chip Package - A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively. | 01-20-2011 |
20110012245 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package. | 01-20-2011 |
20110012246 | Flat Leadless Packages and Stacked Leadless Package Assemblies - A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink. | 01-20-2011 |
20110018111 | LEADFRAME FEATURE TO MINIMIZE FLIP-CHIP SEMICONDUCTOR DIE COLLAPSE DURING FLIP-CHIP REFLOW - A support feature on a leadframe to support a semiconductor die during placement of the die on the leadframe and minimize the collapsing effect of the connector bumps of the die after reflowing. In some embodiments, the support features are formed from material that is different from the leadframe, such as by a ball drop process or a plating process. In some embodiments, the support features are formed from the leadframe material, such as by etching. In some embodiments, the support features are covered with a coating material. | 01-27-2011 |
20110024884 | Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors - A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level. | 02-03-2011 |
20110024885 | METHOD FOR MAKING SEMICONDUCTOR CHIPS HAVING COATED PORTIONS - A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating, and depositing a coating on the stacked lead frames using, for example, an evaporative coating machine. In this manner, the coating is deposited on exposed portions of chips, such as its edges, and is not deposited on masked portions of chips, such as bond pads. | 02-03-2011 |
20110024886 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 02-03-2011 |
20110037153 | HIGH BOND LINE THICKNESS FOR SEMICONDUCTOR DEVICES - Die attach methods used in making semiconductor devices and the semiconductor devices resulting from those methods are described. The methods include providing a leadframe with a die attach pad, using a boundary feature(s) containing a bond wire to define a perimeter on the die attach pad, depositing a conductive material (such as solder) within the perimeter, and then attaching a die containing an integrated circuit device to the die attach pad by using the conductive material. The boundary feature(s) allow an increased thickness of conductive material to be used, resulting in increased bond line thickness and increasing the durability and performance of the resulting semiconductor package. Other embodiments are described. | 02-17-2011 |
20110037154 | Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier - An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure. | 02-17-2011 |
20110042793 | LEAD FRAME ASSEMBLY FOR A SEMICONDUCTOR PACKAGE - A lead frame assembly includes a first lead frame panel having a die receiving area for receiving a semiconductor die, the die having an upper surface having one or more die bond pads located thereon. A second lead frame panel includes integral leads, each integral lead including a terminal, a connecting element extending from the terminal, and a shaped contact located at an end of the connecting element. The second lead frame panel is adapted to be stacked on the first lead frame panel to position each terminal laterally of a respective die receiving area. The positioning of the terminals locates each shaped contact for contact with a respective die bond pad to establish an electrical connection between the die bond pad and the respective terminal when the semiconductor die is mounted on the respective die receiving area. | 02-24-2011 |
20110042794 | QFN SEMICONDUCTOR PACKAGE AND CIRCUIT BOARD STRUCTURE ADAPTED FOR THE SAME - A QFN package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an outer terminal lead; an intermediary terminal disposed between the inner terminal lead and the outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the outer terminal lead. A circuit board includes a core layer; a first metal trace disposed over a first side of the core layer; and a first solder mask covering the first metal trace. The QFN package is mounted over the first solder mask. No metal pad of the first metal trace is formed within an area corresponding to the intermediary terminal. | 02-24-2011 |
20110049690 | Direct contract leadless package for high current devices - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 03-03-2011 |
20110049691 | SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING THE SAME - A semiconductor package includes a chip, a carrier, a bonding wire and a molding compound. The chip includes a pad. The carrier includes a finger and has an upper surface and a lower surface opposite to the upper surface, wherein the upper surface supports the chip. The bonding wire is extended from the finger to the pad for electrically connecting the chip to the carrier, wherein the bonding wire defines a projection portion on the upper surface of the carrier, a straight line is defined to pass through the finger and pad, there is a predetermined angle between the tangent line of the projection portion at the finger and the straight line. The molding compound seals the chip and the bonding wire, and covers the carrier. | 03-03-2011 |
20110049692 | CONNECTION DEVICE BEWTEEN TRANSISTOR AND LEAD FRAME - A connection device includes a transistor, a lead frame, a first connection member and a second connection member. The signal is electronically connected between the transistor and the lead frame by the first and second connection members. The second connection member is located above the first connection member so as to increase the communication area for the signals and reduce the resistance between the transistor and the lead frame. | 03-03-2011 |
20110049693 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME THEREOF - A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. | 03-03-2011 |
20110057299 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (α portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region. | 03-10-2011 |
20110062568 | FOLDED LANDS AND VIAS FOR MULTICHIP SEMICONDUCTOR PACKAGES - Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame that has been folded to create folded leads that form a customized array of land pads and vias. The lead frame contains both longer folded lead and shorter folded leads. The longer leads can be folded so that an upper part of the longer leads form vias, the lower part forms part of a land pad array, and a substantially flat part that is connected to a first die containing an IC. The shorter leads can be folded so that a lower part forms part of a land pad array and the short leads are connected to a second die containing in IC. The folded leads can be routed according to the requirements of each specific IC die to which they are connected and therefore can support multiple dies in the semiconductor package. Other embodiments are also described. | 03-17-2011 |
20110062569 | SEMICONDUCTOR DEVICE PACKAGE WITH DOWN-SET LEADS - A QFP type packaged device includes down-set leads to allow for more I/O's and a smaller foot print. The device includes a die attached to a flag of a lead frame. Die pads are electrically connected to leads of the lead frame with wires. The leads are bent and include indentations so that they are exposed at the bottom side of the package. The leads are also trimmed so that they do not extend out of the sides of the packaged device. | 03-17-2011 |
20110062570 | ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES - Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described. | 03-17-2011 |
20110068446 | Semiconductor Chip Attach Configuration Having Improved Thermal Characteristics - A semiconductor chip | 03-24-2011 |
20110068447 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CIRCUITRY STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead to include a first tip at one end, a second tip on the end opposite from the first tip with a connect area between each end located above the first tip, and a first tier section or a second tier section located between the connect area and the second tip; connecting a bottom component assembly to the first tier section or the second tier section; connecting a top component assembly over the connect area; and applying an encapsulant over and under the connect area with the first tip exposed. | 03-24-2011 |
20110068448 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAP LAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: attaching a semiconductor die to a die pad of a leadframe; forming a cap layer on top of the semiconductor die for acting as a ground plane or a power plane; and connecting the semiconductor die to the cap layer through a cap bonding wire. | 03-24-2011 |
20110068449 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a stepped pad, a plurality of first bonding wires and a second bonding wire. The first semiconductor chip is stacked on a substrate having a plurality of bonding pads, the first semiconductor chip having a plurality of first chips pads formed along a side portion of the first semiconductor chip. The second semiconductor chip is stacked like a step of a staircase on the first semiconductor chip to form a stepped portion through which the first chip pads are exposed on the first semiconductor chip, the second semiconductor chip having a plurality of second chip pads formed along a side portion of the first semiconductor chip. The stepped pad is arranged between the first chip pads on the stepped portion of the first semiconductor chip, the stepped pad including an adhesive pad adhered to the first semiconductor chip and a conductive pad formed on the adhesive pad. A plurality of the first bonding wires electrically connect between the one second chip pad and the one first chip pad and/or between the one first chip pad and the one bonding pad. The second bonding wire electrically connects between the one second chip pad and the one bonding pad using the stepped pad. | 03-24-2011 |
20110068450 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads. | 03-24-2011 |
20110068451 | MULTI-CHIP SEMICONDUCTOR CONNECTOR - In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die. | 03-24-2011 |
20110074000 | OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - An optoelectronic component including a connection carrier comprising a structured carrier strip in which interspaces are filled with an electrically insulating material and an optoelectronic semiconductor chip attached and electrically connected to a top portion of the connection carrier, wherein the electrically insulating material terminates substantially flush with the carrier strip in places or the carrier strip projects beyond the electrically insulating material, and the carrier strip is not covered by the electrically insulating material on the top portion and/or on a bottom portion of the connection carrier. | 03-31-2011 |
20110079885 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHAPED LEAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package lead having a retention structure around a perimeter of the package lead with a first concave surface, a ridge, and a second concave surface; forming a die attach paddle adjacent the package lead and having an another retention structure around a perimeter of the die attach paddle with an another first concave surface, an another ridge, and an another second concave surface; attaching an integrated circuit die to the die attach paddle; connecting a conductive connector to the integrated circuit die and the package lead; and applying an encapsulation over the integrated circuit die, the encapsulation conformed to the retention structure and exposing a portion of the package lead. | 04-07-2011 |
20110079886 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle. | 04-07-2011 |
20110079887 | LEAD FRAME AND METHOD OF MANUFACTURING THE SAME - A lead frame having improved connectivity with a molded portion and a method of manufacturing the lead frame are provided. The lead frame includes a die pad on which a semiconductor chip is to be disposed; at least one lead portion arranged to be connected to the semiconductor chip; and at least one plating layer formed on at least one of the at least one lead portion and the die pad, wherein a top surface of the at least one plating layer has an uneven portion having a first average surface roughness. | 04-07-2011 |
20110079888 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PROTECTIVE COATING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead-frame having a die attach paddle and a contact pad connected by a link; mounting an integrated circuit die over the die attach paddle; molding a package body on the lead-frame and the integrated circuit die including leaving portions of the die attach paddle, the contact pad, and the link exposed from the package body; forming an exposed edge by etching away the link between the contact pad, and the die attach paddle; and depositing a solder-resistant layer on the exposed edge. | 04-07-2011 |
20110084372 | PACKAGE CARRIER, SEMICONDUCTOR PACKAGE, AND PROCESS FOR FABRICATING SAME - A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments. | 04-14-2011 |
20110089546 | MULTIPLE LEADFRAME PACKAGE - Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and having a second plurality of electrical leads, and a plurality of direct electrical connectors between the first and second leadframes, where such direct electrical connectors control the distance between the leadframes. Additional device components can include a primary die, an encapsulant, a secondary die, an inductor and/or a capacitor. The plurality of direct electrical connectors can comprise polymer balls having solder disposed thereabout. Alternatively, the direct electrical connectors can comprise metal tabs that extend from one leadframe to the other. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes. | 04-21-2011 |
20110089547 | METHODS AND DEVICES FOR MANUFACTURING CANTILEVER LEADS IN A SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package includes providing a metallic leadframe having a plurality of cantilever leads and a mounting area for mounting a die, and disposing one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. The method further includes mounting the die in the mounting area and electrically connecting the die to the cantilever leads, and then encapsulating at least a portion of the die, the leadframe, and the supports with an encapsulant. | 04-21-2011 |
20110089548 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are constituted by a tab ( | 04-21-2011 |
20110089549 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a lead frame having a die pad portion or a circuit board, one or more semiconductor elements mounted on the die pad portion of the lead frame or on the circuit board, a copper wire that electrically connects electrical joints provided on the lead frame or the circuit board to an electrode pad provided on the semiconductor element, and an encapsulating member which encapsulates the semiconductor element and the copper wire, wherein the electrode pad and/or the encapsulating member having predetermined properties are combined with the copper wire having predetermined properties. | 04-21-2011 |
20110095409 | Method of Attaching an Interconnection Plate to a Semiconductor Die within a Leadframe Package - A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package. | 04-28-2011 |
20110095410 | WAFER LEVEL SEMICONDUCTOR DEVICE CONNECTOR - This document discusses, among other things, a semiconductor connector including a conductive pad in a recessed pad area on a surface of a dielectric, the dielectric material configured to be activated to conductive plating deposition using laser ablation. | 04-28-2011 |
20110095411 | Wirebond-less Semiconductor Package - A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts. | 04-28-2011 |
20110095412 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 04-28-2011 |
20110108965 | SEMICONDUCTOR DEVICE PACKAGE - A method for forming a semiconductor device package includes providing a lead frame array having a plurality of leads. Each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and each of the openings is at least partially filled with a solder wettable material. A plurality of semiconductor devices are attached to the lead frame array. The plurality of semiconductor devices are encapsulated, and, after encapsulating, the plurality of semiconductor devices are separated along separation lines which intersect the openings | 05-12-2011 |
20110108966 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a conductive layer having a first surface and a second surface; forming first concave trenches in the first surface of the conductive layer and the first concave trenches are connected by a first flat region of the first surface; connecting an integrated circuit to the first flat region with a conductive interconnect; encapsulating the integrated circuit with an encapsulation that fills the first concave trenches; and forming second concave trenches having a similar size in the second surface of the conductive layer with the second concave trenches connected by a second flat region that is larger than the first flat region, and the second concave trenches are formed through the conductive layer to expose the encapsulation. | 05-12-2011 |
20110108967 | SEMICONDUCTOR CHIP GRID ARRAY PACKAGE AND METHOD FOR FABRICATING SAME - A semiconductor chip grid array package includes a die attach pad and a plurality of connector pads. A semiconductor die is mounted on the die attach pad, the semiconductor die having external connection terminals electrically connected respectively to the connector pads. An encapsulating material encapsulates the die and connector pads. A stud protrudes from each of the connector pads for providing an external electrical contact for the semiconductor chip grid array package. Each of the connector pads and respective studs are formed from an electrically conductive sheet. The connector pads have a thickness of at least 60% of the thickness of the conductive sheet and the respective studs have a thickness of no more than 40% of the thickness of the conductive sheet. | 05-12-2011 |
20110108968 | Semiconductor package with metal straps - A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode. | 05-12-2011 |
20110108969 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die paddle, having paddle projections along a paddle peripheral side; forming a lead terminal having a lead extension with the lead extension extending towards the paddle peripheral side and between the paddle projections; mounting an integrated circuit over the die paddle; connecting the integrated circuit and the lead extension; and forming an encapsulation over the die paddle and covering the integrated circuit and lead extension. | 05-12-2011 |
20110108970 | SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF - A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed. | 05-12-2011 |
20110115061 | ELECTRONIC DEVICE INCLUDING A PACKAGING SUBSTRATE HAVING A TRENCH - An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate. | 05-19-2011 |
20110115062 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Terminals ( | 05-19-2011 |
20110115063 | Integrated Circuit Packaging with Split Paddle - An IC package includes ground paddle(s), power paddle(s), a lead frame, a die, and electrically conductive input/output circuit pads, ground circuit pads, and bond wires. The lead frame may include input/output (I/O) pads positioned near the perimeter of the lead frame and around the ground paddle(s) and power paddle(s). The die may be positioned on one of the ground paddles and may include die terminals. Each I/O circuit pad may be positioned on and connected with one of the I/O pads. The ground circuit pads may be positioned on said one ground paddle around the die between the die and the I/O circuit pads. Each ground circuit pad may be connected to said one ground paddle. Each bond wire may connect a die terminal to an I/O circuit pad and/or a ground circuit pad. A bond wire may connect a die terminal to a power paddle. | 05-19-2011 |
20110121441 | DIODE LEADFRAME FOR SOLAR MODULE ASSEMBLY - A leadframe design for a diode or other semiconductor device that reduces stress on the device and provides increased heat dissipation is provided. According to various embodiments, the leadframe has a contoured profile including a recessed area and a raised surface within the recessed area. The surface supports the device such that the edges of the device extend past the surface. Also provided are device assemblies including the novel leadframes. In certain embodiments, the assemblies include one or more leadframes attached via a solder joint to a device. According to various embodiments, the leadframes are attached to the front side of the device, back side of the device or both. In particular embodiments, the device is a bypass diode for one or more solar cells in a solar module. | 05-26-2011 |
20110127659 | PACKAGE INCLUDING AN INTERPOSER HAVING AT LEAST ONE TOPOLOGICAL FEATURE - Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed. | 06-02-2011 |
20110133321 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board. | 06-09-2011 |
20110133322 | LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME - A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins. | 06-09-2011 |
20110133323 | SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP - A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires. | 06-09-2011 |
20110140251 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die. | 06-16-2011 |
20110140252 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL ROW LEAD-FRAME HAVING TOP AND BOTTOM TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation. | 06-16-2011 |
20110140253 | DAP GROUND BOND ENHANCEMENT - A variety of semiconductor package arrangements and packaging methods are described that improve the reliability of bonding wires that down bond a die to a die attach pad. In one aspect, selected portions of the top surface of a lead frame (which may be in panel form) are plated (e.g., silver plated) to facilitate wire bonding. The plating covers some, but not all of a die attach surface of the die attach pad. In some preferred embodiments, the plating on the die attach pad is arranged as a peripheral ring that surrounds an unplated central region of the die support surface. In other embodiments, the plating on the die attach pad takes the form of bars or other geometric patterns that do not fully cover the die support surface. Unplated portions of the die support surface are roughened to improve the adherence of the die to the die attach pad, thereby reducing the probability of die attach pad delamination and the associated risks to down bonded bonding wires. The described lead frames may be used in a variety of packages. Most commonly, a die is attached to the die support surface of the die attach pad and electrically connected to the lead frame leads by wire bonding as appropriate. At least one of the die's bond pads (typically the ground bond pad(s)) is down bonded to the die attach pad. The die, the bonding wires and at least portions of the lead frame are then typically encapsulated with a plastic encapsulant material while leaving a contact surface of the die attach pad exposed to facilitate electrically coupling the die attach pad to an external device. | 06-16-2011 |
20110140254 | Panel Based Lead Frame Packaging Method And Device - A packaged semiconductor die has a preformed lead frame with a central recessed portion, and a plurality of conductive leads. An integrated circuit die has a top surface and a bottom surface opposite thereto, with the top surface having a plurality of bonding pads for electrical connection to the die. The die is positioned in the central recessed portion with the top surface having the bonding pads facing upward, and the bottom surface in contact with the recessed portion. Each of the leads has a top portion and a bottom portion. The leads are spaced apart and insulated from the central recessed portion. A conductive layer is deposited on the top surface of the die and the top portion of the leads and is patterned to electrically connect certain of the bonding pads of the die to certain of the conductive leads. An insulator covers the conductive layer. The present invention also relates to a method of packaging such an integrated circuit die. | 06-16-2011 |
20110140255 | SEMICONDUCTOR DIE PACKAGE INCLUDING IC DRIVER AND BRIDGE - A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe. | 06-16-2011 |
20110140256 | SEMICONDUCTOR DEVICE, SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane. | 06-16-2011 |
20110156227 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques. | 06-30-2011 |
20110156228 | SEMICONDUCTOR DEVICE - A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact. | 06-30-2011 |
20110156229 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged. | 06-30-2011 |
20110163430 | Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof - A package structure and related methods are described. In one embodiment, the package structure includes a chip, a plurality of leads disposed around and electrically coupled to the chip, and a package body formed over the chip and the plurality of leads. At least one lead includes a central metal layer having an upper surface and a lower surface, a first protruding metal block having an upper surface and extending upwardly from the upper surface of the central metal layer, a second protruding metal block having a lower surface and extending downwardly from the lower surface of the central metal layer, a first finish layer on the upper surface of the first protruding metal block, and a second finish layer on the lower surface of the second protruding metal block. The package body substantially covers the first protruding metal block and the first finish layer of each of the leads. | 07-07-2011 |
20110163431 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Retaining regions | 07-07-2011 |
20110163432 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Protrusions | 07-07-2011 |
20110163433 | LEAD FRAME SUBSTRATE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR APPARATUS - A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately. | 07-07-2011 |
20110163434 | STACKED POWER CONVERTER STRUCTURE AND METHOD - A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad. | 07-07-2011 |
20110163435 | Lead frame substrate and method of manufacturing the same, and semiconductor device - A lead frame substrate, includes: a metal plate having first and second surfaces; a semiconductor element mounting section, semiconductor element electrode connection terminals, and a first outer frame section formed on the first surface; external connection terminals formed on the second surface and electrically connected with the semiconductor element electrode connection terminals; a second outer frame section formed on the second surface; and a resin layer formed on a gap between the first outer frame and the second outer frame. Each external connection terminal buried in the resin layer has at least one projection formed on a side surface thereof throughout a side lower portion of the first surface. | 07-07-2011 |
20110169151 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD INTERLOCKING MECHANISMS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having an upper portion and a bottom portion with a first overhang portion from a top surface of the upper portion and the lead also having serrations along upper vertical sides intersecting the top surface; forming an upper contact plate on the top surface; forming a bottom contact plate on a bottom surface of the bottom portion; attaching an integrated circuit die over the upper portion; and encapsulating the upper portion and the integrated circuit die with an encapsulation leaving the bottom portion exposed. | 07-14-2011 |
20110169152 | SEMICONDUCTOR PACKAGE - In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package. | 07-14-2011 |
20110169153 | Lead frame substrate and method of manufacturing the same - A method includes: forming a photoresist pattern to form each of a semiconductor element mounting section on which a semiconductor element is mounted, semiconductor element electrode connection terminals for connection with electrodes of the semiconductor element, and a first outer frame section on a first surface of a metal plate; forming a photoresist pattern to form each of external connection terminals, a second outer frame section, and grooves in at least a part of the second outer frame section on a second surface of the metal plate; etching a metal plate exposing section, in which the metal plate of the second surface is exposed, to form holes that do not pass through the metal plate exposing section and grooves that run from an inside to an outside of the second outer frame section; coating a pre-mold resin on the holes and the grooves, and heating the pre-mold resin under pressure using a flat-bed press to form a resin layer; and etching the first surface to form the semiconductor element mounting section, the semiconductor element electrode connection terminals electrically connected with the external connection terminals, and the first outer frame section. | 07-14-2011 |
20110180916 | MULTI-CHIP PACKAGE HAVING FRAME INTERPOSER - A multi-chip package is provided. The multi-chip package may include a frame interposer, a first chip stack with n number of semiconductor chips on a first surface of the frame interposer, and a second chip stack with m number of semiconductor chips on a second surface of the frame interposer. The interposer may have first and second openings. The first chip stack may extend over one of the first and second openings and may expose the other of the first and second openings. The second chip stack may extend over the other of the first and second openings and may expose the one of the first and second openings. | 07-28-2011 |
20110186975 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a substrate with a first surface and an opposite second surface, a plurality of metal rods throughout the first surface and the second surface of the substrate, a reflector surrounding the first surface of the substrate to form a functional area, a glass reflection layer covering the surfaces of reflector and the functional area and exposing a part of a first electrode area and a part of a second electrode area, at least one semiconductor chip adhered on the functional area, and a transparent gel covering the at least one semiconductor chip. | 08-04-2011 |
20110186976 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead | 08-04-2011 |
20110193206 | STACKABLE SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE IN PRE-MOLDED CARRIER FRAME - Semiconductor packages that contain multiple stacked chips that are embedded in a pre-molded carrier frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. The land pad array contains inner terminals that are formed by first stud bumps that are located on a lower die. The land pad array also contains middle terminals that are formed by first conductive vias in a first molding layer embedding the first die. The first conductive vias are connected to second stud bumps that are located on a second die that is embedded in a second molding layer. The second molding layer contains second conductive vias that are connected to a carrier frame, the bottom of which forms the outer terminals of the land pad array. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability that are especially useful for portable and ultra-portable electronic apparatus. Other embodiments are also described. | 08-11-2011 |
20110193207 | LEAD FRAME FOR SEMICONDUCTOR DIE - A lead frame for providing electrical interconnection to a semiconductor die has a generally rectangular flag area having first and second major surfaces and four sides. The flag area is sized and shaped to receive a semiconductor die on one of the first and second major surfaces. A first row of leads is located adjacent to a first one of the four sides of the flag area and a second row of leads is located adjacent to a second one of the four sides of the flag area, where the second one of the four sides is adjacent to the first one of the four sides. The remaining two sides do not have any adjacent leads. | 08-11-2011 |
20110193208 | SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET AND ITS MANUFACTURING METHOD - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area. | 08-11-2011 |
20110198742 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab. In such a semiconductor device, a circuit formed in the semiconductor element in a monolithic manner is comprised of a plurality of circuit parts and, in a specified circuit part (a low noise amplifier) which forms a portion of the circuit parts, all grounding electrode terminals out of electrode terminals of the semiconductor element are not connected to the tab through wires but are connected with the leads through wires. | 08-18-2011 |
20110204501 | INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING NON-LEADED PACKAGE - An integrated circuit packaging system includes: a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; each one of the plurality of leads includes first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and a lead-to-lead gap formed between the second terminal ends of alternating leads in excess of the predetermined interval gap. | 08-25-2011 |
20110204502 | Method of Manufacturing A Semiconductor Device - The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding. Accordingly, when cutting the suspending leads, corner portions of the back surface of the sealing body can be supported by a flat portion of a holder portion in a cutting die which flat portion has an area sufficiently wider than a cutting allowance of the suspending leads, whereby it is possible to prevent chipping of the resin and improve the quality of the semiconductor device (QFN). | 08-25-2011 |
20110204503 | MICROELECTRONIC PACKAGE ASSEMBLY, METHOD FOR DISCONNECTING A MICROELECTRONIC PACKAGE - A microelectronic package assembly comprises a lead frame having a holding bar ( | 08-25-2011 |
20110210433 | SEMICONDUCTOR CHIP AND FILM AND TAB PACKAGE COMPRISING THE CHIP AND FILM - A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip. The connection surface includes a first edge and a second edge that are substantially parallel to each other and are opposite each other on a respective first side and second side of the chip, and a third edge and fourth edge that are substantially perpendicular to the first and second edges, and are opposite each other on a respective third side and fourth side of the chip. A plurality of input pads of the set of input pads are adjacent the first edge, and are arranged in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads of the set of output pads are adjacent the second edge, and are arranged in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads of the set of output pads are located between the first row and the second row. The plurality of second output pads include at least first and second outermost pads located a certain distance from the respective third edge and fourth edge, and at least first and second inner pads located a greater distance from the respective third edge and fourth edge than the first and second outermost pads. | 09-01-2011 |
20110210434 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's. | 09-01-2011 |
20110215454 | COL PACKAGE HAVING SMALL CHIP HIDDEN BETWEEN LEADS - A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities. | 09-08-2011 |
20110215455 | Semiconductor device capable of switching operation mode and operation mode setting method therefor - A semiconductor device includes a chip, a plurality of pads that is formed along the perimeter of the chip, and that includes a first pad and a second pad placed next to the first pad, and a circuit that is formed on the chip, and that is coupled to the first and second pads. The circuit includes first and second conductivity type transistors that are coupled between first and second reference potentials and a comparator that includes a first input node coupled to the first pad and a second input node coupled to the second pad, and that compares a potential of the first input node with a potential of the second input node. The first pad is coupled to gate electrodes of the first and second conductivity type transistors, and the second pad is coupled to drain electrodes of the first and second conductivity type transistors. | 09-08-2011 |
20110221049 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield. | 09-15-2011 |
20110221050 | Electronic device, relay member, and mounting substrate, and method for manufacturing the electronic device - The relay member is at least partly positioned between the semiconductor chip and lead in the plan view, and metal pieces insulated from one another are arranged on the surface. At least either of the first wire and the second wire has their respective other ends and joined to at least one of the metal pieces arranged on the surface of the relay member. Also, the first wire and the second wire have their respective other ends and joined to each other at that part of the relay member which is between the semiconductor chip and the lead. The foregoing structure is highly reliable and versatile for wire connection. | 09-15-2011 |
20110221051 | LEADFRAME BASED MULTI TERMINAL IC PACKAGE - A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound. | 09-15-2011 |
20110227207 | STACKED DUAL CHIP PACKAGE AND METHOD OF FABRICATION - The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication. | 09-22-2011 |
20110227208 | Structure and Manufacture Method For Multi-Row Lead Frame and Semiconductor Package - The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching. | 09-22-2011 |
20110233746 | Dual-leadframe Multi-chip Package and Method of Manufacture - A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. | 09-29-2011 |
20110241190 | Semiconductor Package - A method of manufacturing a semiconductor package includes providing a carrier and attaching at least one semiconductor piece to the carrier. An encapsulant is deposited onto the at least one semiconductor piece to form an encapsulated semiconductor arrangement. The encapsulated semiconductor arrangement is then singulated in at least two semiconductor packages, wherein each package includes a semiconductor die separated from the semiconductor piece during singulation. | 10-06-2011 |
20110241191 | SEMICONDUCTOR LAMINATION PACKAGE AND METHOD OF PRODUCING SEMICONDUCTOR LAMINATION PACKAGE - A semiconductor lamination package includes a first package with a first semiconductor chip mounted thereon and a second package with a second semiconductor chip mounted thereon. The first package includes first mounting pads disposed on a bottom surface thereof for transmitting an input/output signal externally from the first semiconductor IC chip. The second package is laminated on the bottom surface of the first package. The second package includes a package substrate having first bonding pads disposed on one surface thereof and second mounting pads disposed on the other surface and electrically connected to the first bonding pads; a first wiring portion for electrically connecting the first bonding pads to a chip pad of the second semiconductor chip; and a package bonding substrate having connecting pads disposed on an upper surface of the second package and a wiring path for electrically connecting the connecting pads and the chip pad. | 10-06-2011 |
20110248391 | INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package stacking system includes: providing a bottom package including: providing a first lead frame, forming a bottom package body having the first lead frame in an off-centered parting line position, and forming bottom connection leads of the first lead frame for providing coplanar contacts at an end of the bottom connection leads; mounting a top package on the bottom package including: providing a second lead frame, forming a top package body on the second lead frame, and reforming top connection leads of the second lead frame for over-lapping contact areas on the bottom connection leads of the bottom package; and applying a conductive adhesive on the contact areas for electrically connecting the top connection leads and the bottom connection leads. | 10-13-2011 |
20110248392 | Ball-Grid Array Device Having Chip Assembled on Half-Etched metal Leadframe - A ball grid array device ( | 10-13-2011 |
20110248393 | LEAD FRAME FOR SEMICONDUCTOR DEVICE - A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame. | 10-13-2011 |
20110248394 | LEADFRAME PACKAGE FOR HIGH-SPEED DATA RATE APPLICATIONS - A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm. | 10-13-2011 |
20110248395 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead. | 10-13-2011 |
20110254143 | Chip package structure and method of making the same - Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame. | 10-20-2011 |
20110254144 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member and at least one die in a stacked configuration attached to the support member. The support member may include a leadframe disposed longitudinally between first and second ends and latitudinally between first and second sides. The leadframe includes a lead extending between the first end and the first side. | 10-20-2011 |
20110260306 | LEAD FRAME PACKAGE STRUCTURE FOR SIDE-BY-SIDE DISPOSED CHIPS - A lead frame package structure for side-by-side disposed chips including a lead frame, at least two chips, and a package material. The lead frame includes a plurality of inner leads; a plurality of outer leads; and at least two chip carrying areas having different horizontal levels. The chips are of different sizes and are respectively disposed on the chip carrying areas. The package material encapsulate the inner leads, the chip carrying areas and the chips, wherein the outer leads exposed out of the package material extend from the inner leads and have different horizontal levels. | 10-27-2011 |
20110260307 | INTEGRATED CIRCUIT INCLUDING BOND WIRE DIRECTLY BONDED TO PAD - An integrated circuit includes a chip including a copper bond pad metallization, and a copper bond wire including a copper ball. The copper ball is bonded directly to the copper bond pad. | 10-27-2011 |
20110260308 | CIRCUIT BOARD STRUCTURE, PACKAGING STRUCTURE AND METHOD FOR MAKING THE SAME - A circuit board structure, a packaging structure and a method for making the same are disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure. | 10-27-2011 |
20110260309 | SEMICONDUCTOR PACKAGE, TEST SOCKET AND RELATED METHODS - Provided are a socket, a semiconductor package, a test device and a method of manufacturing a semiconductor package. A socket to test a semiconductor package comprising a housing, a trench receiving a semiconductor package in the housing, at least one probe connected to the semiconductor package at a bottom of the trench, and at least one connector electrically connecting a plurality of contact points exposed at a side of the semiconductor package when the semiconductor package is inserted into the trench. A semiconductor package with contacts exposed from a side of a package substrate, and a method of manufacturing such a semiconductor package are also disclosed. | 10-27-2011 |
20110260310 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a quad flat non-leaded (QFN) package includes: forming die pads and bump solder pads by pressing a metal plate, wherein each of the die pads and the bump solder pads has at least a cross-sectional area greater than another located underneath along its thickness dimension, thereby enabling the die pads and the solder pads to be securely embedded in an encapsulant. The method further includes removing the metal plate after forming the encapsulant so as to prevent the encapsulant from overflowing onto the bottom surfaces of the bump solder pads. | 10-27-2011 |
20110260311 | RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame. | 10-27-2011 |
20110260312 | SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME - A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. | 10-27-2011 |
20110260313 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED ENCAPSULATION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a carrier; mounting an integrated circuit die on a top side of the carrier; connecting the integrated circuit die with the carrier; forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress; and forming a first external interconnect on the top side of the carrier adjacent to and separated from the encapsulation including forming a second external interconnect on a bottom side of the carrier opposite the first external interconnect. | 10-27-2011 |
20110266662 | Leadframe enhancing molding compound bondability and package structure thereof - A leadframe enhancing molding compound bondability includes a chip base and a pin holder. The chip bases includes a chip pad and a support, wherein the chip pad includes a side protrusion extending out of the support, and the side protrusion has a lower surface, and the support has a sidewall, and wherein the lower surface and the sidewall interconnect at an intersection line, and the lower surface is formed upwardly with a recess. Further, a pin holder includes a pin stand and a seat, wherein the pin stand has an edge portion extending out of the seat, the edge portion has a lower surface, the seat has a sidewall, and the lower surface and the sidewall interconnect at a crossing line. The lower surface of the pin stand is formed upward with a recess. As such, the bondability between the leadframe and the molding compound can be greatly enhanced. | 11-03-2011 |
20110266663 | LEAD FRAME BASED SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterized in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface. | 11-03-2011 |
20110278707 | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die - A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias. | 11-17-2011 |
20110278708 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a die stage on which a semiconductor element is mounted, a plurality of connection terminals radially arranged around the die stage, and a plurality of wire connection portions which are each provided at a leading end portion on the die stage side of one of the plurality of connection terminals. Moreover, a fixing tape is attached to back surface sides of the wire connection portions and fixes the plurality of wire connection portions all together. Adjacent two of the wire connection portions are staggered in a longitudinal direction of the corresponding connection terminals, and a portion of the connection terminal running along the wire connection portion of the adjacent connection terminal is formed to be narrower and thinner than the wire connection portion. | 11-17-2011 |
20110278709 | STACKED-DIE PACKAGE FOR BATTERY POWER MANAGEMENT - A battery protection package assembly is disclosed. The assembly includes a power control integrated circuit (IC) with pins for a supply voltage input (VCC) and a ground (VSS) on a first side of the power control IC. First and second common-drain metal oxide semiconductor field effect transistors (MOSFETs) are electrically coupled to the power control IC. The power control IC and the first and second common-drain metal oxide semiconductor field effect transistors (MOSFET) are co-packaged on a common die pad. The power control IC is vertically stacked on top of one or more of the first and second common-drain MOSFETs. Leads coupled to a supply voltage input (VCC) and a ground (VSS) of the power control IC are on a first side of the common die pad. | 11-17-2011 |
20110278710 | Direct Contact Leadless Package - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 11-17-2011 |
20110278711 | Leadless Package for High Current Devices - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 11-17-2011 |
20110285001 | LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate. | 11-24-2011 |
20110285002 | LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS - A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer. | 11-24-2011 |
20110291251 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a first lead adjacent and staggered to a second lead, the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion; connecting an integrated circuit device with the first internal connection portion and with the second internal connection portion; forming an encapsulation over the integrated circuit device with the first lead and the second lead exposed; and forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask. | 12-01-2011 |
20110291252 | METHOD AND SYSTEM FOR FORMING A THIN SEMICONDUCTOR DEVICE - A method and system for forming a thin semiconductor device are disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection. | 12-01-2011 |
20110291253 | LEAD FRAME, ELECTRONIC COMPONENT INCLUDING THE LEAD FRAME, AND MANUFACTURING METHOD THEREOF - A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal. | 12-01-2011 |
20110291254 | SEMICONDUCTOR DEVICE PACKAGE FEATURING ENCAPSULATED LEADFRAME WITH PROJECTING BUMPS OR BALLS - Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with at least one die through electrically conducting bumps or balls and electrically conducting ribbons. Embodiments of the present invention may permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint. | 12-01-2011 |
20110298114 | STACKED INTERPOSER LEADFRAMES - A stacked leadframe assembly is disclosed. The stacked leadframe assembly includes a first die having a surface that defines a mounting plane, a first leadframe stacked over and attached to the first die, a second die stacked over and attached to the first leadframe; and a second leadframe stacked over and attached to the second die. The leadframes have die paddles with extended side panels that have attachment surfaces in the mounting plane. | 12-08-2011 |
20110298115 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component is configured to permit the determination of circuit parameters. A high side FET has a gate terminal coupled to an output terminal of a high side gate drive circuit, a drain terminal coupled for receiving an input voltage, and a source terminal coupled to the drain terminal of a low side FET. The gate terminal of the low side FET is coupled to the output terminal of low side drive circuit and the source terminal of the low side FET is coupled for receiving a source of operating potential. The high side gate drive circuit has a bias terminal coupled for receiving a floating potential where the bias terminal is electrically isolated or decoupled from the commonly connected source and drain terminals of the high side FET and the low side FET, respectively. | 12-08-2011 |
20110298116 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - An object of the present invention is to improve the quality control of a semiconductor device. By forming an inscription comprising a culled or pixel skipping pattern of dimples on the upper surface of a die pad in a QFN, it is possible to confirm the inscription by X-ray inspection or the like even after individuation and specify a cavity of a resin molding die. Further, it is possible to specify the position of a device region in a lead frame. As a result, when a defect appears, it is possible to sort a defective QFN by appearance inspection and improve quality control in the assembly of a QFN. | 12-08-2011 |
20110298117 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. Other embodiments may be described and/or claimed. | 12-08-2011 |
20110298118 | SEMICONDUCTOR DEVICE - A semiconductor device, including: a substrate having an upper face on which a first ground pad, a first power supply pad, a first signal pad, and a second signal pad are formed; a first substrate formed on the substrate and having an upper face on which a third signal pad connected to the first signal pad and a first circuit are formed; and a semiconductor element including a second substrate having a reverse face on which a bump electrode connected to the first circuit and a second circuit are formed and an upper face on which a fourth signal pad connected to the second signal pad is formed, with a signal through via connected to the second circuit and the fourth signal pad being buried in the second substrate. | 12-08-2011 |
20110304033 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE STORAGE METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view. | 12-15-2011 |
20110309484 | LEAD FRAME, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE USING THE SAME - A semiconductor package includes a lead frame, a first chip, a second chip, a plurality of bonding wires and a mold compound. The lead frame includes a pad portion at a center of the frame and a plurality of lead portions. The pad portion and the plurality of lead portions collectively define a receiving portion. The first chip is securely received in the receiving portion. The second chip is mechanically attached to the first chip. The plurality of bonding wires electrically connect the second chip to the plurality of lead portions. The mold compound encapsulates the lead frame, the first chip, the second chip and the plurality of bonding wires to form the semiconductor package. | 12-22-2011 |
20110309485 | ETCHED SURFACE MOUNT ISLANDS IN A LEADFRAME PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package. | 12-22-2011 |
20110316132 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure. | 12-29-2011 |
20110316133 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a penetrable layer; partially immersing leads in the penetrable layer; coupling an integrated circuit die to the leads; molding a package body on the integrated circuit die, the leads, and the penetrable layer; and exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads. | 12-29-2011 |
20110316134 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction. | 12-29-2011 |
20110316135 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided. | 12-29-2011 |
20110316136 | SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY - A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion. | 12-29-2011 |
20110316137 | METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view. | 12-29-2011 |
20120001310 | PACKAGE FOR SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE - A package for a semiconductor device according to the present invention includes at least one through hole | 01-05-2012 |
20120001311 | PACKAGE FOR SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE - In a package for a semiconductor device according to the present invention, steps | 01-05-2012 |
20120001312 | PACKAGE FOR SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE - In a package for a semiconductor device according to the present invention, coating resin | 01-05-2012 |
20120001313 | SEMICONDUCTOR PACKAGE WITH AN EMBEDDED PRINTED CIRCUIT BOARD AND STACKED DIE - A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module. | 01-05-2012 |
20120007224 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 01-12-2012 |
20120007225 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 01-12-2012 |
20120012992 | SEMICONDUCTOR DEVICE - A semiconductor device having an improved whisker resistance in an exterior plating film is disclosed. The semiconductor device includes a tab with a semiconductor chip fixed thereto, plural inner leads, plural outer leads formed integrally with the inner leads, a plurality of wires for coupling electrode pads of the semiconductor chip and the inner leads with each other, and a sealing body for sealing the semiconductor chip. The outer leads project from the sealing body and an exterior plating film, which is a lead-free plating film, is formed on a surface of each of the outer leads. In the exterior plating film, the number of grains not larger than 1 μm in diameter and present on an interface side in the thickness direction of the exterior plating film is larger than the number of grains not larger than 1 μm and present on a surface side of the exterior plating film, whereby the difference in linear expansion coefficient between the exterior plating film and the outer lead is made small, thus making it possible to suppress the growth of whisker. | 01-19-2012 |
20120012993 | DIE PACKAGE INCLUDING SUBSTRATE WITH MOLDED DEVICE - A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate. | 01-19-2012 |
20120018863 | MICROELECTRONIC ELEMENTS WITH REAR CONTACTS CONNECTED WITH VIA FIRST OR VIA MIDDLE STRUCTURES - A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via. A rear contact can be electrically connected to the conductive via and exposed at the rear surface for electrical connection with an external circuit element, such as another like microelectronic unit, a microelectronic package, or a circuit panel. | 01-26-2012 |
20120018864 | BONDING STRUCTURE AND METHOD - A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform. | 01-26-2012 |
20120018865 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND EMBEDDED PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having an upper structure, upper protrusions, and a base side facing away from the upper structure and the upper protrusions; forming tie bars in the leadframe with an opening surrounding the upper structure, the tie bars connected to the upper structure and exposed on the base side; connecting an integrated circuit to the upper protrusions; applying an encapsulant over the integrated circuit, over the upper structure, and in the opening with the base side exposed; removing the tie bars exposing a first surface and a second surface of the encapsulant below the first surface, and forming a die paddle from the upper structure and exposed from the second surface; and removing the leadframe from the base side forming island terminals from the upper protrusions exposed from the second surface and isolated from the die paddle. | 01-26-2012 |
20120018866 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole. | 01-26-2012 |
20120018867 | SUBSTRATE FOR SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame. | 01-26-2012 |
20120025360 | SEMICONDUCTOR ENCAPSULATION AND METHOD THEREOF - A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves. | 02-02-2012 |
20120025361 | SEMICONDUCTOR DEVICE, LEAD FRAME ASSEMBLY, AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame. | 02-02-2012 |
20120032315 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion. | 02-09-2012 |
20120032316 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MOLD, AND SEALING DEVICE - A rear surface opposite to one plane of a die pad is formed to be exposed from one plane of a sealing resin. In addition, a concave portion disposed to be parallel with at least a first side of an outermost edge of a central structure and a second side adjacent to the first side, respectively, is formed in the one plane of the sealing resin. Here, a depth of the concave portion is equal to or greater than a height of the outermost edge of the central structure. | 02-09-2012 |
20120032317 | Self-Aligning Structures and Method for Integrated Chips - A lead frame having a die thereon connects a conductive area on the die to a lead frame contact using a conductive clip that includes a structural portion that is received with a recess-like “tub” formed in the lead frame contact. The end of the clip received in the tub is held in place during subsequent handling by a solder paste deposit until the clip and leadframe undergo solder reflow to effect a reliable electrical connection. The effective surface area between one side of the clip and the other side of the clip within the tub is different so that the surface tension of the liquefied solder formed during the solder reflow step will “draw” the clip into a preferred alignment against a “stop” surface. | 02-09-2012 |
20120038034 | Semiconductor Device and Method of Forming Vertical Interconnect in FO-WLCSP Using Leadframe Disposed Between Semiconductor Die - A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe. | 02-16-2012 |
20120038035 | SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package may include a package substrate having a first surface and a boundary that may be defined by edges of the package substrate. The package further includes a first semiconductor chip having a front surface and a back surface. The back surface of a first portion of the first semiconductor chip may be disposed on the first surface of the package substrate with the back surface of a second portion of the first semiconductor chip extending beyond of the defined boundary of the package substrate. The semiconductor package may also include a second semiconductor chip disposed on the back surface of the second portion of the first semiconductor chip that extends beyond the defined boundary of the package substrate. | 02-16-2012 |
20120043651 | LEADFRAME, LEADFRAME TYPE PACKAGE AND LEAD LANE - A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads and a first power lead arranged between the pair of first and second differential signal leads. One of the pairs of differential signal leads has half-double function transmission mode and two of the other pairs of differential signal leads have double function transmission mode. | 02-23-2012 |
20120056311 | LEADFRAME FOR SEMICONDUCTOR DEVICE - A lead frame for a semiconductor device has a die pad with a first major surface for receiving an semiconductor die and a connection bar that encircles the die pad. First lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the first lead fingers lie in a first plane. Second lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the second lead fingers lie in a second plane that is parallel and spaced from the first plane. An isolation frame is disposed between the proximal ends of the first and second lead fingers. The isolation frame separates but supports the proximal ends of the first and second lead fingers. | 03-08-2012 |
20120061812 | Power Semiconductor Chip Package - A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad. | 03-15-2012 |
20120061813 | Package Structure for DC-DC Converter - A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package. | 03-15-2012 |
20120061814 | Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads. | 03-15-2012 |
20120061815 | POWER SEMICONDUCTOR MODULE HAVING SINTERED METAL CONNECTIONS, PREFERABLY SINTERED SILVER CONNECTIONS, AND PRODUCTION METHOD - A power semiconductor module having a substrate ( | 03-15-2012 |
20120068317 | TSOP WITH IMPEDANCE CONTROL - A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant. | 03-22-2012 |
20120068318 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADDLE MOLDING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a hole, a recess, and a pad, the hole over the recess; mounting an integrated circuit to the package paddle; forming a lead having a bottom surface coplanar with a bottom surface of the pad, the lead isolated from the package paddle; attaching connectors directly on the integrated circuit, the lead, and the package paddle; and forming an encapsulation covering the integrated circuit and within the hole and the recess. | 03-22-2012 |
20120068319 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate. | 03-22-2012 |
20120068320 | Integrated Power Converter Package With Die Stacking - An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry. | 03-22-2012 |
20120068321 | SEMICONDUCTOR DEVICE - The invention enhances resistance to a surge in a semiconductor device having a semiconductor die mounted on a lead frame. An N type embedded layer, an epitaxial layer and a P type semiconductor layer are disposed on the front surface of a P type semiconductor substrate forming an IC die. A metal thin film is disposed on the back surface of the semiconductor substrate, and a conductive paste containing silver particles and so on is disposed between the metal thin film and a metal island. When a surge is applied to a pad electrode disposed on the front surface of the semiconductor layer, the surge current flowing from the semiconductor layer into the semiconductor substrate runs toward the metal island through the metal thin film. | 03-22-2012 |
20120068322 | PACKAGE SUBSTRATE, MODULE AND ELECTRIC/ELECTRONIC DEVICES USING THE SAME - A package substrate includes: a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, which is formed on the first principal surface; a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, which is formed on the second principal surface; an intermediate conductive layer formed between the first conductive layer and the second conductive layer; interlayer insulating layers formed between the first conductive layer and the intermediate conductive layer as well as between the second conductive layer and the intermediate conductive layer; and plural interlayer connection conductors stacked for connecting between the first conductive layer and the second conductive layer so as to pierce through the interlayer insulating layers. | 03-22-2012 |
20120068323 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE - A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface. | 03-22-2012 |
20120074546 | Multi-chip Semiconductor Packages and Assembly Thereof - Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die. | 03-29-2012 |
20120074547 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole. | 03-29-2012 |
20120074548 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a lead overhang protruding from a lead non-horizontal side and a lead ridge protruding from the lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming an encapsulation over the integrated circuit, the lead, and the package paddle, the encapsulation under the lead overhang. | 03-29-2012 |
20120074549 | SEMICONDUCTOR DEVICE WITH EXPOSED PAD - A semiconductor device has a die attached to a die pad and electrically connected to lead fingers. The die, a top surface of the die pad, and a first portion of the lead fingers are covered with a mold compound. A second portion of the lead fingers project from the mold compound and allow for external electrical connection to the die. The mold compound around the die and lead fingers is extended such that a cavity is formed below the die pad. The die pad is exposed via the cavity. A heat sink may be inserted into the cavity and attached to the bottom surface of the die pad. | 03-29-2012 |
20120074550 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a die stage; an inner lead provided near the die stage; and a bus bar provided between the die stage and the inner lead and supported by a hanging lead, wherein the hanging lead is inclined with respect to the inner lead, and a wire connection face of the bus bar is displaced with respect to a wire connection face of the inner lead in a direction of a frame thickness. | 03-29-2012 |
20120074551 | SEMICONDUCTOR DEVICE - An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames are provided in both sides of the lead frame. A portion of the lead frame is encapsulated with the encapsulating resin to function as an inner lead. The encapsulating resin is composed of a resin composition that contains substantially no halogen. Further, an exposed portion of the Al pad provided in the semiconductor chip is electrically connected to the inner lead via the AuPd wire. | 03-29-2012 |
20120074552 | CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a hybrid integrated circuit device, a circuit board on which an island portion of a lead is fixedly attached and a control board on which a control element and the like are mounted are disposed in an overlapping manner. The circuit board and the control board are integrally encapsulated with an encapsulating resin. A transistor disposed on an upper surface of the circuit board and a control element mounted on an upper surface of the control board are also covered by the encapsulating resin. Thus, a module in which an inverter circuit and a control circuit are integrally encapsulated with resin is provided. | 03-29-2012 |
20120080781 | DELAMINATION RESISTANT DEVICE PACKAGE HAVING RAISED BOND SURFACE AND MOLD LOCKING APERTURE - A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity. | 04-05-2012 |
20120091569 | LEADFRAME PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The package structure includes a metal sheet having a first central block, a plurality of first metal blocks, a second central block and a plurality of second metal blocks, a first finish layer and a second finish layer, at least a chip disposed on the metal sheet and a package body encapsulating the chip. The package structure may further include at least an area block for wire routing. | 04-19-2012 |
20120091570 | CHIP PACKAGE STRUCTURE AND CHIP PACKAGING METHOD - A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first end portions of the leads with a plurality of bonding wires through the opening. | 04-19-2012 |
20120091571 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connection between the second pad and outside, and the semiconductor chip is, on the one surface of the lead integrated island, disposed at a position one-sided to the first pad connecting terminal side, and the first pad and the one surface of the lead integrated island are connected by a wire. | 04-19-2012 |
20120091572 | SEMICONDUCTOR PACKAGE AND IMPLEMENTATION STRUCTURE OF SEMICONDUCTOR PACKAGE - The semiconductor package includes a package wiring board having an element housing recessed portion on its top surface to house a semiconductor element; multiple side electrodes which are arranged on the outer side surface of the package wiring board and soldered to multiple motherboard electrodes arranged on a motherboard; a semiconductor element fixed onto the bottom surface of the element housing recessed portion; and an element electrode arranged on the bottom of the element housing recessed portion and electrically connected to the semiconductor element and the side electrodes. The package wiring board has a multilayered structure in which woven fabric and a resin adhesive layer are alternately laminated, and the resin adhesive layer is formed of a resin adhesive that contains inorganic filler particles. | 04-19-2012 |
20120098112 | LEAD FRAME MANUFACTURED FROM LOW-PRICED MATERIAL AND NOT REQUIRING STRICT PROCESS CONTROL, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE LEAD FRAME AND THE SEMICONDUCTOR PACKAGE - Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns. | 04-26-2012 |
20120098113 | DEVICE WITH SEMICONDUCTOR DIE ATTACHED TO A LEADFRAME - Methods and resulting devices are disclosed related to attaching a die to a leadframe. One such method includes initially bonding a carrier pad which is pre-coated with a thermosetting first adhesive to the leadframe. The carrier pad can be electrically non-conductive. The first adhesive can be raised to its thermosetting cure temperature by heating the leadframe to a temperature just above the thermosetting cure temperature of the first adhesive. A thermosetting second adhesive which is liquid at room temperature can be applied to a second major surface of the carrier pad, and the die can be placed on the second adhesive and aligned with the leadframe. The second adhesive can be raised to its thermosetting cure temperature to bond the die to the carrier pad, and in turn form a bonded assembly. | 04-26-2012 |
20120104583 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING SAME - A semiconductor device includes a lead frame that has a die interconnect portion and at least first and second die pads. The die interconnect portion is isolated from the die pads. The device also includes a first die and a second die attached to the first and second die pads and electrically connected to each other by way of the die interconnect portion. The first die is encapsulated in a first medium and the second die is encapsulated in a second medium, the first medium being different from the second medium. | 05-03-2012 |
20120104584 | SEMICONDUCTOR DEVICE PACKAGES WITH PROTECTIVE LAYER AND RELATED METHODS - A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads. | 05-03-2012 |
20120104585 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming signal contacts; forming a power bar having a power bar terminal, the power bar terminal formed in a staggered position relative to the signal contacts; depositing a terminal pad on the power bar terminal; depositing a contact pad on one of the signal contacts; coupling an integrated circuit die to the power bar terminal and the signal contacts; and forming a package body on the integrated circuit die. | 05-03-2012 |
20120104586 | Direct Contact Flip Chip Package with Power Transistors - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 05-03-2012 |
20120104587 | Direct Contact Semiconductor Package with Power Transistor - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 05-03-2012 |
20120104588 | METHOD FOR MANUFACTURING LEADFRAME, PACKAGING METHOD FOR USING THE LEADFRAME AND SEMICONDUCTOR PACKAGE PRODUCT - A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads. | 05-03-2012 |
20120112333 | SEMICONDUCTOR DEVICE WITH NESTED ROWS OF CONTACTS - A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively. | 05-10-2012 |
20120119342 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound. | 05-17-2012 |
20120119343 | STACKED LEADFRAME IMPLEMENTATION FOR DC/DC CONVERTOR POWER MODULE INCORPORATING A STACKED CONTROLLER AND STACKED LEADFRAME CONSTRUCTION METHODOLOGY - Methods and systems are described for enabling the efficient fabrication of small form factor power converter packages and other devices using stacked leadframes. | 05-17-2012 |
20120119344 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads. | 05-17-2012 |
20120133036 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION SUPPORTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a connection structure having a component pad, an outer pad, and an inner pad, the inner pad between the component pad and the outer pad; forming a support structure between the inner pad and the outer pad; mounting an integrated circuit device over the component pad; attaching an interconnect to the integrated circuit device and the outer pad, the interconnect above the inner pad and supported by the support structure; and applying an encapsulation over the connection structure, the interconnect, and the integrated circuit device. | 05-31-2012 |
20120133037 | CLIP INTERCONNECT WITH ENCAPSULATION MATERIAL LOCKING FEATURE - A clip interconnect comprises a columnar part, a bridge part, and a locking feature. The bridge part has a plurality of sides. The columnar part and the bridge part are configured to form an angle at an interface between the columnar part and the bridge part. The locking feature is located in at least one of the plurality of sides of the bridge part. The locking feature comprises an alternating pattern of teeth and valleys. | 05-31-2012 |
20120133038 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE - An integrated circuit package system includes a trace frame includes: an encapsulant; a first series of bonding pads along a length of the encapsulant; a second series of the bonding pads along a width of the encapsulant; conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and a first integrated circuit die on the encapsulant and on the conductive traces that extend beyond the first integrated circuit die. | 05-31-2012 |
20120146201 | DIE ARRANGEMENT AND METHOD OF FORMING A DIE ARRANGEMENT - A die arrangement includes a carrier having a first side and a second side opposite the first side, the carrier including an opening leading from the first side of the carrier to the second side of the carrier; a first die disposed over the first side of the carrier and electrically contacting the carrier; a second die disposed over the second side of the carrier and electrically contacting the carrier; and an electrical contact structure leading through the opening in the carrier and electrically contacting the second die. | 06-14-2012 |
20120146202 | Top exposed Package and Assembly Method - A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls. | 06-14-2012 |
20120146203 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base structure having a die paddle, an outer lead, and an inner lead between the die paddle and the outer lead, with a pre-plated finish on a base structure system side of the base structure; mounting an integrated circuit device to a side of the die paddle opposite the paddle system side; attaching an interconnect to the integrated circuit device and a side of the inner lead opposite the inner lead system side; applying an encapsulation around the integrated circuit device, the interconnect, and the base structure with the pre-plated finish exposed from the encapsulation; and forming an inward channel in the encapsulation to electrically isolate the inner lead. | 06-14-2012 |
20120146204 | SEMICONDUCTOR DEVICES AND ELECTRICAL PARTS MANUFACTURING USING METAL COATED WIRES - The device of this invention includes a semiconductor die attached to a bare copper lead frame and electrically coupled to a lead by a metal wire coated with a metallic material. The device would function similarly to devices where the lead frames were coated with other metallic materials, but at lower costs because instead of plating the lead frame the wire is plated. The wire can be either gold or aluminum. When the wire is gold, the coating may be silver or other suitable metallic materials. When the wire is aluminum, the coating may be nickel, palladium, or other suitable metals. | 06-14-2012 |
20120153449 | NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-leaded package structure is provided. An upper surface and a lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part and electrically connected to the first protruding parts with a plurality of bonding wires. An encapsulant is formed on the upper surface. A back etching process is performed on the lower surface to partially remove the metal base plate until the encapsulant is exposed and a lead group including at least a die pad and a plurality of leads is defined. | 06-21-2012 |
20120161304 | Dual-leadframe Multi-chip Package and Method of Manufacture - A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. | 06-28-2012 |
20120168920 | LEADLESS SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE - A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of bond pads, none of which extend as far as a lateral face of the body. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and bond pads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and bond pads, back surfaces of which remain exposed at a back face of the body. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of bond pads on one side of the substrate and a plurality of cavities on the opposite face. | 07-05-2012 |
20120168921 | LEADLESS SEMICONDUCTOR PACKAGE WITH ROUTABLE LEADS, AND METHOD OF MANUFACTURE - A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of high-aspect-ratio leads, each coupled at a first end to a contact pad of the package, and at a second end to a semiconductor die mounted to the die paddle. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and leads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and leads, and to thin a portion of each of the leads. Back surfaces of the leads remain exposed at a back face of the body. The thinned portions of the leads are covered with a dielectric. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of leads on one side of the substrate and a plurality of cavities on the opposite face. | 07-05-2012 |
20120168922 | High Power Semiconductor Package with Conductive Clip - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168923 | High Power Semiconductor Package with Conductive Clip on Multiple Transistors - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168924 | High Power Semiconductor Package with Multiple Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168925 | High Power Semiconductor Package with Conductive Clips and Flip Chip Driver IC - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168926 | High Power Semiconductor Package with Conductive Clip and Flip Chip Driver IC with Integrated Control Transistor - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages. Moreover, by integrating only the control transistor rather than both the control and sync transistor within the flip chip driver IC, the sync transistor may remain separate, simplifying manufacture and providing greater total surface area for thermal dissipation. | 07-05-2012 |
20120168927 | SEMICONDUCTOR DEVICE - A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass. | 07-05-2012 |
20120168928 | CHIP ASSEMBLY WITH FREQUENCY EXTENDING DEVICE - A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands. | 07-05-2012 |
20120175756 | SEMICONDUCTOR PACKAGES HAVING LEAD FRAMES - Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip. | 07-12-2012 |
20120175757 | METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, THE SEMICONDUCTOR APPARATUS, AND IGNITOR USING THE SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus according to aspects of the invention can include the steps of coating solder on an predetermined area in the upper surface of a lead frame, mounting a chip on solder and melting solder with a hot plate for bonding the chip to the lead frame. The method can also include wiring with bonding wires, turning lead frame upside down, placing lead frame turned upside down on heating cradle, coating solder, the melting point of which is lower than the solder melting point and mounting electronic part on solder; and melting solder with heating cradle for bonding electronic part to lead frame. The bonding with solder can be conducted at a high ambient temperature. Aspects of the semiconductor apparatus can facilitate mounting semiconductor devices and electronic parts on both surfaces of a lead frame divided to form wiring circuits without through complicated manufacturing steps. | 07-12-2012 |
20120175758 | LEAD FRAME AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver. | 07-12-2012 |
20120175759 | WIRING DEVICE FOR SEMICONDUCTOR DEVICE, COMPOSITE WIRING DEVICE FOR SEMICONDUCTOR DEVICE, AND RESIN-SEALED SEMICONDUCTOR DEVICE - A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal. | 07-12-2012 |
20120175760 | LEADFRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a die pad, the die pad including a first surface and a second surface, a first chip arranged on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged on the first surface, a plurality of first recesses formed on the first surface, a plurality of second recesses formed on the first surface, the plurality of second recesses being different from the first plurality of recesses in at least one of size and geometry, a wire, a resin, and a lead, one end of the lead being connected to another end of the wire and a part the lead being encapsulated by the resin. The plurality of first recesses includes a third recess and a fourth recess, and the first chip is arranged in a first area. | 07-12-2012 |
20120175761 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device consisting of a lead frame or a circuit board, at least one semiconductor element which is stacked on or mounted in parallel on the lead frame or on the circuit board, a copper wire which electrically connects the lead frame or the circuit board to the semiconductor element, and an encapsulating material which encapsulates the semiconductor element and the copper wire, wherein the wire diameter of the copper wire is equal to or more than 18 μm and equal to or less than 23 μm,
| 07-12-2012 |
20120181678 | LEADLESS CHIP CARRIER HAVING IMPROVED MOUNTABILITY - Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board. | 07-19-2012 |
20120181679 | SEMICONDUCTOR MODULE - A semiconductor module comprises: a metal block; a semiconductor device installed via a solder layer in a semiconductor device installation area on a surface of the metal block; and a molded portion formed by molding a resin on the metal block and the semiconductor device; wherein the surface of the metal block includes a plating area and a roughened area, and the semiconductor device installation area is provided in the plating area. | 07-19-2012 |
20120181680 | IC PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An IC package is provided. The IC package comprises a leadframe comprising a metal strip( | 07-19-2012 |
20120187552 | Molded Stiffener for Thin Substrates - A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package. | 07-26-2012 |
20120193774 | CONTACTLESS COMMUNICATION MEDIUM - Provided is a contactless communication medium which can prevent invasion of static electricity and has an outer surface which can satisfy requirements on the flatness thereof. A contactless communication medium is provided, in which a sealing member including an insulating layer and a conductive layer provided in a stacked manner and having a shape covering an IC module is located such that the insulating layer is on the IC module side. Owing to this, static electricity coming from outside is diffused by the conductive layer and blocked by the insulating layer. Thus, adverse influence of the static electricity on the IC module is prevented with certainty. The contactless communication medium can also satisfy the requirements on the flatness of an outer surface thereof. | 08-02-2012 |
20120199961 | SEMICONDUCTOR PACKAGES HAVING LEAD FRAMES - Semiconductor packages include a semiconductor chip, a lead frame on which the semiconductor chip is mounted, and a mold layer to encapsulate the semiconductor chip and the lead frame. The lead frame is electrically connected to the semiconductor chip. The lead frame includes a first lead frame and a second lead frame. The first lead frame is electrically connected to the semiconductor chip by a plurality of bonding wires. The first lead frame has outer leads that protrude from the mold layer. The second lead frame is attached to the first lead frame by an insulating adhesion layer. The second lead frame provides a mounting surface on which the semiconductor chip is mounted. The first and second lead frames support the semiconductor chip. | 08-09-2012 |
20120199962 | Semiconductor Package with Cantilever Leads - A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe. | 08-09-2012 |
20120205789 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device, a first semiconductor element having a first terminal is embedded in a resin layer such that terminals thereof are exposed through a first surface of the resin layer. A wiring layer is formed in the first surface of the resin layer. A second semiconductor element includes second and third terminals. Regardless of the relationship between the plane size of the first semiconductor element and that of the second semiconductor element, the second terminal of the second semiconductor element is connected to the first terminal of the first semiconductor element exposed through the first surface of the resin layer, and the third terminal of the second semiconductor element is connected to the wiring layer formed in the resin layer. | 08-16-2012 |
20120205790 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a stacked structure including a lead frame having a front surface and a back surface, the front surface being made of Cu, a semiconductor chip having a front surface and a back surface, including a Cu layer that forms the back surface, disposed so that the back surface is opposed to the front surface of the lead frame, and a bonding layer interposed between the lead frame and the semiconductor chip, in which the bonding layer includes a Bi-based material layer and Cu alloy layers not containing Pb that sandwich the Bi-based material layer from both sides in an opposing direction of the lead frame and the semiconductor chip with respect to the Bi-based material layer. | 08-16-2012 |
20120223423 | Lead Frame Strip with Rails Having Bow Reducing Ribs - A lead frame strip includes an array of sites connected to two side rails which traverse the lead frame strip on two opposite sides. Each site includes a die pad for affixing a semiconductor die and leads for enabling electrical communication between the semiconductor die and a workpiece. Each site is further connected to the two side rails by a sub-rail, which extends between the two side rails. The sub-rail includes a flat portion and a raised or indented rib protruding from the flat portion. The rib has a long dimension parallel to the sub-rail. | 09-06-2012 |
20120228754 | CHIP-LAST EMBEDDED INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME - The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options. | 09-13-2012 |
20120235287 | HIGH BRIGHTNESS AND HIGH CONTRAST PLASTIC LEADED CHIP CARRIER LED - A Plastic Leaded Chip Carrier (PLCC) package is disclosed. The PLCC package provides a light source that is both high contrast and high brightness. Specifically, the PLCC package includes a reflector cup whose surface area is partially inclusive of a lead frame and partially inclusive of a plastic housing that surrounds the lead frame. | 09-20-2012 |
20120235288 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device in accordance with an embodiment comprises a semiconductor chip; a die pad having a chip mount surface for mounting the semiconductor chip; first leads electrically connected to the semiconductor chip; a thermosetting resin part for securing end parts of the first leads to the die pad; and a thermoplastic resin part for sealing the semiconductor chip, the die pad, and the thermosetting resin part. | 09-20-2012 |
20120235289 | POWER DEVICE WITH BOTTOM SOURCE ELECTRODE AND PREPARATION METHOD - A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process. | 09-20-2012 |
20120241931 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; embedding a circuit end of an internal interconnect in the bonding interconnect; and connecting a lead end of the internal interconnect to the lead. | 09-27-2012 |
20120241932 | SEMICONDUCTOR DEVICE - A semiconductor device according to the embodiment is provided with an inner lead. The inner lead includes a first surface and a second surface opposite thereto. A semiconductor chip is mounted on the first surface. A first resin portion seals the semiconductor chip on the first surface. A second resin portion is provided on the second surface. An outer lead is connected to the inner lead, and configured to project outside from the first and second resin portions. A width of the second resin portion in a first direction where the outer lead projects is smaller than that of the first resin portion in the first direction. | 09-27-2012 |
20120241933 | SEMICONDUCTOR MEMORY CARD - In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer. | 09-27-2012 |
20120241934 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor apparatus includes a semiconductor device, a bed, a plurality of leads, a suspension pin, and a mold resin. The bed includes an alignment pin provided in a peripheral portion of the bed. The semiconductor device is mounted on the bed via a first solder. The plurality of leads are electrically connected to a plurality of electrodes of the semiconductor device. The suspension pin is made of the same conductive material as the lead. The suspension pin has an alignment hole in a tip of the suspension pin. The suspension pin engages the peripheral portion of the bed by the alignment pin being inserted into the alignment hole. The suspension pin is fixed to the peripheral portion of the bed by a second solder. The mold resin contains the semiconductor device, the bed, one end of the leads, and the suspension pin. | 09-27-2012 |
20120248590 | SEMICONDUCTOR PACKAGE AND LEAD FRAME THEREFOR - A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers. | 10-04-2012 |
20120248591 | LEAD FRAME AND SEMICONDUCTOR DEVICE - A lead frame for a resin-seal type semiconductor device, which includes a semiconductor element having an electrode, a bonding wire connected to the electrode of the semiconductor element, and a sealing resin covering and sealing the semiconductor element and the bonding wire. The lead frame includes a substrate frame, a four-layer plating, and a three-layer plating. The substrate frame include leads, a connection region, which is sealed by the sealing resin and connected to the bonding wire, and an exposed region, which is not sealed by the sealing resin. A four-layer plating is applied to a portion of the substrate frame that is to be connected to the bonding wire and sealed by the sealing resin. A three-layer plating is applied to an exposed region of the substrate frame that is exposed from the sealing resin. | 10-04-2012 |
20120248592 | LEAD COMPONENT AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE - To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer. | 10-04-2012 |
20120248593 | PACKAGE STRUCTURE FOR DC-DC CONVERTER - A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package. | 10-04-2012 |
20120256306 | EXPOSED DIE PACKAGE FOR DIRECT SURFACE MOUNTING - A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another. | 10-11-2012 |
20120261806 | LEAD FRAME STRIP FOR REDUCED MOLD STICKING DURING DEGATING - A lead frame strip includes an array of sites arranged in at least one row connected to two exterior side rails which traverse the lead frame strip on two opposite sides. Each of the sites is further connected to the two exterior side rails by subrails which extend between the two exterior side rails. Interior side rails extend between the subrails having a length dimension oriented along a first direction. The interior side rails include at least one punch degating aperture having an aperture length oriented along the first direction, wherein a total of the aperture length along the interior side rails is greater than or equal to the die pad length. | 10-18-2012 |
20120261807 | EPOXY RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION, CURED PRODUCT THEREOF, AND SEMICONDUCTOR DEVICE - An epoxy resin composition for semiconductor encapsulation of the present invention contains an epoxy resin (A) and a curing agent (B) and is used to encapsulate a copper wire ( | 10-18-2012 |
20120261808 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed. | 10-18-2012 |
20120267771 | STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR - A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. | 10-25-2012 |
20120267772 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device having suspension leads with less distortion. In QFN having a plurality of external terminal portions at the periphery of the bottom surface of a sealing body, a plurality of leads is linked to a plurality of long suspension leads of the QFN at an intermediate portion thereof or at between the intermediate portion and a position near the die pad. These long suspension leads are each supported by these leads, making it possible to suppress distortion of each of the suspension leads in a wire bonding step or molding step in the fabrication of the QFN. | 10-25-2012 |
20120273931 | Integrated circuit chip package and manufacturing method thereof - The present invention discloses an integrated circuit (IC) chip package and a manufacturing method thereof. The IC chip package includes: a lead frame, including a lead frame array having plural conductive cells, wherein some of the conductive cells are respectively electrically connected with corresponding first extended wires; at least one redistribution layer, wherein each redistribution layer includes plural second extended wires, which are respectively electrically connected to the first extended wires or the second extended wires of another redistribution layer; and a solder array, including plural solder balls, which are electrically connected to the lead frame array. | 11-01-2012 |
20120273932 | POWER SUPPLY MODULE AND PACKAGING AND INTEGRATING METHOD THEREOF - A power supply module and a packaging and integrating method thereof are provided. The power supply module includes a lead frame, a passive element, an integrated circuit (IC), and a power switch Metallic Oxide Semiconductor Field Effect Transistor (MOSFET). The passive element is soldered onto the lead frame by using the surface mount technology. The IC is a flip chip and is mounted and soldered onto the lead frame. | 11-01-2012 |
20120280377 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge. | 11-08-2012 |
20120280378 | COL-BASED SEMICONDUCTOR PACKAGE INCLUDING ELECTRICAL CONNECTIONS THROUGH A SINGLE LAYER LEADFRAME - A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted. | 11-08-2012 |
20120280379 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads. | 11-08-2012 |
20120286409 | UTILIZING A JUMPER CHIP IN PACKAGES WITH LONG BONDING WIRES - A combination for electrically connecting an integrated circuit ( | 11-15-2012 |
20120286410 | SEMICONDUCTOR DEVICE PACKAGING METHOD AND SEMICONDUCTOR DEVICE PACKAGE - Disclosed is a discrete semiconductor device package ( | 11-15-2012 |
20120286411 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR MODULE USING THE SAME - According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected. | 11-15-2012 |
20120286412 | SEMICONDUCTOR DEVEICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device | 11-15-2012 |
20120292753 | MULTI-TRANSISTOR EXPOSED CONDUCTIVE CLIP FOR HIGH POWER SEMICONDUCTOR PACKAGES - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 11-22-2012 |
20120292754 | Common Drain Exposed Conductive Clip for High Power Semiconductor Packages - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors having a common drain coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors for various power applications. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 11-22-2012 |
20120292755 | FLANK WETTABLE SEMICONDUCTOR DEVICE - A flank wettable semiconductor device is assembled from a lead frame or substrate panel by at least partially undercutting the lead frame or substrate panel with a first cutting tool to expose a flank of the lead frame and applying a coating of tin or tin alloy to the exposed flank prior to singulating the lead frame or substrate panel into individual semiconductor devices. The method includes electrically interconnecting lead frame flanks associated with adjacent semiconductor devices before applying the coating of tin or tin alloy. The lead frame flanks may be electrically interconnected during wire bonding. | 11-22-2012 |
20120299172 | LEAD FRAME FOR SEMICONDUCTOR DEVICE - Provided is a lead frame for a semiconductor device, which includes a base layer made of copper, a strike plating layer or a self assembly monolayer (SAM), thereby preventing oxidation of a base layer while simplifying the manufacturing process, reducing the manufacturing costs and reducing a failure ratio. In one embodiment, in the lead frame for a semiconductor device including a die pad and a plurality of leads positioned adjacent to each other around the die pad, the lead frame includes a base layer made of copper; and a first strike plating layer formed on the one or more portions of the surface of the base layer. | 11-29-2012 |
20120306065 | SEMICONDUCTOR PACKAGE WITH PRE-SOLDERED GROOVES IN LEADS - A packaged semiconductor device includes a die pad on which a semiconductor die that includes a plurality of bond pads is attached. A plurality of lead terminals surround the die pad, wherein the plurality of bond pads are connected to the plurality of lead terminals, and the plurality of lead terminals include an outer toe-wall and a groove along their length that extends to the toe-wall to provide a lead terminal orifice. An encapsulating material that defines an outer dimension for the packaged semiconductor device is absent from the grooves. Solder fills the grooves. A bottomside of the solder in the grooves provides an exposed solder surface available for bonding. | 12-06-2012 |
20120306066 | ELECTRONIC DEVICE INCLUDING A PACKAGING SUBSTRATE HAVING A TRENCH - An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate. | 12-06-2012 |
20120313230 | SOLDER ALLOYS AND ARRANGEMENTS - A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc. | 12-13-2012 |
20120313231 | METHOD AND APPARATUS FOR DICING DIE ATTACH FILM ON A SEMICONDUCTOR WAFER - In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method. | 12-13-2012 |
20120313232 | Power Package Including Multiple Semiconductor Devices - In one embodiment, a method includes attaching a film to cover a first portion of a first semiconductor die. The first semiconductor die is attached, using the tape, to a lead frame using a first bonding method. The first bonding method places the film between the lead frame and the semiconductor die. A second semiconductor die is attached to the lead frame using a second bonding method. The second bonding method bonds the lead frame and the semiconductor die. The first semiconductor device and the second semiconductor device are encapsulated into a semiconductor package. | 12-13-2012 |
20120313233 | Semiconductor Package, Stacking Semiconductor Package, And Method Of Fabricating The Same - A stackable semiconductor package, a stacked semiconductor package that uses the stackable semiconductor packages, and a method of fabricating the same. The semiconductor package includes a die paddle unit having a first surface and a second surface opposite to the first surface, a semiconductor die attached to the first surface of the die paddle unit, a plurality of leads each including a first external terminal unit, a second external terminal unit, and a connection lead unit that connects the first external terminal unit to the second external terminal unit, a bonding wire that connects the semiconductor die to the first external terminal unit, and a sealing member formed to expose the first external terminal unit and the second external terminal unit and to surround the semiconductor die and the bonding wire. | 12-13-2012 |
20120319258 | STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF - A method of forming a conductive pattern on a metallic frame for manufacturing a stack frame for electrical connections is disclosed. In one embodiment, a recess is formed in the metallic frame and a conductive element is bonded in the recess to make a stack frame for electrical connections. In another embodiment, the process can be performed on both top surface and bottom surface of metallic frame to make another stack frame for electrical connections. In yet another embodiment, a package structure and a manufacturing method of forming a conductive pattern on a lead frame for electrical connections are disclosed. | 12-20-2012 |
20120319259 | POWER MODULE PACKAGE AND METHOD FOR FABRICATING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: first and second lead frames arranged to face each other, both or either of the first and second frames being made of aluminum; anodized layers formed on portions of the lead frame(s) made of aluminum in the first and second lead frames; and semiconductor devices mounted on first surfaces of the first and second lead frames. | 12-20-2012 |
20120319260 | POWER MODULE PACKAGE AND SYSTEM MODULE HAVING THE SAME - Disclosed herein is a power module package, including: a first substrate having first semiconductor chips mounted thereon; and a second substrate having second semiconductor chips mounted thereon, the second substrate being coupled with the first substrate such that a side surface in a thickness direction thereof is disposed on an upper surface of the first substrate. | 12-20-2012 |
20120326285 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 μm to 8.00 μm deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle. | 12-27-2012 |
20120326286 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WAFER LEVEL RECONFIGURED MULTICHIP PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper portion of a peripheral lead on the leadframe first side; mounting a first integrated circuit over the partially removed region with a first adhesive; forming a first molding layer directly on the first integrated circuit and the peripheral lead; removing a portion of a leadframe second side exposing the first adhesive; mounting a second integrated circuit on the first adhesive of the first integrated circuit; forming a first interconnection layer directly on the first integrated circuit with the first integrated circuit and the peripheral lead electrically connected; and forming a second interconnection layer directly on the second integrated circuit with the second integrated circuit and the peripheral lead electrically connected. | 12-27-2012 |
20120326287 | DC/DC CONVERTOR POWER MODULE PACKAGE INCORPORATING A STACKED CONTROLLER AND CONSTRUCTION METHODOLOGY - Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices. | 12-27-2012 |
20120326288 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICE - A method of assembling a semiconductor device includes providing a conductive lead frame panel and selectively half-etching a top side of the lead frame panel to provide a pin pads. A flip chip die is attached and electrically connected to the pin pads and then the lead frame panel and die are encapsulated with molding compound. A second selective half etching step is performed on a backside of the lead frame panel to form a plurality of separate input/output pins. The side walls of each input/output pin include arcuate surfaces in cross-section. | 12-27-2012 |
20120326289 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: leads ( | 12-27-2012 |
20130001760 | PACKAGE SUBSTRATE HAVING DIE PAD WITH OUTER RAISED PORTION AND INTERIOR RECESSED PORTION - An electronic assembly includes a substrate including a die pad, where the die pad includes and an outer raised flat portion and a recessed portion that includes an inner recessed portion. A semiconductor die is directly on the outer raised flat portion and affixed to the die pad by a die attach material that is in the inner recessed portion. The die attach material is not on a top surface of the outer raised flat portion. | 01-03-2013 |
20130001761 | LEAD CARRIER WITH THERMALLY FUSED PACKAGE COMPONENTS - A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a fusible fixing material on a lower portion. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be heated above a melting temperature of the fusible fixing material and peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. | 01-03-2013 |
20130001762 | Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die - A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure. | 01-03-2013 |
20130009295 | Semiconductor Device Including a Contact Clip Having Protrusions and Manufacturing Thereof - A semiconductor device includes a leadframe with a die pad and a first lead, a semiconductor chip with a first electrode, and a contact clip with a first contact area and a second contact area. The semiconductor chip is placed over the die pad. The first contact area is placed over the first lead and the second contact area is placed over the first electrode of the semiconductor chip. A plurality of protrusions extends from each of the first and second contact areas and each of the protrusions has a height of at least 5 μm. | 01-10-2013 |
20130009296 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body. | 01-10-2013 |
20130009297 | SEMICONDUCTOR DEVICE PACKAGE HAVING CONFIGURABLE LEAD FRAME FINGERS - Embodiments of the present invention relate to the use of configurable lead frame fingers in a semiconductor device package. More specifically, the lead frame of a device package can include a plurality of fingers used to support and provide electrical contact to the die. The die can include a plurality of contacts that comprise a series of parallel columns located a certain distance from one another, and the fingers of the lead frame can be configured to align with the contacts. The lead frame can have multiple terminals, each with one or more fingers and pins. As such, each lead frame configuration may be utilized with different configurations of die. | 01-10-2013 |
20130009298 | SEMICONDUCTOR MODULE - A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns. | 01-10-2013 |
20130009299 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion. | 01-10-2013 |
20130009300 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A dug portion ( | 01-10-2013 |
20130015566 | APPARATUS AND METHODS FOR QUAD FLAT NO LEAD PACKAGINGAANM GONG; ZHIWEIAACI ChandlerAAST AZAACO USAAGP GONG; ZHIWEI Chandler AZ USAANM Xu; JianwenAACI San DiegoAAST CAAACO USAAGP Xu; Jianwen San Diego CA USAANM Gao; WeiAACO USAAGP Gao; Wei USAANM Hayes; Scott M.AACI ChandlerAAST AZAACO USAAGP Hayes; Scott M. Chandler AZ US - A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements. | 01-17-2013 |
20130015567 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SAMEAANM Minamio; MasanoriAACI OsakaAACO JPAAGP Minamio; Masanori Osaka JPAANM Tanaka; ZyunyaAACI OsakaAACO JPAAGP Tanaka; Zyunya Osaka JPAANM Ijima; Shin-ichiAACI OsakaAACO JPAAGP Ijima; Shin-ichi Osaka JP - A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package. | 01-17-2013 |
20130020686 | PACKAGE STRUCTURE AND PACKAGE PROCESS - A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided. | 01-24-2013 |
20130020687 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames. | 01-24-2013 |
20130020688 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure including a leadframe, a chip, bonding wires and an encapsulant is provided. The leadframe includes a die pad, leads and an insulating layer. The die pad includes a chip mounting portion and a periphery portion. At the periphery portion, the die pad has a second upper surface lying between a first upper surface and a lower surface of the die pad. Each lead includes a suspending portion and a terminal portion. The suspending portion connects to the terminal portion and extends from the terminal portion towards the die pad. The insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad. The chip is disposed on the chip mounting portion. The bonding wires electrically connect the chip to the suspending portions. The encapsulant covers the chip, the bonding wires, the insulating layer, and the leadframe. | 01-24-2013 |
20130020689 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING SAME - A Quad Flat Pack (QFP) device includes a semiconductor die attached to a flag of a lead frame. Bonding pads of the die are electrically connected to inner and outer rows of leads of the lead frame with bond wires. The die, die flag, bond wires and portions of the inner and outer leads are covered with a mold compound, which defines a package body. The outer leads are similar to the gull-wing leads of a conventional QFP device while the inner leads form contact points at a bottom surface of the package body. A cut is performed on an inner side of the inner leads to separate the inner leads from the die pad. | 01-24-2013 |
20130020690 | STACKED DIE SEMICONDUCTOR PACKAGE - A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality. | 01-24-2013 |
20130020691 | Method of Manufacturing a Semiconductor Device - A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented. | 01-24-2013 |
20130020692 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed. | 01-24-2013 |
20130032933 | EPOXY RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR DEVICE, LEAD FRAME FOR OPTICAL SEMICONDUCTOR DEVICE AND SUBSTRATE FOR OPTICAL SEMICONDUCTOR DEVICE OBTAINED USING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE - The present invention relates to an epoxy resin composition for an optical semiconductor device, including the following ingredients (A) to (E): (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) a silane coupling agent, in which a total content of the ingredient (C) and the ingredient (D) is from 69 to 94% by weight of the whole of the epoxy resin composition, and the ingredient (E) is contained in an amount satisfying the specific conditions. | 02-07-2013 |
20130037925 | AREA ARRAY QFN - A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame. | 02-14-2013 |
20130037926 | Lead Assembly for a Flip-Chip Power Switch - A power switch assembly includes a flip-chip type integrated circuit chip and a lead-frame with a plurality of spaced apart parallel lead sections. The flip-chip type integrated circuit chip includes a distributed transistor, and first and second pluralities of flip-chip interconnects connected to source and drain regions, respectively. The first and second lead sections at least partially overlap along the first axis. Each of the plurality of lead sections includes a contact portion and an extended portion extending laterally from the contact portion. The extended portions of the first and second lead section extend from the contact portion in opposite directions. The first side of the first and second lead section contacts at least two of the first and plurality of flip-chip interconnects, respectively. The second side of the first and second lead are configured to contact a first and second contact area on a printed circuit board, respectively. | 02-14-2013 |
20130037927 | LEAD CARRIER WITH MULTI-MATERIAL PRINT FORMED PACKAGE COMPONENTS - A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each site includes a die attach pad surrounded by terminal pads. The pads are formed of multiple materials including a lower layer and a body portion. An upper layer can also be provided over the body portion. A chip is mounted upon the die pad and wire bonds extend from the chip to the terminal pads. These parts are all encapsulated within a mold compound. The body portion is preferably formed by providing a matrix of metal powder and a suspension medium at locations where the pads are to be located. Heat is applied to disperse the suspension medium and sinter the metal powder to form the body portion. After encapsulation the temporary support member can be peeled away and the package sites isolated from each other. | 02-14-2013 |
20130043573 | Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores - A semiconductor die is solder bump-bonded to a leadframe or circuit board using solder balls having cores made of a material with a melting temperature higher than the melting temperature of the solder to ensure that in the finished structure the die is parallel to the leadframe or circuit board. | 02-21-2013 |
20130043574 | Multi-Die Semiconductor Package With One Or More Embedded Die Pads - To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package. | 02-21-2013 |
20130043575 | CHIP-PACKAGING MODULE FOR A CHIP AND A METHOD FOR FORMING A CHIP-PACKAGING MODULE - A chip-packaging module for a chip is provided, the chip-packaging module including a chip including a first chip side, wherein the first chip side includes an input portion configured to receive a signal; a chip carrier configured to be in electrical connection with the first chip side, wherein the chip is mounted to the chip carrier via the first chip side; and a mold material configured to cover the chip on at least the first chip side, wherein at least part of the input portion is released from the mold material. | 02-21-2013 |
20130043576 | SEMICONDUCTOR DEVICE - To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP | 02-21-2013 |
20130043577 | MANUFACTURING METHOD THEREOF AND A SEMICONDUCTOR DEVICE - In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals. | 02-21-2013 |
20130049183 | POWER DEVICE AND METHOD OF PACKAGING SAME - A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers. | 02-28-2013 |
20130062746 | Soldering Relief Method and Semiconductor Device Employing Same - A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device. | 03-14-2013 |
20130062747 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer, a two-step cutting technique is used for dicing. After formation of a groove in a semiconductor wafer with a tapered blade, the groove is divided with a straight blade thinner than the groove width. The multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can thus be diced without damaging a relatively fragile low-k layer. | 03-14-2013 |
20130062748 | EPOXY RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULANT AND SEMICONDUCTOR DEVICE USING THE SAME - According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R | 03-14-2013 |
20130069214 | LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING LEAD FRAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame or semiconductor device and a method of manufacturing the same in which where the unit lead frame of each semiconductor device after dicing was located in a lead frame before dicing can be known without an additional manufacturing step. The lead frame includes a plurality of unit lead frames each having a die pad, suspension leads coupled to the die pad, and leads formed around the die pad. An identification mark including at least one of a penetrating groove, recess, and convex is formed in at least one of the die pad, suspension leads, and leads. The identification mark of a first unit lead frame and the identification mark of a second unit lead frame are different from each other at least either in location in the unit lead frame or in shape. | 03-21-2013 |
20130075883 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side. | 03-28-2013 |
20130075884 | SEMICONDUCTOR PACKAGE WITH HIGH-SIDE AND LOW-SIDE MOSFETS AND MANUFACTURING METHOD - A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction. | 03-28-2013 |
20130075885 | LEAD FRAME AND PACKAGING METHOD - There is provided a lead frame and a packaging method. The lead frame comprises a first plurality of die pads, a second plurality of leads extending from the first plurality of die pads, and a third plurality of tie elements, each of which connects one of the first plurality of die pads to another. | 03-28-2013 |
20130082371 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a die pad, at least one semiconductor die mounted on the die pad, a plurality of leads disposed along peripheral edges of the die pad, at least one connecting bar for supporting the die pad, a first power bar disposed on one side of the connecting bar, a second power bar disposed on the other side of the connecting bar, and a connection member traversing the connecting bar and electrically connecting the first power bar with the second power bar. | 04-04-2013 |
20130087901 | DESIGN FOR EXPOSED DIE PACKAGE - In one aspect of the present invention, an integrated circuit package with an exposed die and a protective housing will be described. The housing extends beyond the exposed back surface of the die to help protect it from damage. The integrated circuit package includes a lead frame and an integrated circuit die. The integrated circuit die is electrically and physically attached to the lead frame. The housing encapsulates the lead frame and the die. The housing also includes a recessed region at the bottom of the package where the back surface of the die is exposed. There is a protruding protective structure at the bottom of the package that helps to protect the die and prevent its exposed back surface from coming in contact with an external object. | 04-11-2013 |
20130093072 | LEADFRAME PAD DESIGN WITH ENHANCED ROBUSTNESS TO DIE CRACK FAILURE - A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die. | 04-18-2013 |
20130099365 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME LEAD ARRAY ROUTING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe with a grid lead and a support pad; connecting a redistribution layer to the grid lead, the redistribution layer over the support pad; mounting an integrated circuit over the redistribution layer; applying an encapsulation on the redistribution layer, the redistribution layer in an interior area of the leadframe and the interior area under the integrated circuit; forming a support pad residue on the bottom surface of the redistribution layer by removing the support pad under the encapsulation and the interior redistribution layer; and forming an insulation layer on the support pad residue and the grid lead. | 04-25-2013 |
20130099366 | SYSTEMS AND METHODS FOR LEAD FRAME LOCKING DESIGN FEATURES - Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle. | 04-25-2013 |
20130099367 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLANARITY CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation. | 04-25-2013 |
20130105955 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME | 05-02-2013 |
20130105956 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME | 05-02-2013 |
20130105957 | LEAD FRAME SEMICONDUCTOR DEVICE | 05-02-2013 |
20130105958 | Compact Wirebonded Power Quad Flat No-Lead (PQFN) Package | 05-02-2013 |
20130113090 | POWER MODULE, ELECTRICAL POWER CONVERTER, AND ELECTRIC VEHICLE - In order to prevent an increase in temperature of a discharge resistance discharging an electric charge accumulated in a smoothing capacitor, the present description discloses a power module. The power module has a first lead frame, a second lead frame, first and second semiconductor switches connected in series between the first lead frame and the second lead frame, a resistor connected between the first lead frame and the second lead frame, and a resin package that encapsulates the first lead frame, the second lead frame, the first semiconductor switch, the second semiconductor switch, and the resistor. In this power module, a radiator portion for radiating heat from the first lead frame and/or the second lead frame is formed in at least a part of the package. | 05-09-2013 |
20130119526 | LEAD FRAME, SEMICONDUCTOR MANUFACTURING APPARATUS, AND SEMICONDUCTOR DEVICE - According to one embodiment, a lead frame includes a die pad having a mounting surface on which a semiconductor chip is mounted, plural leads having inner leads and outer leads, and a connecting member that extends from the die pad to both ends of a plurality of leads and connects the die pad and the plurality leads so that the ends of the inner leads are positioned above of the mounting surface. | 05-16-2013 |
20130127030 | SEMICONDUCTOR DEVICE PACKAGING HAVING SUBSTRATE WITH PRE-ENCAPSULATION THROUGH VIA FORMATION - A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided. | 05-23-2013 |
20130127031 | CHIP-CARRIER, A METHOD FOR FORMING A CHIP-CARRIER AND A METHOD FOR FORMING A CHIP PACKAGE - Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity. | 05-23-2013 |
20130127032 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened. | 05-23-2013 |
20130127033 | SEMICONDUCTOR DEVICE - A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. | 05-23-2013 |
20130127034 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a lead frame; a semiconductor element held by the lead frame; a frame body which is formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; and a protective resin filling a region surrounded by the frame body. The lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame, and is covered with the frame body. | 05-23-2013 |
20130134569 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package. | 05-30-2013 |
20130147024 | BALANCED LEADFRAME PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion. | 06-13-2013 |
20130147025 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - A first chip is mounted on a substrate and includes a plurality of bump pads located on an active surface of the first chip. A wire bonds a first bump pad to the substrate. An intermediate layer is disposed on a portion of the active surface of the first chip, and a via within the intermediate layer extends to a second bump pad. A second chip is disposed on the intermediate layer, and wherein the second chip includes a third bump pad located on an active surface of the second chip and aligned with the via formed in the intermediate layer. A corresponding bump is disposed on one or more of the second bump pad and the third bump pad, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. | 06-13-2013 |
20130154071 | Isolation Barrier Device and Methods of Use - Systems and methods pertaining to a digital signal isolator device are described. In one embodiment, the device includes an isolation barrier and two metal support paddles. The isolation barrier contains an organic and/or a semi-organic insulating material with at least one capacitor embedded inside. One of the two metal support paddles is located below a first portion of a bottom surface of the isolation barrier to provide support to the isolation barrier, while the other metal support paddle is located below a second portion of a bottom surface of the isolation barrier to provide support to the isolation barrier. | 06-20-2013 |
20130154072 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit. | 06-20-2013 |
20130154073 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND LEADFRAME THEREFOR - In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection. | 06-20-2013 |
20130154074 | SEMICONDUCTOR STACK PACKAGES AND METHODS OF FABRICATING THE SAME - Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided. | 06-20-2013 |
20130154075 | SEMICONDUCTOR DEVICE - In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur. | 06-20-2013 |
20130154076 | Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads. | 06-20-2013 |
20130161804 | INTEGRATED CIRCUIT (IC) LEADFRAME DESIGN - Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of adjacent lead fingers are staggered proximate and distal the at least one edge. | 06-27-2013 |
20130161805 | INTEGRATED CIRCUIT (IC) LEADFRAME DESIGN - Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge, the at least one edge having one or more slots located therein. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of pairs of adjacent lead fingers extend into corresponding slots in the paddle. | 06-27-2013 |
20130161806 | WINDOW CLAMP TOP PLATE FOR INTEGRATED CIRCUIT PACKAGING - A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding. | 06-27-2013 |
20130168841 | Programmable Interposer with Conductive Particles - An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes. | 07-04-2013 |
20130175679 | OPTOISOLATOR LEADFRAME ASSEMBLY - An optoisolator leadframe assembly includes: an emitter leadframe part including a first rail and a plurality of emitter leadframe units, each rail including two rows of emitter leadframes, each having a die-mounting pad; and a receiver leadframe part including a second rail and a plurality of receiver leadframe units, each including two rows of receiver leadframes, each having a die-mounting pad. The die-mounting pads of the emitter leadframes of each row of each of the emitter leadframe units are respectively aligned with and spaced apart from the die-mounting pads of the receiver leadframes of an adjacent row of an adjacent one of the receiver leadframe units. Each of the emitter and receiver leadframe parts is a single piece. | 07-11-2013 |
20130181334 | CONNECTOR AND RESIN-SEALED SEMICONDUCTOR DEVICE - A connector for electrically connecting a chip electrode of a semiconductor element to a lead constituting an external leading terminal of the chip electrode, includes a first connecting part having an interface joined to the chip electrode; a second connecting part having an interface joined to a base end part of the lead; and a plate-shape coupling part for connecting the first connecting part and the second connecting part to each other, and having a step formed on the interface of the first connecting part in a direction away from the chip electrode by a half blanking process. | 07-18-2013 |
20130181335 | LEADFRAME AND SEMICONDUCTOR PACKAGE MADE USING THE LEADFRAME - Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the leadframe includes a rectangular frame. A chip pad and a plurality of leads are within the frame. The lower side of the chip pad and the leads includes one or more vertically recessed horizontal surfaces. The upper side of the chip pad may include a groove around a chip mounting region. In a package, the chip pad supports a semiconductor chip electrically connected to the leads. The lower side of the chip pad and leads are exposed at an exterior surface of the package body. Encapsulant material underfills the recessed lower surfaces of the chip pad and leads, thereby locking them to the encapsulant material. A wire may be reliably bonded to the chip pad within the groove formed in the upper side thereof. | 07-18-2013 |
20130187260 | PACKAGED SEMICONDUCTOR DEVICES, AND RELATED METHODS AND SYSTEMS - A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers. | 07-25-2013 |
20130187261 | SEMICONDUCTOR DEVICE - Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached and a second mount region to which a controlling semiconductor chip is fixedly attached are formed isolated from each other. A projecting area is formed in the first mount region, and the projecting area protrudes into the second mount region. The controlling semiconductor chip is fixedly attached to the top surfaces of the projecting area and the second mount region by use of an insulating adhesive sheet material. This structure prevents the short circuit between the two chips, and improves accuracy in temperature detection with the controlling semiconductor chip. | 07-25-2013 |
20130193567 | LEAD FRAME AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a lead frame, includes forming a rectangular first dimple includes, first inclined side surfaces inclined to a depth direction, and arranged in two opposing sides in one direction, and standing side surfaces standing upright to a depth direction, and arranged in two opposing sides in other direction, on a backside of a die pad by a first stamping, and forming a second dimple having second inclined side surfaces inclined on the backside of the die pad by a second stamping, such that a second inclined side surfaces of the second dimple are arranged in side areas of the standing side surfaces of the first dimple, wherein the standing side surfaces are transformed into reversed inclined side surfaces inclined to a reversed direction to the first inclined side surfaces, and a front side of the die pad is semiconductor element mounting surface. | 08-01-2013 |
20130200506 | METHOD OF PREVENTING EPOXY BLEED OUT OF LEAD FRAME AND LEAD FRAME MANUFACTURED BY USING THE SAME - The epoxy bleed out prevention method including: providing a lead frame that is manufactured through a shaping process which forms a die pad and a plurality of leads by using a conductive raw material, a pre-plating process performed on the shaped conductive raw material, and a tape attaching process; and performing a bleed out prevention process which prevents an epoxy bleed out of a die bonding epoxy-based resin applied on the die pad after the tape attaching process. | 08-08-2013 |
20130200507 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 08-08-2013 |
20130200508 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques. | 08-08-2013 |
20130207250 | CHIP ATTACH FRAME - A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads. | 08-15-2013 |
20130207251 | SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY - A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion. | 08-15-2013 |
20130207252 | Semiconductor Device - To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire. | 08-15-2013 |
20130214398 | Semiconductor Device and Method of Forming Base Leads from Base Substrate as Standoff for Stacking Semiconductor Die - A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die. | 08-22-2013 |
20130214399 | DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology - Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices. | 08-22-2013 |
20130221506 | Semiconductor Packages with Integrated Heat Spreaders - One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader. | 08-29-2013 |
20130221507 | ALUMINUM ALLOY LEAD-FRAME AND ITS USE IN FABRICATION OF POWER SEMICONDUCTOR PACKAGE - A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air. | 08-29-2013 |
20130221508 | SEMICONDUCTOR DEVICE SEALED WITH A RESIN MOLDING - An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's. | 08-29-2013 |
20130221509 | LEAD FRAME FOR MOUNTING LED ELEMENTS, LEAD FRAME WITH RESIN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES, AND LEAD FRAME FOR MOUNTING SEMICONDUCTOR ELEMENTS - A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region. | 08-29-2013 |
20130228907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. | 09-05-2013 |
20130228908 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a resin sealed semiconductor device with improved reliability. After positioning a cap (lid) so as to cover semiconductor chips and wires, resin is supplied into a space formed by the cap, so that a sealing body is formed to cover the semiconductor chips and the wires. In the step of forming the sealing body, the resin is supplied from an opening formed at a corner of the cap in the planar view. The sealing body is exposed at the corner of the cap, so that the exposed part of the sealing body can be kept away from the wires. | 09-05-2013 |
20130234307 | LEAD FRAME LAND GRID ARRAY - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 09-12-2013 |
20130234308 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED DEVICE AND METHOD OF MANUFACTURING THE SAME - A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip. | 09-12-2013 |
20130234309 | SEMICONDUCTOR DEVICE - Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads. | 09-12-2013 |
20130241041 | SEMICONDUCTOR PACKAGES WITH LEAD EXTENSIONS AND RELATED METHODS - A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface. | 09-19-2013 |
20130241042 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING SAME - In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same. | 09-19-2013 |
20130249068 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer. | 09-26-2013 |
20130249069 | CIRCUIT PACKAGE, AN ELECTRONIC CIRCUIT PACKAGE, AND METHODS FOR ENCAPSULATING AN ELECTRONIC CIRCUIT - A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures. | 09-26-2013 |
20130249070 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film. | 09-26-2013 |
20130249071 | SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME - A method of assembling a semiconductor device includes providing a lead frame having a die pad and a fame member with lead fingers that surround the die pad. The lead fingers have distal ends connected to the frame member and proximal ends near the die pad. A die is attached to the die pad and die connection pads are electrically connected to the proximal ends of the lead fingers with bond wires. The die, bond wires, and part of the lead fingers are encapsulated with an encapsulant. The encapsulating process includes separating the lead fingers into first and second sets of lead fingers. The proximal ends of the first set lie in a first plane and the proximal ends of the second set lie in a second plane that is spaced and maintained from the first plane solely by the encapsulation material. | 09-26-2013 |
20130249072 | Direct Contact Package for Power Transistors - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 09-26-2013 |
20130256855 | CHIP ARRANGEMENT, A METHOD FOR FORMING A CHIP ARRANGEMENT, A CHIP PACKAGE, A METHOD FOR FORMING A CHIP PACKAGE - A chip arrangement is provided, the chip arrangement including: a first chip carrier; a second chip carrier; a first chip electrically connected to the first chip carrier; a second chip disposed over the first chip carrier and electrically insulated from the first chip carrier; and a third chip electrically connected to the second chip carrier; wherein at least one of the first chip and the second chip is electrically connected to the third chip. | 10-03-2013 |
20130256856 | Multichip Power Semiconductor Device - An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor. | 10-03-2013 |
20130256857 | Semiconductor Packages and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. | 10-03-2013 |
20130256858 | PCB Based RF-Power Package Window Frame - A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate. | 10-03-2013 |
20130256859 | Dual Power Converter Package Using External Driver IC - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively. | 10-03-2013 |
20130256860 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead. | 10-03-2013 |
20130256861 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals. | 10-03-2013 |
20130256862 | Support Device for a Semiconductor Chip and Optoelectronic Component with a Carrier Device and Electronic Component with a Carrier Device - A carrier device for a semiconductor chip includes a bondable and/or solderable metallic carrier having a mounting region for the semiconductor chip and a soldering region. The carrier is at least partly covered with a covering material. A solder barrier is arranged between the soldering region and the mounting region at an interface between the carrier and the covering material. An electronic component and an optoelectronic component are furthermore specified. | 10-03-2013 |
20130256863 | EPOXY RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION AND SEMICONDUCTOR DEVICE - A highly reliable semiconductor device with the improved humidity resistance reliability is disclosed. A disclosed epoxy resin composition for semiconductor encapsulation encapsulates, in the manufacture of the semiconductor device, a semiconductor element that is mounted on a lead frame having a die pad unit or a circuit substrate and a wire that connects an electrical junction disposed on the lead frame or circuit substrate and an electrode pad disposed on the semiconductor element. The epoxy resin composition includes an epoxy resin (A), a curing agent (B), and an inorganic filler (C). The epoxy resin (A) has a main peak area of 90% or more with respect to the total area of all peaks as measured by the gel permeation chromatography area method. | 10-03-2013 |
20130264693 | LEAD FRAME WITH GROOVED LEAD FINGER - A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding. | 10-10-2013 |
20130264694 | ELECTRONIC PACKAGE STRUCTURE HAVING EXPOSED LANDS AND METHOD - In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands. | 10-10-2013 |
20130264695 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor device includes a unit component including a wiring portion formed by electrically connecting a die pad of and a lead of a lead frame, and a semiconductor package whose connection terminal is connected to the lead, wherein the unit component is stacked, and the leads located to upper and lower sides are connected mutually via an electrode. | 10-10-2013 |
20130264696 | SEMICONDUCTOR DEVICE - A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction. | 10-10-2013 |
20130277813 | CHIP PACKAGE AND METHOD OF FORMING THE SAME - Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip. | 10-24-2013 |
20130277814 | METHOD FOR FIXING SEMICONDUCTOR CHIP ON CIRCUIT BOARD AND STRUCTURE THEREOF - A method for fixing a semiconductor chip on a circuit board is provided, which includes following steps. The circuit board is provided, which sequentially includes a substrate having a chip connecting portion, at least one metal wire and an insulating layer. An organic insulating material is formed on the insulating layer of the outside edge of the chip connecting portion. An anisotropic conductive film (ACF) is then formed to cover the chip connecting portion and a portion of the organic insulating material. Finally, a semiconductor chip is hot-pressed on the ACF. The organic insulating material formed on the insulating layer is used to prevent the metal wires beneath the insulating layer from occurring of corrosion. A semiconductor chip package structure is also provided. | 10-24-2013 |
20130277815 | METHOD OF FORMING A THIN SUBSTRATE CHIP SCALE PACKAGE DEVICE AND STRUCTURE - In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure. | 10-24-2013 |
20130277816 | PLASTIC-PACKAGED SEMICONDUCTOR DEVICE HAVING WIRES WITH POLYMERIZED INSULATOR SKIN - The assembly of a chip ( | 10-24-2013 |
20130277817 | LEAD FRAME, SEMICONDUCTOR PACKAGE, AND MANUFACTURING METHOD OF THE SAME - A semiconductor package includes a lead frame including a chip mounting portion and a terminal portion, a semiconductor chip, which is mounted on the chip mounting portion and connected to the terminal portion, a through groove penetrating the terminal portion from one surface on a side of the semiconductor chip to another surface in a thickness direction of the terminal portion, a lid portion covering an end portion of the through groove on the side of the semiconductor chip, and a resin portion sealing the semiconductor chip, wherein the another surface of the terminal portion and a side surface of the terminal portion facing an outside of the semiconductor package are coated by a plating film. | 10-24-2013 |
20130277818 | CHIP CARRIER SUPPORT SYSTEMS - In one embodiment, a chip carrier support system includes a chip carrier support structure and a chip carrier. The chip carder forms a complementary fit with the chip carder support structure and includes an integrated circuit and a plurality of leads in communication with the integrated circuit. | 10-24-2013 |
20130285222 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including: a lead frame including a chip attachment unit and a lead unit; a semiconductor chip that is mounted on the chip attachment unit of the lead frame; a wire that electrically connects the semiconductor chip to the lead unit; an insulation layer formed in the lead frame under the chip attachment unit; and an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire, wherein the lead unit does not protrude to the outside of the encapsulant. | 10-31-2013 |
20130285223 | METHOD FOR MANUFACTURING ELECTRONIC DEVICES - A support structure includes a support cell with a support substrate, junction sacrificial portions surrounding the support substrate, and pin blocks extending from the junction sacrificial portion toward the support substrate. A semiconductor chip is mounted to the support substrate and electrically wire bonded to the pin blocks. An encapsulating body covers the chip, with the pin blocks extending from the body. A transversal groove is formed in each pin block. Surfaces of the pin block and groove are electroplated with solder material. Each pin block is sectioned at the groove to define a pin having a first end corresponding to a portion of the groove surface of the groove and a second end corresponding to the sectioned portion of the pin block that is not electroplated with solder material. Sectioning causes the separation of the chip-insulating body assembly from the junction sacrificial portions. | 10-31-2013 |
20130285224 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes a lead frame, an oscillator, an integrated circuit and first bonding wires. The oscillator includes plural terminals separated from each other by a predetermined distance, and that is mounted to an oscillator mounting region formed on a first face of the lead frame. The oscillator mounting region has a narrower width than the distance between the plural terminals. The integrated circuit is mounted to a second face of the lead frame, which is on an opposite side to the first face. The first bonding wires connect the plural terminals of the oscillator to terminals of the integrated circuit. | 10-31-2013 |
20130285225 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components. | 10-31-2013 |
20130285226 | SYSTEMS AND METHODS FOR LEAD FRAME LOCKING DESIGN FEATURES - Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle. | 10-31-2013 |
20130285227 | LEADFRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire. | 10-31-2013 |
20130292811 | LEADFRAME HAVING SELECTIVE PLANISHING - A metal leadframe strip ( | 11-07-2013 |
20130292812 | LEAD FRAME FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE USING THE LEAD FRAME - A lead frame for a semiconductor device and a semiconductor device package using the lead frame. The lead frame includes a package body having an internal space configured to mount a semiconductor device, and a lead unit disposed so as to apply voltages to the semiconductor device. The lead unit includes internal leads embedded in the package body and having an area in which the semiconductor device is to be mounted, and external leads each being connected to the internal leads, respectively . Each external lead protrudes from the package body and each has a contact portion that contacts a printed circuit board (PCB). The lead frame also includes and a support structure disposed on external sides of the package body and supporting the external leads. | 11-07-2013 |
20130292813 | MULTI-CHIP FLIP CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A multi-chip flip chip package includes multiple dies. Each die comprises several pads for coupling with pads of the other die and for coupling with pins of the multi-chip flip chip package through conducting elements. A dielectric element is positioned between the dies and the conducting elements, and positioned between the dies for providing the electrical insulation. The dies and the conducting elements between the dies are coated with a packaging element for preventing physical damage and corrosion. | 11-07-2013 |
20130292814 | INTEGRATED POWER CONVERTER PACKAGE WITH DIE STACKING - An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry. | 11-07-2013 |
20130292815 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. | 11-07-2013 |
20130299956 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - There is provided a technology by which the position of 1 pin in a tabless package can be recognized easily. The rear surfaces of plural leads are exposed on a rear surface of a resin-sealed body which seals a semiconductor chip etc., a image recognition area is further provided adjacent to 1 pin (lead with index 1), and a rear surface of an identification mark is exposed from the rear surface of the resin-sealed body of the image recognition area. This identification mark is made of the same conductive member as the plural leads. | 11-14-2013 |
20130299957 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip. | 11-14-2013 |
20130299958 | LEAD STRUCTURES WITH VERTICAL OFFSETS - A microelectronic structure includes a first row of contacts ( | 11-14-2013 |
20130307131 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least one semiconductor chip, a first lead, and a second lead. The first lead includes a first portion connected to the semiconductor chip via a first wiring. The second lead includes a first portion connected to the semiconductor chip via a second wiring. The first portion of the first lead and the first portion of the second lead extend along a first direction. The first portion of the first lead is disposed so as to oppose the first portion of the second lead. The semiconductor chip is disposed between the first portion of the first lead and the first portion of the second lead. | 11-21-2013 |
20130307132 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least one semiconductor chip and a lead. The lead has a first portion connected to the semiconductor chip via a wiring. The first portion of the lead extends along a first direction and is placed so as to face the semiconductor chip. | 11-21-2013 |
20130320515 | SYSTEM, METHOD AND APPARATUS FOR LEADLESS SURFACE MOUNTED SEMICONDUCTOR PACKAGE - A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body. | 12-05-2013 |
20130328181 | ELECTRONIC SYSTEM WITH A COMPOSITE SUBSTRATE - A composite substrate made of a conductive pattern structure mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the conductive pattern structure. Metal lines are used for electrical coupling between the circuitry of the IC chip and the conductive pattern structure. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the conductive pattern structure and good heat distribution from the lead frame. | 12-12-2013 |
20130334674 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TIEBAR-LESS DESIGN AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die attach pad integrally connected to a connector portion and a lead; attaching an integrated circuit die to the die attach pad; connecting an internal interconnect to the integrated circuit die and the lead; forming an encapsulation over the integrated circuit die; removing the connector portion to separate the die attach pad and the lead; and forming an isolation cover between the die attach pad and the lead. | 12-19-2013 |
20130334675 | PACKAGE STRUCTURE HAVING LATERAL CONNECTIONS - An embodiment of a packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor. Thus, well-established techniques for incorporating a lead frame or any other conductive system in a package may be applied in order to impart wireless lateral connectivity to packaged semiconductor devices in an electronic system. | 12-19-2013 |
20130341778 | Device Contact, Electric Device Package and Method of Manufacturing an Electric Device Package - An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer. | 12-26-2013 |
20130341779 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a sealing step of sealing an inner lead of a lead frame with a resin, and a bending step of bending a target bending region in which a stress by bending is not applied to a resin burr generated in the sealing step. | 12-26-2013 |
20140001615 | Package-In-Packages and Methods of Formation Thereof | 01-02-2014 |
20140001616 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE | 01-02-2014 |
20140001617 | METHOD OF USING BONDING BALL ARRAY AS HEIGHT KEEPER AND PASTE HOLDER IN SEMICONDUCTOR DEVICE PACKAGE | 01-02-2014 |
20140001618 | SOLDER FLOW IMPEDING FEATURE ON A LEAD FRAME | 01-02-2014 |
20140001619 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME | 01-02-2014 |
20140001620 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE | 01-02-2014 |
20140001621 | SEMICONDUCTOR PACKAGES HAVING INCREASED INPUT/OUTPUT CAPACITY AND RELATED METHODS | 01-02-2014 |
20140008777 | THERMAL LEADLESS ARRAY PACKAGE WITH DIE ATTACH PAD LOCKING FEATURE - Embodiments of the present invention are directed to a thermal leadless array package with die attach pad locking feature and methods of producing the same. A copper layer is half-etched on both surfaces to define an array of package contacts and a die attach pad. Each die attach pad is fully embedded in encapsulate material to provide a positive mechanical locking feature for better reliability. In some embodiments, the contacts include four active corner contacts. | 01-09-2014 |
20140008778 | PHOTONIC SEMICONDUCTOR DEVICES IN LLC ASSEMBLY WITH CONTROLLED MOLDING BOUNDARY AND METHOD FOR FORMING SAME - Embodiments of a laminate leadless carrier package are presented. The package includes an optoelectronic chip, a substrate supporting the optoelectronic chip, a plurality of conductive slotted vias, a wire bond pad disposed on the top surface of the substrate, a wire bond coupled to the optoelectronic chip and the wire bond pad and an encapsulation covering the optoelectronic chip, the wire bond, and at least a portion of the top surface of the substrate. The slotted vias provide electrical connections between the top conductive layer and the bottom conductive layer. The substrate includes a plurality of conductive and dielectric layers laminated together including a bottom conductive layer, a top conductive layer, and a dielectric layer between the top and bottom conductive layers. The encapsulation is a molding compound, and the molding compound is pulled back from at least one of the slotted vias. | 01-09-2014 |
20140015117 | VERY EXTREMELY THIN SEMICONDUCTOR PACKAGE - A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. | 01-16-2014 |
20140027892 | Electric Device Package Comprising a Laminate and Method of Making an Electric Device Package Comprising a Laminate - A system and method for manufacturing an electric device package are disclosed. An embodiment comprises comprising a first carrier contact, a first electric component, the first electric component having a first top surface and a first bottom surface, the first electric component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier and an connection element comprising a second electric component and an interconnect element, the connection element having a connection element top surface and a connection element bottom surface, wherein the connection element bottom surface comprises a first connection element contact and a second connection element contact, and wherein the first connection element contact is connected to the first component contact and the second connection element contact is connected to the first carrier contact. The packaged device further comprises an encapsulant encapsulating the first electric component. | 01-30-2014 |
20140027893 | CIRCUIT SUBSTRATE FOR MOUNTING CHIP, METHOD FOR MANUFACTURING SAME AND CHIP PACKAGE HAVING SAME - A circuit board includes an insulation layer, an electrically conductive layer, and a solder mask layer. The insulation layer has a plurality of through holes passing through. The electrically conductive layer is formed on a surface of the insulation layer and covers the through holes. The electrically conductive layer has a plurality of portions exposed in the through holes to serve as a plurality of first conductive pads. The solder mask layer covers the electrically conductive layer and defines a plurality of openings to expose parts of the electrically conductive layer. Parts of the electrically conductive layer are exposed to the solder mask layer to serve as a plurality of second conductive pads. The second conductive pads are electrically connected to the first conductive pads respectively. This disclosure further relates to a chip package and a method of manufacturing the same. | 01-30-2014 |
20140027894 | RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame. | 01-30-2014 |
20140035113 | PACKAGING AND METHODS FOR PACKAGING - A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead. | 02-06-2014 |
20140035114 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD - In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network. | 02-06-2014 |
20140035115 | SEMICONDUCTOR DEVICE - A semiconductor device includes any one of a lead frame having a die pad portion and a circuit board, one or more semiconductor elements, a copper wire, an encapsulating member. The one or more semiconductor elements are mounted on any one of the die pad portion of the lead frame and the circuit board. The copper wire electrically connects electrical joints provided on any one of the lead frame and the circuit board to an electrode pad provided on the semiconductor element. The encapsulating member encapsulates the semiconductor element and the copper wire. The electrode pad provided on the semiconductor element is formed from palladium. The copper wire has a copper purity of 99.99% by mass or more and an elemental sulfur content of 5 ppm by mass or less. | 02-06-2014 |
20140035116 | Top Exposed Semiconductor Chip Package - A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls. | 02-06-2014 |
20140042603 | Electronic Device and Method of Fabricating an Electronic Device - A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip. | 02-13-2014 |
20140042604 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR PACKAGE - Disclosed herein is a three-dimensional (3D) semiconductor package. The 3D semiconductor package includes a printed circuit board, a main interposer that is formed on the printed circuit board, a semiconductor device that is formed on the main interposer, and a support interposer that is disposed on the same plane as a plane of the semiconductor device, or disposed between the main interposer and the semiconductor device. Here, each of the main interposer, the semiconductor device, and the support interposer may include a through-via formed based on a thickness direction of the printed circuit board. | 02-13-2014 |
20140042605 | LEAD FRAME PACKAGE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip. | 02-13-2014 |
20140048919 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ARRAY CONTACTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire. | 02-20-2014 |
20140048920 | Selective Leadframe Planishing - A metal leadframe strip ( | 02-20-2014 |
20140054759 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented. | 02-27-2014 |
20140061883 | LEADFRAMES, AIR-CAVITY PACKAGES, AND ELECTRONIC DEVICES WITH OFFSET VENT HOLES, AND METHODS OF THEIR MANUFACTURE - A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings. | 03-06-2014 |
20140061884 | STACKED DIE POWER CONVERTER - A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die. | 03-06-2014 |
20140061885 | Power Quad Flat No-Lead (PQFN) Package - Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes. | 03-06-2014 |
20140061886 | Semiconductor Package with Interposer - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 03-06-2014 |
20140070388 | SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME - A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package. | 03-13-2014 |
20140070389 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other. | 03-13-2014 |
20140070390 | MULTI-CHIP PACKAGING STRUCTURE AND METHOD - Disclosed are multi-chip packaging structures and methods. In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper surface of each chip comprises a plurality of pads; (ii) a lead frame with a chip carrier and a plurality of pins, where the N chips are stacked in layers on the chip carrier, and where a chip in an upper layer partially covers a chip in a lower layer such that the plurality of pads of the lower layer chip are exposed; (iii) a plurality of first bonding leads configured to connect pads on one chip to pads on another chip; and (iv) a plurality of second bonding leads configured to connect pads on at least one chip to the plurality of pins for external connection to the multi-chip packaging structure. | 03-13-2014 |
20140070391 | LEAD CARRIER WITH PRINT-FORMED TERMINAL PADS - A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a plurality of terminal pads surrounding a die attach region. The pads are formed of sintered electrically conductive material. A chip is placed at the die attach region and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronic system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package. | 03-13-2014 |
20140070392 | COMMON DRAIN POWER CLIP FOR BATTERY PACK PROTECTION MOSFET - A first embodiment is a common drain+clip | 03-13-2014 |
20140077347 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other. | 03-20-2014 |
20140077348 | SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME - A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. | 03-20-2014 |
20140084432 | METHOD AND APPARATUS FOR MULTI-CHIP STRUCTURE SEMICONDUCTOR PACKAGE - A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect. | 03-27-2014 |
20140084433 | Semiconductor Device Having a Clip Contact - A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device. | 03-27-2014 |
20140084434 | SEMICONDUCTOR DEVICE - A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN. | 03-27-2014 |
20140084435 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part. | 03-27-2014 |
20140084436 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained. | 03-27-2014 |
20140084437 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIP MOUNTED ON LEAD FRAME - A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires. | 03-27-2014 |
20140084438 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device has a plurality of electronic components mounted on an insulating substrate formed with a metal layer, and electrically connected to each other or to the metal layer; a positioning wire member having a predetermined diameter and a predetermined length, and bonded to each of the plurality of electronic components or to the metal layer; a lead frame disposed to bridge and electrically connect the plurality of electronic components to each other or between the metal layer and the electronic components; and an opening having a size capable of inserting the wire member therethrough formed to penetrate through the lead frame, to join the lead frame to each of the electronic components or the metal layer at a predetermined position therein. The lead frame is positioned on the insulating substrate by inserting the wire member into the opening. | 03-27-2014 |
20140091447 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire. | 04-03-2014 |
20140091448 | Semiconductor Package with Corner Pins - There are provided semiconductor packages having corner pins and methods for their fabrication. Such a semiconductor package includes a leadframe and a die paddle, the leadframe having first and second edge sides meeting to form a first corner. The semiconductor package also includes edge pins arrayed substantially parallel to the first edge side and edge pins arrayed substantially parallel to the second edge side. In addition, the semiconductor package includes a first corner pin situated at the first corner, the first corner pin being electrically isolated from the die paddle. | 04-03-2014 |
20140091449 | Power Quad Flat No-Lead (PQFN) Semiconductor Package with Leadframe Islands for Multi-Phase Power Inverter - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a U-phase output node situated on a first leadframe island of a leadframe, a V-phase output node situated on a second leadframe island of said leadframe, and a W-phase output node situated on a W-phase die pad of said leadframe. The first leadframe island can be on a first leadframe strip of the leadframe, where the first leadframe strip is connected to a U-phase die pad of the leadframe. The second leadframe island can be on a second leadframe strip of the leadframe, where the second leadframe strip is connected to a V-phase die pad of the leadframe. A first W-phase power switch is situated on the W-phase die pad. Furthermore, at least one wirebond is connected to the W-phase die pad and to a source of a second W-phase power switch. The W-phase die pad can be a W-phase output terminal of the PQFN package. | 04-03-2014 |
20140097526 | PACKAGED IC HAVING PRINTED DIELECTRIC ADHESIVE ON DIE PAD - A method of assembling a packaged integrated circuit (IC) includes printing a viscous dielectric polymerizable material onto a die pad of a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto the viscous dielectric polymerizable material. Bond wires are wire bonded between the plurality of bond pads and the metal terminals of the leadframe. | 04-10-2014 |
20140097527 | METHOD OF MANUFACTURE INTEGRATED CIRCUIT PACKAGE - An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. Tape may be applied to the lower surface of the leadframe to support the shunt and hold it in place relative to the leadframe until wirebonding and encapsulation have been completed. Thereafter, the tape may be removed. | 04-10-2014 |
20140097528 | CHIP ARRANGEMENTS, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal. | 04-10-2014 |
20140097529 | SOLDER FLOW-IMPEDING PLUG ON A LEAD FRAME - Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch. | 04-10-2014 |
20140097530 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package and a manufacturing method thereof are provided. The integrated circuit package can include a substrate provided with a circuit pattern, a first set of bonding fingers and a second set of bonding fingers, a first chip stack mounted on the substrate and having a plurality of first semiconductor chips stacked in a first direction in a stepped manner, each of the first semiconductor chips being provided with a first bonding pad at an end thereof on one side, a second chip stack mounted on the first chip stack and having a plurality of second semiconductor chips stacked in a second direction opposite to the first direction in a stepped manner. | 04-10-2014 |
20140097531 | Power Quad Flat No-Lead (PQFN) Package in a Single Shunt Inverter Circuit - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC. | 04-10-2014 |
20140103507 | Optical Device Package And System - Optical device packages and systems are disclosed. In one embodiment, a system may comprise first and second optical device packages. A respective first and second optical path length may be associated with the first and second optical device packages. The first and second optical path lengths may be adjusted differently. However, respective first and second sets of external dimensions of the first and second optical device packages may be the same or substantially the same. In one embodiment, one or more Quad Flat No Lead (QFN) packages may be employed. | 04-17-2014 |
20140103508 | ENCAPSULATING PACKAGE FOR AN INTEGRATED CIRCUIT - An apparatus is provided. An integrated circuit or IC is secured to a package housing. The IC has an IC substrate and an epitaxial layer formed over the substrate and having an active region and an upper surface. The upper surface is substantially exposed, and bond pads are formed over the epitaxial layer. Bond fixtures are each secured to and in electrical contact with at least one of the bond pads and with the package housing. A fill formed over at least a portion of the epitaxial layer so as to substantially encapsulate the active region, where the fill has a dielectric constant that is substantially equivalent to the dielectric constant of air. Additionally, the fill has a thickness, where the thickness is sufficiently large enough to confine parasitics of the active region at the upper surface of the epitaxial layer. | 04-17-2014 |
20140103509 | Semiconductor Device and Method of Forming Conductive Ink Layer as Interconnect Structure Between Semiconductor Packages - A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device. | 04-17-2014 |
20140103510 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion. | 04-17-2014 |
20140103511 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE STORAGE METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view. | 04-17-2014 |
20140103512 | Dual-leadframe Multi-chip Package - A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. | 04-17-2014 |
20140103513 | SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY - A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion. | 04-17-2014 |
20140103514 | Power Quad Flat No-Lead (PQFN) Package Having Bootstrap Diodes on a Common Integrated Circuit (IC) - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase inverter situated on a leadframe. The PQFN package further includes drivers situated on the leadframe and configured to drive the multi-phase inverter. The PQFN package also includes bootstrap diodes respectively coupled to the drivers. The bootstrap diodes are in a common integrated circuit (IC) that is situated on the leadframe. The common IC can include the drivers. The drivers can be high side drivers that are coupled to high side power switches of the multi-phase inverter. Also, the bootstrap diodes can be coupled to a supply voltage terminal of the PQFN package. Furthermore, the PQFN package can include wirebonds coupling the common IC to bootstrap supply voltage terminals of the PQFN package. | 04-17-2014 |
20140103515 | SEMICONDUCTOR DEVICE - In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur. | 04-17-2014 |
20140110829 | Module Comprising a Semiconductor Chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 04-24-2014 |
20140117523 | STACKED DUAL-CHIP PACKAGING STRUCTURE AND PREPARATION METHOD THEREOF - The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate. | 05-01-2014 |
20140117524 | POWER SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - There are provided a power semiconductor module and a manufacturing method thereof, the power semiconductor module including: a lead frame; a base substrate including a circuit wiring formed on an insulating layer thereof; a plurality of power semiconductor devices disposed to contact the circuit wiring; and a multilayer substrate formed by stacking a plurality of substrates and electrically connecting the power semiconductor devices and the lead frame to one another using a connection line formed therein and having conductivity. | 05-01-2014 |
20140117525 | POWER MODULE PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a power module package including: a base substrate; a metal layer including a circuit pattern and a connection pad formed on the base substrate; a semiconductor device including a plurality of electrodes mounted on the circuit pattern of the metal layer; and a plurality of lead frames formed on the connection pad of the metal layer and respectively connected to the plurality of electrodes of the semiconductor device. | 05-01-2014 |
20140124912 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Each stitch part of a plurality of leads of a package has a first region having the most outer surface on which Ag plating is applied and a second region having the most outer surface on which Ni plating is applied. Further, the second region is arranged on a die pad side, and the first region is arranged on a periphery side of a sealer. Therefore, in each stitch part, types of plating applied on the most outer surfaces of the first region and the second region can be differentiated from each other, a thick Al wire can be connected to the second region of the second lead, and a thin Au wire can be connected to the first region of the first lead. As a result, usage of only Au plating can be avoided, so that the cost of the package is reduced. | 05-08-2014 |
20140131848 | LAND STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD THEREFOR - In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part. | 05-15-2014 |
20140131849 | STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR - A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. | 05-15-2014 |
20140138810 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connection between the second pad and outside, and the semiconductor chip is, on the one surface of the lead integrated island, disposed at a position one-sided to the first pad connecting terminal side, and the first pad and the one surface of the lead integrated island are connected by a wire. | 05-22-2014 |
20140145319 | Semicondutor Packages and Methods of Fabrication Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad. | 05-29-2014 |
20140145320 | DIE PACKAGE - An electronic device package including an electronic device within a block of insulating material, for example a QFN package. The paddle may be design to extend beyond the die to allow wirebonding between a region of the paddle and the die. Leads may be extended underneath the die and adhered to the die. | 05-29-2014 |
20140151865 | SEMICONDUCTOR DEVICE PACKAGES PROVIDING ENHANCED EXPOSED TOE FILLETS - A mechanism is provided by optically inspectable surface mount bonding of no-leads packages is enhanced. Embodiments of the present invention use a lead frame within the no-leads package that provides a plated surface not only along the bottom of the package but also in a direction substantially parallel to the sides of the package. Since the plated surface has a greater affinity for solder during a reflow process than does the bare metal of the lead frame, toe fillets have a greater chance of forming in a manner that can be optically inspected during a test for quality of the bonding of the package to a printed circuit board. In addition, a mold chase that conforms to the shape of the lead frame is used to prevent mold compound from adhering to the portions of the lead frame external to the package that are used as electrical contacts. | 06-05-2014 |
20140151866 | Packaged Semiconductor Device with Tensile Stress and Method of Making a Packaged Semiconductor Device with Tensile Stress - An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein the second thickness is larger than the first thickness. | 06-05-2014 |
20140151867 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 06-05-2014 |
20140159217 | MULTICHIP PACKAGE AND FABRICATION METHOD THEREOF - A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate. | 06-12-2014 |
20140159218 | CHIP PACKAGING STRUCTURE OF A PLURALITY OF ASSEMBLIES - Disclosed herein are chip packaging structures for packaging multiple assemblies therein. In one embodiment, a chip packaging structure can include: (i) a first assembly located at a bottom layer of the chip packaging structure; (ii) at least one second assembly located above the first assembly, where the second assembly is electrically connected to the first assembly by a plurality of first protruding structures located under the second assembly; (iii) at least one third assembly located above the second assembly, where the third assembly is electrically connected to the first assembly by a plurality of second protruding structures located outside of the second assembly; and (iv) where a first portion of the third assembly and the plurality of second protruding structures form a bent structure substantially perpendicular to a second portion of the third assembly. | 06-12-2014 |
20140159219 | MULTI-COMPONENT CHIP PACKAGING STRUCTURE - Disclosed herein are various chip packaging structures and arrangements. In one embodiment, a multiple-component chip packaging structure can include: (i) a first component arranged on a bottom layer; (ii) at least one second component arranged on the first component, where the at least one the second component is electrically connected to the first component by a plurality of protruding structures; (iii) at least one third component on the at least one second component; (iv) at least one extension structure arranged on at least one side of the at least one third component, where the at least one extension structure is configured to lead out electric polarities of the at least one third component; and (v) a plurality of bonding wires that electrically connect the at least one extension structure to the first component. | 06-12-2014 |
20140159220 | Semiconductor Device and Method of Manufacture Thereof - A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip. | 06-12-2014 |
20140159221 | LEAD FRAME, METHOD FOR MANUFACTURING LEAD FRAME AND SEMICONDUCTOR DEVICE USING SAME - Provided is a lead frame by which a die pad can be easily exposed when the lead frame is used for a semiconductor device. The lead frame has a die pad with an upper surface on which a semiconductor element is mounted. The lead frame is used for the semiconductor device with the exposed surface of the die pad being exposed from a sealing resin. A downwardly-projecting first metal burr is formed along the peripheral portion of the exposed surface of the die pad and heads of the first metal burr are flat. | 06-12-2014 |
20140167236 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME - System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts. A masking layer can be formed on an upper surface of the lead frame for protection and shielding purposes. Routing layer and conductive lands may subsequently be formed by shaping the lead frame, along with bottom encapsulation. The masking layer may subsequently be removed for additional processing steps including connecting an integrated circuit die to the upper surface of the lead frame. | 06-19-2014 |
20140167237 | POWER MODULE PACKAGE - Disclosed herein is a power module package, including: a substrate; semiconductor chips mounted on one surface of the substrate; external connection terminals connected to one surface of the substrate; and a connecting member having one end contacting the semiconductor chips and the other end contacting the external connection terminals and electrically and mechanically connecting between the semiconductor chips and the external connection terminals. | 06-19-2014 |
20140167238 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 06-19-2014 |
20140167239 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a substrate including a metal layer, a first insulation layer formed on the metal layer, a first circuit pattern formed on the first insulation layer and including a first pad and a second pad spaced apart from the first pad, a second insulation layer formed on the first insulation layer to cover the first circuit pattern, and a second circuit pattern formed on the second insulation layer and including a third pad formed on a location corresponding to the first pad and a fourth pad spaced apart from the third pad; a semiconductor chip mounted on the second circuit pattern; one end being electrically connected to the semiconductor chip, and another end protruding from the outside, wherein the first pad and the third pad, and the second pad and the fourth pad have different polarities. | 06-19-2014 |
20140167240 | SEMICONDUCTOR DEVICE CARRIER AND SEMICONDUCTOR PACKAGE USING THE SAME - The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer. | 06-19-2014 |
20140175627 | LEAD FRAME HAVING A PERIMETER RECESS WITHIN PERIPHERY OF COMPONENT TERMINAL - Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal. | 06-26-2014 |
20140175628 | COPPER WIRE BONDING STRUCTURE IN SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode. A copper clip attaches on the Au plating layer of the second top electrode. A gold (Au) stud bump is formed on the Au plating layer of the first top electrode with a copper wire connected on the stud bump. The Au stud bump is thicker than a thickness of the Au plating layer and thinner than a thickness of the copper clip to avoid copper wire NSOP (non-stick on pad) problem due to Ni plating layer diffusion during the solder reflow process in the copper clip attachment. | 06-26-2014 |
20140175629 | APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING - To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad. | 06-26-2014 |
20140175630 | Semiconductor Package with Multiple Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 06-26-2014 |
20140183713 | DIE PACKAGE STRUCTURE - The die package structure includes a die, and the pads on one side of the active surface of the die. The connecting terminal is disposed on one side of the packaged substrate region and is passed through the packaged substrate region. The external connecting terminal is disposed on another side adjacent to the connecting terminal. The back surface of the packaged substrate region is fixed on the die by the adhesive layer, and the pad of the die is to be exposed. A conductive wire electrically connected the connecting terminal with the pads on the die. A packaged body encapsulated the packaged substrate region, the active surface of the die and the conductive wire, and the external connecting terminal is to be exposed. A conductive component is electrically connected with the connecting terminal and being exposed on the packaged body. | 07-03-2014 |
20140183714 | DIE PACKAGE STRUCTURE - A die packaged structure is provided, which includes a die having the pad disposed on one side of the active surface. A packaged substrate having a front surface and a back surface, and the connecting terminal disposed on one side of the packaged substrate region, and passed through the packaged substrate region. An opening is disposed between the connecting terminal and one side of the packaged substrate region. Then, the back surface of the packaged substrate is fixed on die by an adhesive layer, such that the pad is exposed on the opening of the packaged substrate region. A conductive wire is electrically connected the pad with the connecting terminal, and a packaged body is encapsulated the packaged substrate region, the die and the conductive wire, and the external connecting terminal is exposed on the packaged substrate region. A conductive component is arranged on the external connecting terminal. | 07-03-2014 |
20140183715 | SEMICONDUCTOR DEVICE - According to the present invention, a semiconductor device having superior electrical conductivity is provided. The semiconductor device of the present invention is provided with a base material, a semiconductor element, and an adhesive layer that adheres the base material and the semiconductor element while interposed there between. In the adhesive layer of the semiconductor device, a metal particle and an insulating particle are dispersed, and the metal particle has flaked shape or ellipsoidal/spherical shape. As the content percentage by volume of the metal particle in the adhesive layer is a and the content percentage by volume of the insulating particles in the adhesive layer is b, the content percentage (a+b) by volume of fillers in the adhesive layer is 0.20 or more and 0.50 or less and the content percentage a/(a+b) by volume of the metal particles in the fillers is 0.03 or more and 0.70 or less. | 07-03-2014 |
20140191380 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING - An integrated circuit (“IC”) device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger central body portion and at least one relatively smaller peripheral portion in electrical continuity with the central body portion. The peripheral portion(s) project laterally outwardly from the central body portion of the die pad. Lateral displacement of a portion(s) of an encapsulation layer overlying the peripheral portion(s) is resisted by abutting surfaces on the peripheral portion(s) and the encapsulation layer. | 07-10-2014 |
20140191381 | INTEGRATED CIRCUIT MODULE WITH DUAL LEADFRAME - An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die. | 07-10-2014 |
20140191382 | CIRCUIT SUBSTRATE, METHOD OF MANUFACTURING CIRCUIT SUBSTRATE, AND ELECTRONIC COMPONENT - A circuit substrate includes: a mounting region having an exposed surface that is planarized, and in which a predetermined chip is to be mounted; patterns provided in the mounting region, and including respective top faces that form a part of the exposed surface; and solder bumps provided on the respective patterns, and having substantially same shape as one another. | 07-10-2014 |
20140191383 | POWER DEVICE AND METHOD OF PACKAGING SAME - A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers. | 07-10-2014 |
20140191384 | PRE-ENCAPSULATED ETCHING-THEN-PLATING LEAD FRAME STRUCTURE WITH ISLAND AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film using photolithography, forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, performing an etching process on the top surface and the back surface of the metal substrate, removing the first photoresist film and the second photoresist film, placing the etched metal substrate in a mold, encapsulating the etched metal substrate using the mold; and performing a plating process on the encapsulated metal substrate. | 07-10-2014 |
20140197526 | SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. | 07-17-2014 |
20140197527 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%. | 07-17-2014 |
20140210061 | CHIP ARRANGEMENT AND CHIP PACKAGE - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion. | 07-31-2014 |
20140210062 | Leadframe-Based Semiconductor Package Having Terminals on Top and Bottom Surfaces - A semiconductor device ( | 07-31-2014 |
20140210063 | SEMICONDUCITIVE CATECHOL GROUP ENCAPSULANT ADHESION PROMOTER FOR A PACKAGED ELECTRONIC DEVICE - A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant. | 07-31-2014 |
20140210064 | WIRE BONDING METHOD AND STRUCTURE - An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires. | 07-31-2014 |
20140210065 | SEMICONDUCTOR PACKAGE - A semiconductor package having a metal frame includes a frame-shaped conductive member which has an opening portion, mounted on a substrate, and a semiconductor element disposed within the opening. A ring-shaped wiring pattern is provided on a portion of the substrate outwards from the opening portion of the conductive member. The electrostatic coupling capacity of the ring-shaped wiring pattern and the conductive member is not less than the electrostatic coupling capacity of a semiconductor metal wiring layer and the conductive member. The ring-shaped wiring pattern and the ground wiring of the semiconductor metal wiring layer are electrically connected. | 07-31-2014 |
20140217566 | DOUBLE-SIDED PACKAGE - Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die. | 08-07-2014 |
20140217567 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of the concave part. The front edge portion of the pillar electrode is exposed from the concave part of the resin, which makes it possible to suppress increase in the height of the pillar electrode and to form the pillar electrodes having fine patterns or a narrow pitch. | 08-07-2014 |
20140217568 | Semiconductor Package with Cantilever Leads - A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe. | 08-07-2014 |
20140231977 | SEMICONDUCTOR PACKAGES WITH LOW STAND-OFF INTERCONNECTIONS BETWEEN CHIPS - A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface of the first die. A surface of a second semiconductor die is bonded to the stud bumps. The first main surface of the first die is wire bonded to the first main surface of the support. The first and second dies, the stud bumps, the bond wire, and at least a portion of the first main surface of the support are encapsulated with a mold compound. | 08-21-2014 |
20140231978 | SEMICONDUCTOR PACKAGE WITH INNER AND OUTER LEADS - A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections. | 08-21-2014 |
20140239471 | IC PACKAGE WITH STAINLESS STEEL LEADFRAME - Various aspects of the disclosure are directed to integrated circuit (IC) die leadframe packages. In accordance with one or more embodiments, a stainless steel leadframe apparatus has a polymer-based layer that adheres to both stainless steel and IC die encapsulation, with the stainless steel conducting signals/data between respective surfaces for communicating with the packaged IC die. In some embodiments, the apparatus includes the IC die adhered to the polymer-based layer via an adhesive, wire bonds coupled to the stainless steel leadframe for passing the signals/data, and an encapsulation epoxy that encapsulates the IC die and wire bonds. | 08-28-2014 |
20140239472 | DUAL-FLAG STACKED DIE PACKAGE - In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags. | 08-28-2014 |
20140239473 | WIRE BONDING ASSEMBLY AND METHOD - A method of wire bonding a die to a lead frame comprising mounting the die on a die attachment pad portion of a leadframe and supporting the leadframe on a support plate having a vacuum hole therein filled with porous material. | 08-28-2014 |
20140246766 | Semiconductor Chip Package - The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements. | 09-04-2014 |
20140246767 | SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME - A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the down bond area from die attach material, which may occur during a die attach process. | 09-04-2014 |
20140252577 | CHIP CARRIER STRUCTURE, CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material. | 09-11-2014 |
20140252578 | BALANCED STRESS ASSEMBLY FOR SEMICONDUCTOR DEVICES - An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The material and thicknesses of the substrates and lead frames are selected so stress experienced by the electronic devices caused by changes in temperature of the assembly are balanced from the center of the assembly, thereby eliminating the need for balancing stresses at a substrate level by applying substantially matching metal layers to both sides of the substrates. | 09-11-2014 |
20140252579 | 3D-Packages and Methods for Forming the Same - A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate. | 09-11-2014 |
20140252580 | LEAD FRAME, SEMICONDUCTOR PACKAGE INCLUDING THE LEAD FRAME, AND METHOD OF MANUFACTURING THE LEAD FRAME - There is provided a lead frame including a plurality of plating layers formed on both an upper surface and a lower surface of a base material including a metal, wherein an upper outermost plating layer of an upper part of the lead frame is a silver plating layer including silver, and a lower outermost plating layer of a lower part of the lead frame is a gold plating layer including gold. | 09-11-2014 |
20140252581 | LEAD FRAME AND SUBSTRATE SEMICONDUCTOR PACKAGE - A semiconductor chip package includes a lead frame having a die paddle, leads surrounding the paddle and a central window through the paddle. A substrate has a base side and a superior side. A peripheral portion of the base side is secured to the paddle and a central portion of the base side is exposed through the central window. A semiconductor chip is secured to the superior side of the substrate. The semiconductor chip is electrically connected to the plurality of leads and the substrate. A mold compound covers at least portions of the lead frame, the substrate and the semiconductor chip. The chip package can be electrically connected to other devices or a circuit board by way of the leads and BGA pads of the substrate exposed in the central window. | 09-11-2014 |
20140252582 | LEAD FRAME AND SEMICONDUCTOR DEVICE - A lead frame of high quality which can endure direct bonding to a semiconductor element, and a semiconductor device of high reliability which utilizing the lead frame. A lead frame includes a plurality of connected units, each unit including a pair of lead portions arranged spaced apart and opposite from each other, for mounting a semiconductor element and electrically connecting to a pair of electrodes of the semiconductor element respectively. The lead portions respectively include an element mounting region arranged on a surface thereof to mount the semiconductor element, and a groove extending from opposing end surfaces of each of the pair of lead portions, in a direction away from the end surfaces and bending in a surrounding manner along outer periphery of the element mounting region. | 09-11-2014 |
20140264802 | Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof - A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body. | 09-18-2014 |
20140264803 | PACKAGE DEVICE INCLUDING AN OPENING IN A FLEXIBLE SUBSTRATE AND METHODS OF FORMING THE SAME - Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or simply cut through the flexible substrate to divide the flexible substrate into two parts. Connectors may be placed within the opening of the flexible substrate and connected to redistribution layers of the flexible substrate. Dies can be attached to the connectors and electrically connected to the connectors and to the redistribution layers of the flexible substrate. Structure supports may be placed at another side of the flexible substrate on the surface or within an opening. | 09-18-2014 |
20140264804 | STACK DIE PACKAGE - In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die. | 09-18-2014 |
20140264805 | Semiconductor Package And Fabrication Method Thereof - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 09-18-2014 |
20140264806 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 09-18-2014 |
20140264807 | SEMICONDUCTOR DEVICE - Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached and a second mount region to which a controlling semiconductor chip is fixedly attached are formed isolated from each other. A projecting area is formed in the first mount region, and the projecting area protrudes into the second mount region. The controlling semiconductor chip is fixedly attached to the top surfaces of the projecting area and the second mount region by use of an insulating adhesive sheet material. This structure prevents the short circuit between the two chips, and improves accuracy in temperature detection with the controlling semiconductor chip. | 09-18-2014 |
20140284779 | SEMICONDUCTOR DEVICE HAVING REINFORCED WIRE BONDS TO METAL TERMINALS - A method of assembling semiconductor devices includes connecting a bond wire between a bond pad on a top side surface of a semiconductor die having its bottom side surface attached to a package substrate and a bonded area within a metal terminal of the package substrate, where a bond is formed along a bonding interface between the bond wire and bonded area. After the connecting, a metal paste is applied including a plurality of metal particles and a binder over the bonded area. The metal paste is sintered to densify the plurality of metal particles to form reinforcement material including within a portion of the bonding interface for providing improved wirebond performance, such as increased pull strength. | 09-25-2014 |
20140284780 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device with improved reliability. A logic chip (first semiconductor chip) and a laminated body (second semiconductor chip) are stacked in that order over a wiring substrate. An alignment mark formed over the wiring substrate is aligned with an alignment mark formed on a front surface of the logic chip, whereby the logic chip is mounted over the wiring substrate. An alignment mark formed on a back surface of the logic chip is aligned with an alignment mark formed on a front surface of the laminated body, whereby the laminated body is mounted over the back surface of the logic chip LG. | 09-25-2014 |
20140284781 | SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - A first electrode of a first switching element is connected to a first electrode of a second switching element via a first lead frame. A second electrode of the first switching element is connected to an element of a snubber circuit via a second lead frame. A second electrode of the second switching element is connected to the element of the snubber circuit via a third lead frame. A first portion of the element of the snubber circuit is joined to a front face of the second lead frame and a second portion thereof is joined to a front face of the third lead frame. A resin portion has a slit formed to extend from an outer surface of the resin portion to an inside of a gap between opposed end faces of the second lead frame and the third lead frame. | 09-25-2014 |
20140284782 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device | 09-25-2014 |
20140291824 | Leadframe, Semiconductor Package Including a Leadframe and Method for Producing a Leadframe - A lead frame includes a die pad and a lead finger with an inner portion which is configured to be electrically connected to contact pads of a die and with an outer portion which has an attach portion. The attach portion is configured to be soldered to an external solder pad, wherein the attach portion has a width, a length and a thickness. An opening extends through the thickness of the attach portion. | 10-02-2014 |
20140291825 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device in the preferred embodiment includes: a lead frame comprising a die pad and an electrode terminal; and at least one semiconductor chip bonded to a surface of the die pad, wherein the lead frame excluding a bottom surface thereof and the semiconductor chip are sealed by a sealing resin, and an unevenness is introduced on a bonding interface between the surface of the die pad and the semiconductor chip. | 10-02-2014 |
20140291826 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device and a manufacturing method for a semiconductor device in which during QFP (quad flat package assembly) a wire passing over a bus bar and coupled to an inner lead is set at a loop height different from a second wire at a low loop height, and a third wire at a high loop height, and also mounted nearer a standard suspension lead than the second wire and the third wire. The loop height of the wire becomes gradually higher than the direction of resin flow in the resin sealing process so that wire sweep can be reduced and the reliability of the QFP assembly can be improved. | 10-02-2014 |
20140291827 | Lead Frame and Semiconductor Device - A lead frame includes an outer lead and a plating layer that covers a lower surface and side surfaces of the outer lead. The plating layer does not cover the upper surface of the outer lead. A frame base material is exposed from the plating layer at the upper surface of the outer lead. | 10-02-2014 |
20140291828 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor element having an electrode facing a first direction; a first lead having a conductive distal end surface facing the electrode, and a rising portion which is connected to the distal end surface to extend away from the electrode; a conductive bonding material bonding the electrode of the semiconductor element to the distal end surface of the first lead; and a sealing resin covering the semiconductor element, at least a portion of the first lead, and the conductive bonding material | 10-02-2014 |
20140306331 | CHIP AND CHIP ARRANGEMENT - Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body. | 10-16-2014 |
20140306332 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A packaged multi-output converter ( | 10-16-2014 |
20140306333 | CAVITY PACKAGE WITH DIE ATTACH PAD - A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer. | 10-16-2014 |
20140319664 | QUAD FLAT NO-LEAD (QFN) PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad. | 10-30-2014 |
20140319665 | Power Semiconductor Package - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 10-30-2014 |
20140319666 | LEAD FRAME AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THE SAME - The present invention provides a lead frame having excellent solder wettability and solderability, that is well-bonded to a copper wire, and manufactured with low cost, and a semiconductor package manufactured by using the same. The lead frame includes: a base material; a first metal layer formed on at least one surface of the base material, the first metal layer comprising nickel; a second metal layer formed on a surface of the first metal layer, the second metal layer comprising palladium; and a third metal layer formed on a surface of the second metal layer, the third metal layer comprising silver. | 10-30-2014 |
20140327123 | PACKAGED IC HAVING PRINTED DIELECTRIC ADHESIVE ON DIE PAD - A packaged integrated circuit (IC) includes a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto attached by a dielectric polymer material to the die pad. Bond wires are between the plurality of bond pads and the metal terminals of the leadframe. A mold material different from said dielectric polymer material provides encapsulation for the packaged IC. An area of the dielectric polymer material exceeds an area of the IC die. The dielectric polymer material forms a dielectric polymer/mold material interface with the mold material. | 11-06-2014 |
20140327124 | POWER TRANSISTOR WITH HEAT DISSIPATION AND METHOD THEREFORE - A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die. | 11-06-2014 |
20140332942 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip. | 11-13-2014 |
20140332943 | BARREL-PLATING QUAD FLAT NO-LEAD (QFN) PACKAGING STRUCTURES AND METHOD FOR MANUFACTURING THE SAME - A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming a first metal layer containing a plurality of inner leads; etching the substrate from the back surface of the substrate to form a plurality of I/O pads; filling sealant in the etched areas; attaching at least one die in a predetermined region on the top surface of the substrate; connecting the die and the inner leads using metal wires; sealing the die, the inner leads, and the metal wires with a molding compound; separating the resulting joint QFN components into individual QFN components; and forming a second metal layer on the back surface of the I/O pads. | 11-13-2014 |
20140332944 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device ( | 11-13-2014 |
20140346656 | Multilevel Leadframe - A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together. | 11-27-2014 |
20140353808 | Packaged Semiconductor Device - Disclosed is a packaged device, comprising a carrier comprising a first carrier contact, a first electrical component having a first top surface and a first bottom surface, the first electrical component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier, an embedded system comprising a second electrical component having a second top surface, an interconnect element, and a first connecting element, the embedded system having a system bottom surface, wherein the system bottom surface comprises a first system contact, wherein the second top surface comprises a first component contact, and wherein the first system contact is connected to the first component contact by the interconnect element and the first component contact of the second electrical component is connected to the first carrier contact by means of the first connecting element. | 12-04-2014 |
20140353809 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A technique capable of enhancing a reliability of a semiconductor device is provided. A semiconductor device has a die pad on which a semiconductor chip is mounted. The die pad is sealed with resin so that a lower surface located on an opposite side of an upper surface on which the semiconductor chip is mounted is exposed. Also, the die pad has a central part including a region in which the semiconductor chip is mounted and a peripheral edge part provided next to the central part in a planar view. In addition, a step surface formed so that a height of the peripheral edge part becomes higher than a height of the central part is provided at a boundary between the central part and the peripheral edge part. | 12-04-2014 |
20140361418 | A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area. | 12-11-2014 |
20140361419 | POWER CONTROL DEVICE AND PREPARATION METHOD THEREOF - A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon. | 12-11-2014 |
20140361420 | HYBRID PACKAGING MULTI-CHIP SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure. | 12-11-2014 |
20140361421 | LEAD FRAME BASED SEMICONDUCTOR DIE PACKAGE - A lead frame based semiconductor die package includes a lead frame having a die pad that supports a semiconductor die and lead fingers that surround the die and die pad. The die is electrically connected to the lead fingers with bond wires. The die and bond wires are covered with an encapsulant with ends of the lead fingers projecting out from the encapsulant. One set of the lead fingers are bent and project down and another set of the lead fingers are bent and project inwardly, and under a bottom surface of the encapsulant. The encapsulant includes a slot or groove for receiving the lead fingers of the second set. | 12-11-2014 |
20140361422 | SEMICONDUCTOR DEVICE - In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN. | 12-11-2014 |
20140361423 | Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die - A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure. | 12-11-2014 |
20140367838 | LEADFRAME WITH LEAD OF VARYING THICKNESS - A leadframe that includes a die attachment pad and a lead having a bondwire attach portion with a thickness less than 50% of the thickness of an adjacent portion of the lead. Also a method of forming a leadframe includes forming a lead having a bond wire attach portion with an original thickness and coining the bond wire attach portion to a thickness less than 50% of the original thickness. An integrated circuit package and a method of forming an integrated circuit package are also disclosed. | 12-18-2014 |
20140374892 | LEAD FRAME AND SEMICONDUCTOR DEVICE USING SAME - A lead frame for a semiconductor device has a die pad for supporting a semiconductor die and intermediate lead fingers extending from a periphery of the package towards the die pad, and each having a bonding end near the die pad. Outer lead fingers are located adjacent respective tie bars edges, each outer lead finger extending from the periphery of the package towards the die pad. Each outer lead finger has a transverse region coupling two spaced longitudinal regions. The two spaced longitudinal regions each have a bonding region near the die pad. A semiconductor die is attached to the die pad and bond wires electrically couple connection pads of the semiconductor die to the bonding regions of each outer lead finger. Only one of the bond wires is bonded to the bonding region of the second longitudinal region. | 12-25-2014 |
20140374893 | SEMICONDUCTOR PACKAGE - A semiconductor package, comprising: a package substrate including chip regions, a separation region between the chip regions, and an edge region around the chip and separation regions; semiconductor chips disposed on the chip regions of the package substrate; and signal patterns. The package substrate comprises an upper layer substantially adjacent to the semiconductor chips, a lower layer including interconnection structures disposed in the chip regions, and an intermediate layer between the upper and lower layers, the intermediate layer includes through holes disposed only outside of the separation region; and the signal patterns are in contact with the interconnection structures through the through holes. | 12-25-2014 |
20150008567 | USING AN INTEGRATED CIRCUIT DIE CONFIGURATION FOR PACKAGE HEIGHT REDUCTION - A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface. | 01-08-2015 |
20150008568 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor device includes: a resin molded member ( | 01-08-2015 |
20150008569 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a die pad, which includes an upper surface and a lower surface, the upper surface forming a rectangular shape in plan view; a plurality of support pins that support the die pad; a plurality of inner leads arranged around the die pad; a plurality of outer leads connected to each of the inner leads; a semiconductor chip which includes a main surface and a back surface and in which a plurality of electrode pads is formed in the main surface; a plurality of wires which electrically couple the electrode pads of the semiconductor chip to the inner leads respectively; and a sealing body that seals the support pins, the inner leads, the semiconductor chip, and the wires. A first support pin of the plurality of support pins is integrally formed together with the die pad. The first support pin is terminated inside the sealing body. | 01-08-2015 |
20150014833 | QUAD FLAT SEMICONDUCTOR DEVICE WITH ADDITIONAL CONTACTS - A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts. | 01-15-2015 |
20150014834 | HYBRID LEAD FRAME AND BALL GRID ARRAY PACKAGE - A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry. | 01-15-2015 |
20150014835 | SOLDER FLOW IMPEDING FEATURE ON A LEAD FRAME - One embodiment is directed towards a packaged chip including a lead frame. At least one chip is mounted on the lead frame. At least one edge the lead frame has a solder flow impeding feature located thereon. The solder flow impeding feature includes an integral portion of the lead frame that extends in a first projection outward at an edge of the lead frame and parallel to an external surface of the lead frame. An internal surface of the first projection is aligned with an internal surface of the main portion of the lead frame. The solder flow impeding feature also includes a second projection that extends from an external side of the first projection in a direction generally perpendicular to the first projection. | 01-15-2015 |
20150021751 | SEMICONDUCTOR DEVICE WITH PLATED PILLARS AND LEADS - A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead electrically coupled to the conductive pillar, a metal plating layer covering the conductive lead and conductive pillar, and an encapsulant material encapsulating the semiconductor die and at least a portion of the plating layer. The pillar, lead, and plating layer may comprise copper, for example. The plating layer may fill a gap between the pillar and the lead. A portion of the metal plating layer may, for example, comprise an external lead. The metal plating layer may cover a side surface of the pillar and a top surface, side surface, and at least a portion of a bottom surface of the lead. The metal plating layer may cover side and bottom surfaces of the pillar and top, side, and at least a portion of bottom surfaces of the conductive lead. | 01-22-2015 |
20150021752 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having excellent moisture resistance and high temperature storage properties. The semiconductor device includes a lead frame that has a die pad and an inner lead, as a substrate, a semiconductor element that is mounted on the die pad, an electrode pad that is provided in the semiconductor element, a copper wire that connects the inner lead provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. A region of the electrode pad disposed within a range of at least equal to or less than 3 μm from a junction surface with the copper wire in a depth direction includes a metal, which is less likely to be ionized than aluminum, as a main component, and a content of sulfur in the copper wire is equal to or more than 15 ppm and equal to or less than 100 ppm with respect to a total amount of the copper wire. | 01-22-2015 |
20150021753 | PACKAGING STRUCTURE OF A SEMICONDUCTOR DEVICE - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 01-22-2015 |
20150028463 | Integrated Passives Package, Semiconductor Module and Method of Manufacturing - An integrated passives package includes an encapsulation compound and a plurality of electrically conductive pads embedded in the encapsulation compound. Each of the pads has opposing first and second sides. The first side of the pads is uncovered by the encapsulation compound and forms array of external electrical connections at a first side of the package. The integrated passives package further includes a plurality of passive components embedded in the encapsulation compound. Each of the passive components has a first terminal attached to one of the pads and a second terminal attached to a different one the pads at the second side of the pads. Corresponding semiconductor modules and methods of manufacturing are also provided. | 01-29-2015 |
20150028464 | LEAD FRAME, ELECTRIC POWER CONVERTING DEVICE, SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - According to the disclosure, a lead frame is provided, which includes: a first island and a second island that are arranged side by side; an outer peripheral frame; first leads that extend in a second direction perpendicular to the first direction; second leads that extend in the second direction; a first coupling portion that couples the first leads to the frame; a second coupling portion that couples the second leads to the frame; an intermediate portion formed between the first and second coupling portions in the first direction such that it extends in the second direction to terminate before the space between the first and second islands; and a deformation restraining portion formed or provided in at least one of the first leads, the second leads, the first and the second coupling portions and configured to restrain deformations of the first and second leads during a molding process. | 01-29-2015 |
20150028465 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° C. for 16 hours in the atmosphere, a barrier layer containing any metal selected from palladium and platinum is farmed at a junction between the copper wire and the electrode pad. | 01-29-2015 |
20150028466 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in parallel in a predetermined direction, wherein each of the power units includes a plurality of semiconductor elements placed on a metal plate having predetermined gaps with each other. The semiconductor elements of each of the two power units include a near-sided semiconductor element that is closer to an inlet of the resin among the two semiconductor elements having the predetermined gap therebetween. A structure is positioned on a passage and downstream in a resin flow direction relative to a predetermined position that corresponds to end parts of the near-sided semiconductor elements. The structure is a joint to connect the two power units placed adjacent to each other in the predetermined direction, and to be integrally sealed with the resin, along with the power unit. | 01-29-2015 |
20150028467 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements. | 01-29-2015 |
20150041967 | Molded Semiconductor Package with Backside Die Metallization - A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame. | 02-12-2015 |
20150054145 | INTEGRATED CIRCUIT PACKAGE WITH DIE ATTACH PADDLE HAVING AT LEAST ONE RECESSED PORTION - An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die. | 02-26-2015 |
20150054146 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and which has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same as or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal component of the bonding wire, a rate of interdiffusion of the main metal component of the bonding wire and the main metal component of the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (Au) and aluminum (Al) at a junction of aluminum (Al) and gold (Au) under the post-curing temperature. | 02-26-2015 |
20150054147 | LEAD FRAME HAVING A PERIMETER RECESS WITHIN PERIPHERY OF COMPONENT TERMINAL - Embodiments described herein relate to a packaged circuit including a lead frame having at least one recess pattern on an internal surface thereof. The at least one recess pattern includes a perimeter recess that defines a perimeter around one or more raised surfaces. The packaged circuit also includes a component having one or more terminals. One of the terminals is mounted to the one or more raised surfaces such that the terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the terminal. The packaged circuit also includes component attach adhesive between the single terminal of the component and the one or more raised surfaces of the lead frame. | 02-26-2015 |
20150061096 | Semiconductor Package with Multi-Level Die Block - A semiconductor package includes a block having a first side, a second side opposite the first side and a recessed region extending from the second side toward the first side so that the block has a thinner part in the recessed region and a thicker part outside the recessed region. The semiconductor package further includes a first semiconductor die and a second semiconductor die each having opposing first and second sides. The first semiconductor die is disposed in the recessed region of the block and attached to the thinner part of the block at the first side of the first semiconductor die. The second semiconductor die is attached to the second side of the first semiconductor die at a first side of the second semiconductor die. | 03-05-2015 |
20150061097 | EDGE COUPLING OF SEMICONDUCTOR DIES - Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together. | 03-05-2015 |
20150061098 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a conductive portion having semiconductor elements provided on a substrate, a case housing the conductive portion, and a lead terminal integrated into the case to be directly connected to the semiconductor elements or an interconnection of the substrate. The lead terminal has a stress relief shape for reliving stress generated in the lead terminal. | 03-05-2015 |
20150061099 | DENSE-PITCH SMALL-PAD COPPER WIRE BONDED DOUBLE IC CHIP STACK PACKAGING PIECE AND PREPARATION METHOD THEREFOR - A dense-pitch small-pad copper wire bonded double IC chip stack package comprises a plastic package body, in which a lead frame carrier and a frame lead inner pin are arranged; the upper surface of the lead frame carrier is fixedly connected with a first IC chip; a second IC chip is stacked on the first IC chip; the upper surface of the first IC chip and the upper surface of the second IC chip are respectively provided with a plurality of pads which are arranged as two lines of pad groups in parallel; the two pad groups are respectively a first pad group and a second pad group; a metal ball is implanted on each pad; each metal ball is connected with a first copper bonding ball; and a third copper bonding wire is formed by looping and arching on a corresponding metal ball between the second IC chip and the first IC chip. The preparation process of the present invention comprises thinning, scribing, loading the chip, performing pressure welding, plastic packaging and post-curing, trimming, electroplating, printing, forming and separating, and packaging. The package and the preparation method of the invention avoid the hidden danger of open circuit of a plastic packaging punching wire caused by the crater on the pad, the short circuit of adjacent welding spots, and the easy damage of a previous wire. | 03-05-2015 |
20150061100 | Semiconductor Arrangement, Method for Producing a Number of Chip Assemblies, Method for Producing a Semiconductor Arrangement and Method for Operating a Semiconductor Arrangement - A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode. | 03-05-2015 |
20150061101 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer. | 03-05-2015 |
20150069591 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage. | 03-12-2015 |
20150069592 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND APPLICATION BOARD MOUNTED WITH SAME - In one embodiment, a semiconductor device includes a lead frame including an island portion and a terminal portion separated from the island portion. The device further includes a semiconductor chip mounted on the island portion and including an electrode. The device further includes an insulating layer disposed on the semiconductor chip and having an opening to expose at least a part of the electrode. The device further includes a connector covering the electrode exposed through the opening and electrically connecting the electrode and the terminal portion. | 03-12-2015 |
20150069593 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a semiconductor device includes a lead frame including a chip mounting portion and a lead portion separated from the chip mounting portion and having the same thickness as the chip mounting portion, a level of an upper face of the chip mounting portion being same as a level of an upper face of the lead portion. The device further includes a semiconductor chip mounted on the upper face of the chip mounting portion and electrically connected to the lead portion. The device further includes a molding resin which collectively seals up the lead frame and the semiconductor chip. The device further includes a metal film covering parts of rear faces of the chip mounting portion and the lead portion. | 03-12-2015 |
20150069594 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion. | 03-12-2015 |
20150069595 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 03-12-2015 |
20150076675 | LEADFRAME PACKAGE WITH WETTABLE SIDES AND METHOD OF MANUFACTURING SAME - Embodiments of the present disclosure are directed to leadframe packages with wettable sides and methods of manufacturing same. In one embodiment, the leads of the leadframe packages have recesses with a curved profile formed therein. The recesses are plated with a solder wettable layer of conductive material that enables solder to flow along the surface during surface mounting of the package to a board, such as a PCB. | 03-19-2015 |
20150076676 | POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD - A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto. | 03-19-2015 |
20150076677 | CTE MATCHED INTERPOSER AND METHOD OF MAKING - The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, <1:1, preferably 1:1 to 2:1. | 03-19-2015 |
20150084171 | NO-LEAD SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed. | 03-26-2015 |
20150084172 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND METHOD OF MANUFACTURE THEREOF - A system and method of manufacture of an integrated circuit packaging system includes: a leadframe having a side solderable lead with a half-etched lead portion and a lead top side; a mold body directly on the leadframe and the side solderable lead, the lead top side of the side solderable lead exposed from the mold body; a mold groove in the mold body and in a portion of the side solderable lead for exposing a lead protrusion of the side solderable lead on an upper perimeter side of the mold body; and the half-etched lead portion exposed from a lower perimeter side of the mold body. | 03-26-2015 |
20150084173 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device having a converter circuit, a brake circuit and an inverter circuit and manufacturable by a simplified manufacturing process. the semiconductor device has a plurality of die pads, IGBTs, diodes, freewheel diodes, an HVIC and LVICs mounted on the plurality of die pads, a plurality of leads, and an encapsulation resin body that covers these component parts. In a manufacturing process, a single-plate lead frame having the above-described plurality of die pads and leads connected together can be prepared. The semiconductor device may be manufactured by using this single-plate lead frame. | 03-26-2015 |
20150084174 | SEMICONDUCTOR DEVICE LEADFRAME - For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion. | 03-26-2015 |
20150084175 | SEMICONDUCTOR DEVICE LEADFRAME - For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion. | 03-26-2015 |
20150084176 | HIGH EFFICIENCY MODULE | 03-26-2015 |
20150084177 | LEAD FRAME FOR MOUNTING LED ELEMENTS, LEAD FRAME WITH RESIN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES, AND LEAD FRAME FOR MOUNTING SEMICONDUCTOR ELEMENTS - A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region. | 03-26-2015 |
20150091147 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a die pad, wherein a semiconductor die is mounted on the die pad; a plurality of leads comprising a power lead disposed along a peripheral edge of the die pad; at least one connecting bar connecting with the die pad; and a power bar disposed on one side of the connecting bar, wherein the power bar is integrally connected to the power lead. A capacitor is mounted between the power bar and the connecting bar. | 04-02-2015 |
20150097278 | SURFACE MOUNT SEMICONDUCTOR DEVICE WITH ADDITIONAL BOTTOM FACE CONTACTS - Assembling a surface mount semiconductor device includes providing a lead frame structure with peripheral leads and additional bottom face contacts integral with frame members. Outer portions of the bottom face contact members are interposed between inner portions of adjacent pairs of the peripheral leads. A package body is formed by encapsulating the lead frame structure in which the frame members are positioned outside a side edge surface. The peripheral leads and the bottom face contact members project between the side edge surface of the package body and the frame members. The frame members are cut and the peripheral leads and the bottom face contact members are separated and electrically isolated from each other. | 04-09-2015 |
20150097279 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead. | 04-09-2015 |
20150102476 | QUAD FLAT NO LEAD PACKAGE AND PRODUCTION METHOD THEREOF - The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved. | 04-16-2015 |
20150102477 | X-LINE ROUTING FOR DENSE MULTI-CHIP-PACKAGE INTERCONNECTS - X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective. | 04-16-2015 |
20150108626 | Multilevel Leadframe - A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together. | 04-23-2015 |
20150115425 | MULTI-CHIP STACKED PACKAGE AND METHOD FOR FORMING THE SAME - The present disclosure relates to a multi-chip stacked package and a method for forming the same. The package comprises a chip carrier and multiple levels of chips, with one or more chips being arranged in each level, wherein one or more levels of chips, except for the topmost chips, have conductive vias, a patterned conductor layer is arranged on a back surface of a lower one of two chips in two adjacent levels, conductive bumps are provided between two adjacent levels of chips, and the conductive vias of a lower chip are electrically coupled to an upper chip by means of the patterned conductor layer and the conductive bumps. In the present disclosure, electrical connections are redistributed by means of the patterned conductor layer, and are further used for coupling multiple levels of chips by means of the conductive bumps. The resultant chip has a reduced chip size and can be used for electrically coupling various levels of chips, which achieves flexible electrical connections. | 04-30-2015 |
20150115426 | PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR PACAKGE USING THE SAME - Provided are a printed circuit board which can be used as a substrate for a package, a method of manufacturing the printed circuit board, and a semiconductor package using the printed circuit board, the printed circuit board including: a first substrate having a first mounting area for mounting a package substrate and a second mounting area for mounting a semiconductor element; a single layer or multi-layered circuit pattern of the first substrate; and a post bump connected to the circuit pattern, provided on an external insulating layer of the first mounting area, and having a concave upper surface. | 04-30-2015 |
20150123253 | SEMICONDUCTOR DEVICE AND DIE BONDING STRUCTURE THEREOF - Provided are a semiconductor device and a bonding structure thereof, in which an inter-metal compound is not formed with a semiconductor die or a lead frame, thereby improving electrical and mechanical properties and wettability and suppressing conglomeration of a die bonding material. The semiconductor device includes a semiconductor die, a barrier layer formed on a surface of the semiconductor die, a first metal layer formed on the barrier layer, a central metal layer formed on the first metal layer, and a second metal layer formed on the central metal layer. Here, the first and second metal layers have a first melting temperature, and the central metal layer has a second melting temperature lower than the first melting temperature. | 05-07-2015 |
20150123254 | CHIP SCALE DIODE PACKAGE NO CONTANING OUTER LEAD PINS AND PROCESS FOR PORDUCING THE SAME - A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection. | 05-07-2015 |
20150123255 | METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, AND CHIP ARRANGEMENT - A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure. | 05-07-2015 |
20150130037 | Method of Electrically Isolating Shared Leads of a Lead Frame Strip - A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. A semiconductor die is attached to the die paddles. A molding compound covers the unit lead frames, including the semiconductor dies. Prior to testing or other processing of the lead frame strip, a gap is etched into a region of the leads which are shared by adjacent ones of the unit lead frames. The gap extends at least mostly through the shared leads. A partial cut is made in the molding compound around the periphery of the unit lead frames prior to the subsequent processing, including below the gap in the shared leads, to electrically isolate the leads of the unit lead frames. | 05-14-2015 |
20150130038 | SOLDER FLOW-IMPEDING PLUG ON A LEAD FRAME - Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material and is adhered to the two or more adjacent sections of the lead frame. The plug functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame. | 05-14-2015 |
20150137337 | SEMICONDUCTOR PACKAGE AND LEAD FRAME - A semiconductor package is disclosed, which includes: a die paddle portion; a plurality of conductive portions circumventing the die paddle portion; a power bus bar and a ground bus bar formed around the periphery of the die paddle portion; a semiconductor element attached to the die paddle portion and electrically connected to the conductive portions, the power bus bar, and the ground bus bar by a plurality of bonding wires; and an encapsulant encapsulating the semiconductor element and the bonding wires. The ground bus bar extends outward along the power bus bar and is mutually configured with the power bus bar so as to reduce the loop inductance and resistance of the power bus bar while in use. | 05-21-2015 |
20150137338 | SEMICONDUCTOR ASSEMBLY AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor assembly is characterized by the step of attaching a chip-on-interposer subassembly on a base carrier with the chip inserted into a through opening of the base carrier and the interposer laterally extending beyond the through opening. The base carrier provides a platform for the chip-on-interposer subassembly attachment, whereas the interposer provides primary fan-out routing for the chip. In the method, a buildup circuitry is electrically coupled to the interposer and an optional cover sheet or additional buildup circuitry can be provided on the chip. | 05-21-2015 |
20150145112 | Electronic Component - In an embodiment, an electronic component includes a housing, a die pad having a first surface and a second surface opposing the first surface, a first high voltage semiconductor device arranged on the first surface of the die pad, a further semiconductor device arranged on the second surface of the die pad and a conductive connection between the first high voltage semiconductor device and the further semiconductor device. The conductive connection is surrounded by the housing and includes a portion arranged adjacent the die pad. | 05-28-2015 |
20150294924 | COMBINED QFN AND QFP SEMICONDUCTOR PACKAGE - A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type. | 10-15-2015 |
20150294925 | QUAD FLAT NO-LEAD PACKAGE AND MANUFACTURING METHOD THEREOF - A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads. | 10-15-2015 |
20150294927 | Semiconductor Device and Production Method for Same - The present invention relates to a power module obtained by connecting the opposite sides of a chip with solder, and prevents the side surfaces of a base portion from becoming wet with solder, which would otherwise cause connection failures of the solder or chip displacement, and also prevents peeling of molding resin, which would otherwise break the chip or shorten the life of the solder. The base portion is integrally formed with one of lead frames, and the side surfaces of the base portion and the surface of the main body of the lead frame are roughened so as to have reduced solder wettability. Meanwhile, the solder connection surface of the base portion is not roughened so as to ensure the solder wettability. Accordingly, it is possible to reduce failures that may occur during solder connection and obtain a highly reliable power module. | 10-15-2015 |
20150294929 | SEMICONDUCTOR DIE PACKAGE AND METHOD OF ASSEMBLING SAME - A semiconductor die package is assembled from a lead frame having lead fingers with a bonding end adjacent a die flag, and an elongate region extending away from the die flag. A semiconductor die is mounted on the die flag and electrodes of the semiconductor die are electrically connected to the bonding ends with bond wires. Each elongate region is bent into an external connector lead with mounting feet. The elongate region of each of the lead fingers protrudes from a housing formed from a mold compound. The mold compound extends from the housing to provide insulated support fingers molded to the external connector leads. | 10-15-2015 |
20150303128 | Device Including Multiple Semiconductor Chips and Multiple Carriers - A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact. | 10-22-2015 |
20150303133 | FLAT NO-LEAD PACKAGE AND THE MANUFACTURING METHOD THEREOF - A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads disposed in the encapsulating material. The encapsulating material has a package bottom surface. The die pad has a plurality of die pad extensions extending from the edges thereof. The chip is mounted on the die pad. The first contact pads are disposed near the edges of the encapsulating material and electrically coupled to the chip. The second contact pads are located between the die pad and the first contact pads and electrically coupled to the chip. Each of the second contact pads have a second contact pad extension corresponding to one of the die pad extensions respectively. The bottom surfaces of the first contact pads, the second contact pads and the second contact pad extensions arc exposed on the package bottom surface, | 10-22-2015 |
20150303135 | Method for Fabricating a Semiconductor Package and Semiconductor Package - A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body. | 10-22-2015 |
20150311143 | LEAD FRAMES HAVING METAL TRACES WITH METAL STUBS - A lead frame has a trace embedded in an encapsulant and a plurality of stubs (i) embedded in the encapsulant and (ii) connected to and extending from the trace at different locations along the length of the trace. The stubs inhibit the formation of cracks that may otherwise form along the trace due to thermal or mechanical bending of the lead frame, especially cracks that tend to occur along the four linear edge traces located at the periphery of some conventional embedded lead frames. | 10-29-2015 |
20150318233 | DC-DC CONVERTER HAVING TERMINALS OF SEMICONDUCTOR CHIPS DIRECTLY ATTACHABLE TO CIRCUIT BOARD - A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound. | 11-05-2015 |
20150318247 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A resin electrode capacitor having resin electrodes is used as a chip capacitor mounted so as to bridge between two seating faces of a lead frame. According to this configuration, when stress due to a step difference between the seating faces or stress due to a pressure from mold resin during encapsulation is applied to the chip capacitor, it is the resin electrodes that peel off. Hence, breakage of an element base can be prevented, which can in turn forestall a failure of a semiconductor device. | 11-05-2015 |
20150325501 | Cantilevered Leadframe Support Structure for Magnetic Wireless Transfer Between Integrated Circuit Dies - A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers. | 11-12-2015 |
20150325504 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor element, a main lead on which the semiconductor element is disposed, and a resin package that covers the semiconductor element and the main lead. A notch that is recessed toward the center of the main lead in plan view as seen in the thickness direction of the semiconductor element is formed in the main lead. | 11-12-2015 |
20150325506 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead. | 11-12-2015 |
20150325549 | PACKAGE ON PACKAGE STRUCTURE WITH PILLAR BUMP PINS AND RELATED METHOD THEREOF - A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second package has a plurality of pads connected to the pillar bump pins, respectively. A method of forming a package on package (POP) structure includes at least the following steps: providing a first package with a plurality of pillar bump pins; providing a second package with a plurality of pads; and forming the POP structure by connecting the pillar bump pins to the pads. | 11-12-2015 |
20150332982 | METAL BASE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING METAL BASE SUBSTRATE - A metal base substrate of the present invention includes a copper plate made of copper, a metal layer that is formed on the copper plate and is made of a metal different from the copper, an insulating resin sheet that is formed by bonding a sheet made of an insulating resin onto the metal layer, and a circuit pattern formed on the insulating resin sheet. | 11-19-2015 |
20150332990 | PACKAGE - A package includes: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package; a die pad region surrounded with the lead frames in a plane view; a semiconductor chip mounted on the die pad region; a plurality of bonding pads disposed on the semiconductor chip; and a plurality of bonding wires configured to connect the lead frames and the bonding pads, respectively, wherein the bonding wires are respectively connected to front end portions of the lead frames by bonding with an angle ranging from 45 to 135 degrees with respect to a trace of front end portions of the lead frames in the plane view. | 11-19-2015 |
20150332996 | INTERPOSER AND METHOD OF FABRICATING THE SAME - The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically. | 11-19-2015 |
20150340307 | Molded chip package and method of manufacturing the same - A method of manufacturing a molded chip package is provided which comprises arranging an electronic chip on a supporting structure; forming an isolation layer at least on portions of the electronic chip; and molding an encapsulation which covers the electronic chip and the supporting structure at least partially by using a molding material comprising a matrix material and a conductive filler material. | 11-26-2015 |
20150348879 | SEMICONDUCTOR DEVICE WITH ENCAPSULATED LEAD FRAME CONTACT AREA AND RELATED METHODS - A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires, and leads. Each lead may extend through a respective lead opening and outwardly from the encapsulation material. | 12-03-2015 |
20150348880 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device | 12-03-2015 |
20150348889 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame includes a first segment having a first bottom plate, and a second segment having a second bottom plate. The first segment and the second segment are arranged side by side, the first bottom plate is spatially isolated from the second bottom plate, and the first bottom plate is thicker than the second bottom plate. The first semiconductor component is disposed on the first bottom plate, and the second semiconductor component is disposed on the second bottom plate. The second semiconductor component is thicker than the first semiconductor component. The first conductive member electrically connects the second semiconductor component to the first segment. | 12-03-2015 |
20150348891 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH LEAD FRAME MADE FROM TOP AND BOTTOM COMPONENTS AND RELATED DEVICES - A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC. | 12-03-2015 |
20150357264 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a die pad having an upper surface and a lower surface opposite to the upper surface, a semiconductor chip having a main surface and a back surface opposite to the main surface so that a plurality of electrode pads are formed on the main surface and being mounted on the die pad so that the back surface is opposite to the upper surface of the die pad, a plurality of leads arranged to be aligned on a side of the die pad, a first wire electrically connecting between a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads, and a second wire having a diameter thicker than a diameter of the first wire and electrically connecting between a second electrode pad among the plurality of electrode pads of the semiconductor chip. | 12-10-2015 |
20150357265 | SYSTEMS AND METHODS FOR LEAD FRAME LOCKING DESIGN FEATURES - Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle. | 12-10-2015 |
20150357267 | COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE - A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation. | 12-10-2015 |
20150357268 | POWER SEMICONDUCTOR DEVICE WITH SMALL CONTACT FOOTPRINT AND THE PREPARATION METHOD - A power semiconductor package with a small footprint and a preparation method thereof are disclosed. The first semiconductor chip and second semiconductor chip are attached on the front and back sides of a die paddle. Conductive pads are then attached on the electrodes at the top surfaces of the first and second semiconductor chips flowed by the formation of a plastic package body covering the die paddle, first and second semiconductor chips, the conductive pads, where a side surface of a conductive pad is exposed from a side surface of the plastic package body. | 12-10-2015 |
20150357289 | SEMICONDUCTOR DEVICE - A semiconductor device | 12-10-2015 |
20150380344 | RESIN SEALING TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LEAD FRAME - The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc. | 12-31-2015 |
20150380345 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger. | 12-31-2015 |
20150380376 | SURFACE FINISH FOR WIREBONDING - The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure. | 12-31-2015 |
20160005626 | EXPOSED DIE CLIP BOND POWER PACKAGE - In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions. | 01-07-2016 |
20160005678 | ELECTRONIC DEVICE COMPRISING AN IMPROVED LEAD FRAME - An electronic device includes a chip and a support element which supports the chip. Leads are provided to be electrically coupled to at least one terminal of the chip. A coupling element is mounted to a free region of the support element that is not occupied by the chip. The coupling element includes a conductive portion electrically connected to at least one lead and to the at least one terminal of the chip to obtain an electrical coupling. | 01-07-2016 |
20160005699 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar. | 01-07-2016 |
20160013120 | Lead Frame and Semiconductor Device | 01-14-2016 |
20160013162 | Substrate Interconnections having Different Sizes | 01-14-2016 |
20160020162 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group. | 01-21-2016 |
20160020182 | Wire Bond Mold Lock Method and Structure - A method and apparatus are described for fabricating a microchip structure ( | 01-21-2016 |
20160027720 | SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME - A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. | 01-28-2016 |
20160027722 | Stacked Synchronous Buck Converter Having Chip Embedded in Outside Recess of Leadframe - A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip. | 01-28-2016 |
20160035652 | Integrated Circuit Device With Wire Bond Connections - An integrated circuit assembly includes a die with a bond pad; a stud bump formed on the bond pad; and a ball bond formed on the stud bump. | 02-04-2016 |
20160035654 | Source Down Semiconductor Devices and Methods of Formation Thereof - A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer. | 02-04-2016 |
20160035655 | Semiconductor Package Having Etched Foil Capacitor Integrated Into Leadframe - A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal. | 02-04-2016 |
20160043020 | Semiconductor Packaging Structure And Forming Method Therefor - The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins. By adopting the present invention, a transverse area occupied by the package structure is decreased, the volume of the entire package structure is correspondingly decreased, and the integration level of the package structure is improved. The present invention further provides a forming method of the semiconductor package structure. | 02-11-2016 |
20160043021 | Dual Power Converter Package - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. | 02-11-2016 |
20160043022 | Power Converter Package Using Driver IC - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. | 02-11-2016 |
20160049318 | FLOATING MOLD TOOL FOR SEMICONDCUTOR PACKAGING - Tooling for molding a packaged semiconductor device includes a clamping plate, a cavity bar, and an attachment mechanism. The cavity bar has a mold half that has a mold cavity for molding the packaged semiconductor device. The mold half has teeth and a space between pairs of adjacent teeth. The teeth and the spaces support bending of leads of a lead frame of the packaged semiconductor device. The attachment mechanism affixes the cavity bar to the clamping plate and permits the cavity bar to slide relative to the clamping plate. This sliding of the cavity bar enables proper alignment with a mating cavity bar to reduce the likelihood of resin bleed. | 02-18-2016 |
20160049345 | LOW-STRESS DUAL UNDERFILL PACKAGING - The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed. | 02-18-2016 |
20160049357 | THIN PLASTIC LEADLESS PACKAGE WITH EXPOSED METAL DIE PADDLE - A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips. | 02-18-2016 |
20160049943 | SEMICONDUCTOR DEVICE AND METERING APPARATUS - A semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that generates a timing signal of a frequency according to a oscillation frequency of the oscillation circuit, and a frequency correction section that corrects a frequency of the timing signal based on temperature data; and a discrete device that includes at least one of a temperature sensing device that detects a peripheral temperature, that supplies the detected temperature as temperature data to the frequency correction section, and that is provided as a separate body to the semiconductor chip, or a capacitor that is electrically connected to both the oscillator and the oscillation circuit and that is provided as a separate body to the semiconductor chip, wherein the oscillator, the semiconductor chip and the discrete device are contained within a single package. | 02-18-2016 |
20160056092 | Leadframe and method of manufacturing the same - A hybrid leadframe is provided comprising a thin leadframe layer comprising a diepad and a structured region; and a metal layer being thicker than the thin leadframe layer and arranged on the diepad. | 02-25-2016 |
20160056093 | SOLDER FLOW-IMPEDING PLUG ON A LEAD FRAME - Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame. | 02-25-2016 |
20160056096 | POWER SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units. | 02-25-2016 |
20160056100 | Packages Having Integrated Devices and Methods of Forming Same - An embodiment device package includes a discrete device, a first connector on a bottom surface of the discrete device, and a second connector on a top surface of the discrete device. The first connector bonds the discrete device to a first package component, and the second connector bonds the discrete device to a second package component. | 02-25-2016 |
20160056125 | Hybrid Interconnect for Chip Stacking - Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a substrate, and adhering a first semiconductor device. Chip stacks are formed by providing a plurality of semiconductor devices and bonding them to the substrate and the first semiconductor device. At least one of the provided semiconductor devices is physically connected to both the substrate and the first semiconductor device it is stack on. Other semiconductor devices may stacked by forming conductive channels in the first semiconductor device, and placing the other semiconductor devices in physical contact with the first semiconductor device and the conductive channels. | 02-25-2016 |
20160064298 | Embedding additive particles in encapsulant of electronic device - An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and a plurality of capsules in the encapsulant, wherein the capsules comprise a core comprising an additive and comprise a shell, in particular a crackable shell, enclosing the core. | 03-03-2016 |
20160064310 | SEMICONDUCTOR PACKAGE HAVING ROUTING TRACES THEREIN - A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package. | 03-03-2016 |
20160064311 | LEAD FRAME CONSTRUCT FOR LEAD-FREE SOLDER CONNECTIONS - An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement. | 03-03-2016 |
20160064313 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin. | 03-03-2016 |
20160064361 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin. | 03-03-2016 |
20160071787 | SEMICONDUCTOR DEVICE ATTACHED TO AN EXPOSED PAD - The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings. | 03-10-2016 |
20160071788 | PACKAGED SEMICONDUCTOR DEVICES HAVING SOLDERABLE LEAD SURFACES EXPOSED BY GROOVES IN PACKAGE COMPOUND - A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces. | 03-10-2016 |
20160079146 | INTER-CONNECTION OF A LEAD FRAME WITH A PASSIVE COMPONENT INTERMEDIATE STRUCTURE - Consistent with an example embodiment, there is a package assembly structure. The structure comprises a lead frame having a topside surface and an opposite under-side surface; the lead frame includes a die attach paddle, wherein a die attach region is defined on the opposite under-side surface. Pad landings surround the die attach region. A plurality of locking pins are arranged at predetermined locations about the die attach paddle, on the top side surface. The plurality of locking pins may be formed integrally in the lead frame and project upward from the top side surface. | 03-17-2016 |
20160086876 | Electronic Component - In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer. | 03-24-2016 |
20160086877 | SEMICONDUCTOR DEVICE - The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction. | 03-24-2016 |
20160093525 | PRINTED INTERCONNECTS FOR SEMICONDUCTOR PACKAGES - A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads. | 03-31-2016 |
20160093556 | QUAD-FLAT NON-LEAD PACKAGE STRUCTURE AND METHOD OF PACKAGING THE SAME - A quad-flat non-lead package structure includes a film layer, a conducting layer, a die, an encapsulant, and a plurality of metal bumps. The film layer has a plurality of through holes. A pad of the conducting layer and conducting wirings are disposed at the film layer but are not connected to each other. The conducting wirings are disposed at the through holes, respectively. The die is fixedly disposed at the pad and electrically connected to the conducting wirings. The encapsulant covers the conducting layer and the die. The metal bumps are disposed in the through holes, respectively, each have one end electrically connected to a corresponding one of the conducting wirings, and each have the other end protruding from a corresponding one of the through holes. Accordingly, the quad-flat non-lead package structure features reduced likelihood of pin disconnection and enhanced adhesiveness required for surface-mount technology. | 03-31-2016 |
20160093557 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip. | 03-31-2016 |
20160093558 | PACKAGED DEVICE WITH ADDITIVE SUBSTRATE SURFACE MODIFICATION - A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains. | 03-31-2016 |
20160093560 | POWER SEMICONDUCTOR DEVICE AND THE PREPARATION METHOD - An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip. | 03-31-2016 |
20160093561 | SEMICONDUCTOR DEVICE - To reduce a mounting area while securing a mounting strength of a semiconductor device, a power transistor includes a chip mounting portion, a semiconductor chip, a plurality of leads, and a sealing body. An outer lead portion in each of the plurality of leads includes a first portion protruding from a second side surface of the sealing body in a first direction, a second portion extending in a second direction intersecting with the first direction, and a third portion extending in a third direction intersecting with the second direction. Furthermore, a length of the third portion in the third direction of the outer lead portion is shorter than a length of the first portion in the first direction. | 03-31-2016 |
20160093562 | NON-INSULATED POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A non-insulated power semiconductor module may include a housing, at least a pair of lead frames fixedly seated in the housing and having a plurality of power semiconductor chips mounted on surfaces thereof, and an insulation member disposed between the housing and the pair of lead frames. | 03-31-2016 |
20160099189 | Semiconductor Packages and Modules with Integrated Ferrite Material - A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The semiconductor package further includes a semiconductor die attached to the die paddle and having a plurality of pads including a gate pad, a plurality of electrical conductors connecting the pads to the leads, an encapsulant encasing the semiconductor die and a portion of the leads such that part of the leads are not covered by the encapsulant, and a ferrite material embedded in the encapsulant and surrounding a portion of the electrical conductor that connects the gate pad to the gate lead. A method of manufacturing the semiconductor package and a semiconductor module with integrated ferrite material are also provided. | 04-07-2016 |
20160099200 | ALUMINUM ALLOY LEAD FRAME FOR A SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS - Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry the die, and leads, which are designed to be electrically coupled to the die; and a package, of encapsulating material, which is designed to encapsulate the die and partially coming out of which are the leads. The lead frame has as constituent material an aluminum alloy comprising a percentage of silicon ranging between 1% and 1.5%. | 04-07-2016 |
20160104661 | A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET - The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area. | 04-14-2016 |
20160104662 | METHOD AND SYSTEM FOR EXTENDING DIE SIZE AND PACKAGED SEMICONDUCTOR DEVICES INCORPORATING THE SAME - A packaged semiconductor device includes a die flag and a plurality of lead frame fingers each having a proximate end spaced apart from the die flag. A first surface of a spacer mechanically and electrically couples to a first surface of the die flag, and a first surface of a die mechanically and electrically couples to a second surface of the spacer. At least one electrical connector electrically couples an electrical contact on a second surface of the die with a lead frame finger. A molding compound encapsulates the die, spacer, at least a portion of the at least one electrical connector, at least a portion of the die flag, and at least a portion of each lead frame finger. A width of the spacer along the second surface of the spacer is greater than a width of the die flag along the first surface of the die flag. | 04-14-2016 |
20160104664 | SEMICONDUCTOR DEVICE HAVING A PLURALITY OF CIRCUITS ARRANGED ON A SIDE OF A SEMICONDUCTOR CHIP - A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group. | 04-14-2016 |
20160111355 | Compact Single-Die Power Semiconductor Package - Disclosed is a power semiconductor package including a power transistor having a first power electrode and a gate electrode on its top surface and a second power electrode on its bottom surface. The second power electrode is configured for attachment to a partially etched leadframe segment, where the partially etched leadframe segment is attached to a substrate. A conductive clip is situated over the first power electrode and extends to the substrate in order to couple the first power electrode to the substrate without using a leadframe. | 04-21-2016 |
20160111356 | Compact Multi-Die Power Semiconductor Package - One disclosed implementation is a power semiconductor package including a sync transistor having a drain on its top surface and a source and a gate on its bottom surface. The source of the sync transistor is configured for attachment to a first partially etched leadframe segment and the gate of the sync transistor is configured for attachment to a second partially etched leadframe segment. A control transistor has a source and a gate on its top surface and a drain on its bottom surface. The drain of the control transistor is configured for attachment to a third partially etched leadframe segment. A first conductive clip extends to the substrate and is situated over the drain of the sync transistor and the source of the control transistor, the first conductive clip coupling the drain of the sync transistor and the source of the control transistor to the substrate without using a leadframe. | 04-21-2016 |
20160111357 | SEMICONDUCTOR DEVICE - A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided. | 04-21-2016 |
20160111403 | LEADFRAME-BASED SYSTEM-IN-PACKAGES HAVING SIDEWALL-MOUNTED SURFACE MOUNT DEVICES AND METHODS FOR THE PRODUCTION THEREOF - Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall. | 04-21-2016 |
20160111581 | PACKAGED SEMICONDUCTOR DEVICES AND RELATED METHODS - A packaged semiconductor device includes a substrate, a die, at least one electrical connector, a first mold compound formed of translucent material, and a second mold compound. A first face of the die is electrically and mechanically coupled to the substrate. The at least one electrical connector electrically couples at least one electrical contact on a second face of the die with at least one conductive path of the substrate. The first mold compound formed of a translucent material at least partially encapsulates the die and the at least one electrical connector. The second mold compound at least partially encapsulates the first mold compound and forms a window through which the first mold compound is exposed. In implementations the second mold compound is opaque and the first mold compound is transparent. In implementations the substrate includes a lead frame having a die flag and a plurality of lead frame fingers. | 04-21-2016 |
20160118365 | DIE ATTACHMENT FOR PACKAGED SEMICONDUCTOR DEVICE - A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects. | 04-28-2016 |
20160126162 | PACKAGE WITH MULTIPLE I/O SIDE-SOLDERABLE TERMINALS - Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. There are at least five I/O terminals wherein each of said terminals comprise a respective metal side pad wherein the respective metal side pad is disposed in a recess. A feature of this embodiment is that the each of the side pads is electroplated. The electroplated side pads accept solder and the solder menisci are contained by the recesses. | 05-05-2016 |
20160126163 | LEAD FRAME STRIP WITH MOLDING COMPOUND CHANNELS - A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads connected to the periphery structure and extending towards the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles, electrically connecting each of the semiconductor dies to the leads, and forming a liquefied molding compound on each of the unit lead frames. The liquefied molding compound is formed such that the liquefied molding compound encapsulates the semiconductor dies and flows into the molding compound channels thereby forming molding extensions that extend onto the periphery structures. | 05-05-2016 |
20160126165 | METHOD OF CONNECTING A SUBSTRATE AND CHIP ASSEMBLY - A method of connecting a substrate is provided, wherein the substrate may include a first main surface and a second main surface opposite the first main surface. The method may include forming at least one protrusion on the first main surface of the substrate, forming a fixing agent over the first main surface of the substrate and over the at least one protrusion; and arranging the substrate on a carrier. The at least one protrusion may contact a surface of the carrier and may be configured to keep the first main surface of the substrate at a distance to the contacted surface of the carrier corresponding to a height of the protrusion, thereby forming a space between the first main surface of the substrate and the carrier. During the arranging the substrate on the carrier, at least a part of the fixing agent formed over the at least one protrusion may be displaced into the space between the first main surface of the substrate and the carrier. | 05-05-2016 |
20160126228 | FAN-OUT WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures. | 05-05-2016 |
20160133547 | SEMICONDUCTOR DIE ARRANGEMENT - A semiconductor die arrangement comprising a first die including at least one semiconductor device; a second die including at least one semiconductor device; a lead frame associated with the first die and comprising one or more lead fingers, wherein the second die is mounted on one of the lead fingers and electrically connected to a further element by a bond wire. | 05-12-2016 |
20160133548 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire. | 05-12-2016 |
20160141224 | POWER MODULE AND FABRICATION METHOD FOR THE SAME - A power module includes: an insulating layer; a leadframe (metal layer) disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip, at least a part of the metal layer, and at least a part of the insulating layer, wherein the insulating layer includes a relatively-soft insulating layer disposed at a side of the leadframe and a relatively-hard insulating layer disposed at an opposite side of the leadframes. Accordingly, there can be provided the power module with improved cooling capability and improved reliability, and the fabrication method for such a power module. | 05-19-2016 |
20160141231 | POWER MODULE AND FABRICATION METHOD FOR THE SAME - A power module includes: an insulating layer; a leadframe disposed on the insulating layer; a semiconductor chip disposed on the leadframe; and a mold resin formed so as to cover the semiconductor chip and at least a part of the metal layer, wherein a groove into which a part of the insulating layer is inserted is formed on a surface of the leadframe facing the insulating layer. Accordingly, there can be provided the power module with improved reliability so that the insulating layer and the leadframe may be hardly deviated from each other even if external force is applied thereon; and a fabrication method for such a power module. | 05-19-2016 |
20160141233 | FIRST-PACKAGED AND LATER-ETCHED NORMAL CHIP THREE DIMENSION SYSTEM-IN-PACKAGE METAL CIRCUIT BOARD STRUCTURE AND PROCESSING METHOD THEREOF - The present invention relates to a first-packaged and later-etched normal chip three dimension-on-chip metal circuit board structure and a processing method for manufacturing the same, the structure includes: metal substrate frame ( | 05-19-2016 |
20160148859 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points. | 05-26-2016 |
20160148861 | FIRST-PACKAGED AND LATER-ETCHED THREE-DIMENSIONAL FLIP-CHIP SYSTEM-IN-PACKAGE STRUCTURE AND PROCESSING METHOD THEREFOR - A first-packaged and later-etched three-dimensional flip-chip system-in-package structure and a processing method thereof are provided. The package structure includes: a pad ( | 05-26-2016 |
20160148862 | SEMICONDUCTOR MODULE - A common connecting section for connection to terminals at the same potential in circuits is placed outside a mold section to allow a reduction in size of a semiconductor module | 05-26-2016 |
20160155689 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD | 06-02-2016 |
20160155690 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE | 06-02-2016 |
20160155695 | INTERPOSERS WITH CIRCUIT MODULES ENCAPSULATED BY MOLDABLE MATERIAL IN A CAVITY, AND METHODS OF FABRICATION | 06-02-2016 |
20160163622 | PACKAGING-BEFORE-ETCHING FLIP CHIP 3D SYSTEM-LEVEL METAL CIRCUIT BOARD STRUCTURE AND TECHNIQUE THEREOF - Provided are a packaging-before-etching flip chip 3D system-level metal circuit board structure and technique thereof. The metal circuit board structure comprises a metal substrate frame; the front face of the metal substrate frame is provided with pins; the front faces of the pins are provided with conductive posts; chips are installed in a flip manner between the pins via underfills; the peripheral areas of the pins, the conductive posts and the chip are encapsulated with molding compound, the top of the molding compound being parallel to the tops of the conductive posts; and the surfaces of the metal substrate frame, the pins and the conductive posts exposing out of the molding compounds are provided with an anti-oxidation layer, thus solving the problem of limited functionality and application of a traditional metal lead frame due to the fact that objects cannot be embedded therein. | 06-09-2016 |
20160163671 | INTEGRATED CIRCUIT PACKAGE WITH POWER PLATES - A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment. | 06-09-2016 |
20160172272 | INTEGRATED CIRCUIT (IC) PACKAGE WITH A SOLDER RECEIVING AREA AND ASSOCIATED METHODS | 06-16-2016 |
20160172273 | INTEGRATED CIRCUIT DEVICE WITH PLATING ON LEAD INTERCONNECTION POINT AND METHOD OF FORMING THE DEVICE | 06-16-2016 |
20160172276 | Bonding clip, carrier and method of manufacturing a bonding clip | 06-16-2016 |
20160172277 | LAND STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD THEREFOR | 06-16-2016 |
20160172282 | POST-MOLD FOR SEMICONDUCTOR PACKAGE HAVING EXPOSED TRACES | 06-16-2016 |
20160172318 | SEMICONDUCTOR DEVICES WITH IMPEDANCE MATCHING-CIRCUITS | 06-16-2016 |
20160181180 | PACKAGED SEMICONDUCTOR DEVICE HAVING ATTACHED CHIPS OVERHANGING THE ASSEMBLY PAD | 06-23-2016 |
20160181185 | SEMICONDUCTOR PACKAGE STRUCTURE | 06-23-2016 |
20160181186 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR | 06-23-2016 |
20160190044 | CHIP PACKAGE AND A WAFER LEVEL PACKAGE - Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for. | 06-30-2016 |
20160190046 | PROCESS FOR MANUFACTURING A PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A surface-mount electronic device includes a body of semiconductor material, and a lead frame that includes a plurality of contact terminals. The plurality of contact terminals is electrically connected to the semiconductor body. The contact terminals are formed of sintered material. | 06-30-2016 |
20160190047 | ELECTRONIC DEVICE HAVING A LEAD WITH SELECTIVELY MODIFIED ELECTRICAL PROPERTIES - A die package having a plurality of connection pads, a die substrate supporting a plurality of connection elements, a first lead having a first metal core with a first core diameter, and a dielectric layer surrounding the first metal core, the dielectric layer having a first dielectric thickness that varies along its length and/or the dielectric layer having an outer metal layer at least partially surrounding the dielectric layer, for selectively modifying the electrical characteristics of the lead. | 06-30-2016 |
20160190048 | STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR - A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. | 06-30-2016 |
20160190075 | HIGH FREQUENCY INTEGRATED CIRCUIT AND PACKAGING FOR SAME - An integrated circuit can include a group of bond pads alternating between bond pads configured to provide a return path and bond pads configured to provide a signal bond pad. For example, five bond pads can be arranged in a return-signal-return-signal-return arrangement. The integrated circuit can further be configured to receive or transmit high frequency signals. | 06-30-2016 |
20160197030 | INTEGRATED CIRCUIT (IC) PACKAGE WITH THICK DIE PAD, AND ASSOCIATED METHODS | 07-07-2016 |
20160204052 | PACKAGED SEMICONDUCTOR DEVICE HAVING LEADFRAME FEATURES PREVENTING DELAMINATION | 07-14-2016 |
20160254214 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | 09-01-2016 |
20160254216 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME | 09-01-2016 |
20160379916 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SIDEWALL RECESS AND RELATED DEVICES - A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material. | 12-29-2016 |
20160379921 | CIRCUIT BOARDS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME - A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5. | 12-29-2016 |
20170236772 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 08-17-2017 |
20170236775 | LEAD FRAME AND METHOD FOR MANUFACTURING THE SAME | 08-17-2017 |
20180025965 | WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method Therefor | 01-25-2018 |
20190148171 | Stacked Semiconductor Devices and Methods of Forming Same | 05-16-2019 |
20190148263 | CLIP FOR SEMICONDUCTOR PACKAGE | 05-16-2019 |
20190148270 | METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE HAVING ENHANCED WETTABLE FLANK AND STRUCTURE | 05-16-2019 |
20190148271 | LEADFRAME WITH LEAD PROTRUDING FROM THE PACKAGE | 05-16-2019 |
20190148272 | ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS | 05-16-2019 |