Class / Patent application number | Description | Number of patent applications / Date published |
257687000 | Housing or package filled with solid or liquid electrically insulating material | 46 |
20080224296 | Article and Panel Comprising Semiconductor Chips, Casting Mold and Methods of Producing the Same - A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer. | 09-18-2008 |
20090020864 | Wafer Level package Structure and Fabrication Methods - A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die. | 01-22-2009 |
20090032929 | SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP - Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate. | 02-05-2009 |
20090032930 | PACKAGING SUBSTRATE HAVING CHIP EMBEDDED THEREIN AND MANUFACTURING METHOD THEREOF - A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed. | 02-05-2009 |
20090039494 | Power semiconductor module with sealing device for sealing to a substrate carrier and method for manufacturing it - A power semiconductor module comprising a housing of a first plastic, at least one substrate carrier with a circuit constructed thereon and electric terminating elements extending therefrom. The housing includes attachment means for its permanent connection with the substrate carrier. The housing has a permanently elastic sealing device of a second plastic which is formed integrally with the housing and encircles and is directed towards a first inner main surface of the substrate carrier. A method for constructing such a module includes the steps of constructing a housing of a first mechanically stable plastic and a sealing device of a second permanently elastic plastic; disposing the at least one substrate carrier on the housing; and permanently connecting the housing to the substrate carrier. | 02-12-2009 |
20090045498 | Partitioning of electronic packages - Partitioning electronic sensor packages is provided. The electronic sensor package includes an electronic component, a sensor device, and electrical connections between the electronic component and the sensor device. A dam is written in the electronic sensor package to partition the package into two or more sections, where the sensor device is situated at least partially in one section and the electronic component is situated at least partially in another section. The partitioning of the dam allows the two sections to be filled with different fill materials. For example, the section with the sensor device can be filled with a soft gel-like material to provide some moisture protection to the sensor device without causing detrimental stresses to the sensor device, whilst the section with the electronic component can be filled with a highly moisture protective epoxy. | 02-19-2009 |
20090057865 | SANDWICHED ORGANIC LGA STRUCTURE - An LGA structure is provided having at least one semiconductor device over a substrate and a mechanical load apparatus over the semiconductor device. The structure includes a load-distributing material between the mechanical load apparatus and the substrate. Specifically, the load-distributing material is proximate a first side of the semiconductor device and a second side of the semiconductor device opposite the first side of the semiconductor device. Furthermore, the load-distributing material completely surrounds the semiconductor device and contacts the mechanical load apparatus, the substrate, and the semiconductor device. The load-distributing material can be thermally conductive and comprises an elastomer and/or a liquid. The load-distributing material comprises a LGA interposer adapted to connect the substrate to a PCB below the substrate and/or a second substrate. Moreover, the load-distributing material comprises compressible material layers and rigid material layers. The load-distributing material comprises a rigid material incased in a compressible material. | 03-05-2009 |
20090065923 | SEMICONDUCTOR PACKAGE WITH IMPROVED SIZE, RELIABILITY, WARPAGE PREVENTION, AND HEAD DISSIPATION AND METHOD FOR MANUFACTURING THE SAME - The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on the upper portion of the semiconductor package module, and a penetration electrode penetrates the semiconductor package. The penetration electrode is electrically connected to the circuit patterns. The described semiconductor package improves upon important characteristics such as size, reliability, warpage prevention, and heat dissipation. | 03-12-2009 |
20090096078 | Semiconductor device and method for manufacturing a semiconductor device - A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region. | 04-16-2009 |
20090261467 | Semiconductor device - A semiconductor device including a semiconductor chip having a plurality of electrodes on one surface thereof in a thickness direction, a resin layer overlapping the one chip surface to provide a rectangular mounting surface, a plurality of metal posts in the resin layer, where the metal posts are electrically connected to the electrodes, and solder terminals respectively connected to the metal posts. The resin layer has a groove formed therein at the mounting surface so as to surround an area on which the metal posts are provided. The semiconductor device is mounted on the mounting substrate with an underfill material filled in a space between the mounting surface and the mounting substrate. | 10-22-2009 |
20090267212 | Semiconductor Device - The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes. | 10-29-2009 |
20090267213 | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump - A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required. | 10-29-2009 |
20090273070 | Liquid Resin Composition for Electronic Components and Electronic Component Device - The invention relates to a liquid resin composition for electronic components which is used in sealing of electronic components, comprising a liquid epoxy resin, a curing agent containing a liquid aromatic amine, and an inorganic filler, and further comprising at least one member selected from a hardening accelerator, silicone polymer particles, and a nonionic surfactant. There is thereby provided a liquid resin composition for electronic components, which is excellent in fluidity in narrow gaps, is free of void generation, is excellent in adhesiveness and low-stress characteristic and is excellent in fillet formation, as well as an electronic component device having high reliability (moisture resistance, thermal shock resistance), which is sealed therewith. | 11-05-2009 |
20090273071 | IC CHIP MOUNTING PACKAGE AND PROCESS FOR MANUFACTURING THE SAME - In one embodiment of the present invention, an IC chip mounting package is arranged such that an IC chip and a film base member are connected via an interposer, and a section in which the IC chip, the film base member, and the interposer are connected is sealed with sealing resin. The sealing resin is provided by potting sealing resin around the interposer via a potting nozzle, or is provided by potting the sealing resin around the IC chip, that is, via a device hole. Moreover, the sealing resin has a coefficient of linear expansion of not more than 80 ppm/° C., a viscosity of not less than 0.05 Pa·s but not more than 0.25 Pa·s, and also includes filler having a particle size of not more than 1 μm. | 11-05-2009 |
20090302450 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided in which the heat dissipation characteristic of a flip-chip mounted semiconductor chip is improved. A semiconductor device is provided with a substrate, a semiconductor flip-chip mounted on the substrate, a sealing resin layer for sealing around the semiconductor flip-chip. A sealing resin layer for sealing the semiconductor chip is formed around the semiconductor chip. In this semiconductor device, the back surface of the semiconductor chip is exposed and is convex with respect to the upper surface of the sealing resin layer. | 12-10-2009 |
20090309208 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes: an insulating layer having an opening therethrough; a wiring pattern formed on the insulating layer; an external connection terminal provided on a portion of the wiring pattern which is exposed from the opening; a semiconductor element flip-chip-mounted on the wiring pattern through a connection portion; an underfill resin which is filled between the semiconductor element and the wiring pattern to cover the connection portion; and a sealing resin portion which seals the semiconductor element. | 12-17-2009 |
20100013076 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package includes a semiconductor chip having a top surface on which a conductive pad is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top and bottom surfaces to each other; a first insulating layer covering the top surface of the semiconductor chip and laterally extending to the outside of the semiconductor chip; a fillet member covering a boundary where the side surface of the semiconductor chip and the first insulating layer meet each other; and a molding layer covering the bottom surface of the semiconductor chip, the fillet member, and the first insulating layer. | 01-21-2010 |
20100052137 | ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICONDUCTOR DEVICE BY ENCAPSULATION OF THE BOND STRUCTURE - The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces by providing a fill material after the wire bonding process in order to encapsulate at least the sensitive metal surfaces and a portion of the bond wire. Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package or carrier substrate with a required degree of reliability based on a corresponding fill material for encapsulating at least the sensitive metal surfaces. | 03-04-2010 |
20100052138 | RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame. | 03-04-2010 |
20100052139 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR SEALING RESIN - There is provided a semiconductor device which has been improved in adhesion between leads and a sealing resin (molding resin), and thus does not undergo peeling therebetween, and has high reliability. | 03-04-2010 |
20100090328 | Power semiconductor module with a hermetically tight circuit arrangement and method for producing such a module - A power semiconductor module comprising a substrate, a circuit formed thereon and having a plurality of conductor tracks that are electrically insulated from one another and power semiconductor components arranged on the conductor tracks. The latter are connected in a circuit-conforming manner by a connection device, which has an alternating layer sequence of at least two electrically conductive layers with at least one electrically insulating layer between them. In this case, the substrate has a first sealing area, which uninterruptedly encloses the circuit. Furthermore, this sealing area is connected to an assigned second sealing area on a layer of the connection device by a connection layer. According to the invention, this power semiconductor module is produced by applying pressure to the substrate, to the power semiconductor components and to the connection device. | 04-15-2010 |
20100127374 | Multi-stack semiconductor package, semiconductor module and electronic signal processing system including thereof - Multi-stack semiconductor packages and application technologies are provided. The multi-stack semiconductor package may include stacked semiconductor packages which may include a topmost semiconductor package and a bottommost semiconductor package. Each of the unit semiconductor packages may include a substrate, a semiconductor chip formed on the substrate, a molding material filled around the semiconductor chip on the substrate, and an adhesive layer formed on the semiconductor chip and the molding material. The semiconductor chip and the substrate of a semiconductor package may each include conductive vias providing an electrical connection between the semiconductor packages. The substrate of the upper semiconductor package stacked in an upper portion may be directly adhered onto the adhesive layer of the lower semiconductor package stacked in a lower portion. | 05-27-2010 |
20100230797 | WARP-SUPPRESSED SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region. | 09-16-2010 |
20100314741 | INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package stacking system including: forming a base frame includes: providing a support panel, and forming a coupling pad, a mounting pad, a base frame trace, a discrete component pad, or a combination thereof on the support panel; fabricating a package substrate; coupling an integrated circuit die to the package substrate; mounting the base frame over the integrated circuit die and the package substrate; and removing the support panel from the base frame. | 12-16-2010 |
20100327421 | IC PACKAGE DESIGN WITH STRESS RELIEF FEATURE - A protective structure is provided on a substrate to which a semiconductor die is attached. The protective structure surrounds the die and reduces the thermo-mechanical stresses to which the die is subject. The die is protected against cracking, warping, and delamination. | 12-30-2010 |
20110024891 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY EDGE COATING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package. | 02-03-2011 |
20110147912 | METHODS AND APPARATUSES TO STIFFEN INTEGRATED CIRCUIT PACKAGE - A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate. | 06-23-2011 |
20110156234 | SELF REPAIRING IC PACKAGE DESIGN - An integrated circuit package comprises a molding compound covering a semiconductor die. A healing substance is on the surface of the semiconductor die at an interface of the molding compound and the semiconductor die. The healing compound comprises a catalyst and a plurality of microcapsules containing a sealing compound. If the molding compound becomes delaminated from the semiconductor die the microcapsules rupture and spill the sealing compound. When the sealing compound is spilled and contacts the catalyst the sealing compound and catalyst polymerize and fasten the molding compound to the semiconductor die. | 06-30-2011 |
20110169155 | SEMICONDUCTOR APPARATUS WITH LID BONDED ON WIRING BOARD AND METHOD OF MANUFACTURING THE SAME - A semiconductor apparatus includes: a wiring board; a lid; and gap filling resin. A semiconductor chip is mounted on the wiring board. The lid includes inlet portions for injecting resin. The semiconductor chip is covered with the lid on the wiring board. The gap filling resin bonds the wiring board and the lid inside the lid. | 07-14-2011 |
20110278713 | EMBEDDED COMPONENT SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME AND FABRICATION METHODS THEREOF - An embedded electronic component semiconductor package structure and a packaging process thereof are provided. By providing two or more preformed building blocks, the electronic component can be assembled to the joined building blocks to obtain the embedded component semiconductor package structure. | 11-17-2011 |
20120068326 | ANTI-TAMPER MICROCHIP PACKAGE BASED ON THERMAL NANOFLUIDS OR FLUIDS - A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling. | 03-22-2012 |
20120086113 | FLEXIBLE CIRCUITS AND METHODS FOR MAKING THE SAME - Embodiments of the invention relate to a method for creating a flexible circuit, including defining a cavity in a top surface of a substrate before disposing a semiconductor chip within the cavity, such that a backside of the chip is disposed beneath the top surface of the substrate and above a bottom surface of the cavity. The method also includes forming a flexible connecting layer on the top surface of the substrate and extending over the chip. Other embodiments relate to a flexible circuit including a substrate defining a cavity in a top surface thereof. The cavity has encapsulant and a chip disposed therein, wherein a frontside of the chip is substantially coplanar with the top surface of the substrate. A flexible connecting layer is disposed on the top surface of the substrate and is partially supported by the substrate. | 04-12-2012 |
20120139093 | IN-SITU FOAM MATERIAL AS INTEGRATED HEAT SPREADER (IHS) SEALANT - An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant. | 06-07-2012 |
20120319262 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a mountable assembly includes: forming an integrated circuit device having a non-horizontal device side, an active device side, and a passive device side, providing a first integrated circuit die having an active side, a passive side, and an internal interconnect on the active side, applying a die attach adhesive on the passive side, attaching the passive side to the passive device side with the die attach adhesive, and applying an underfill on the passive device side and the internal interconnect, the underfill having a non-horizontal underfill side coplanar with the non-horizontal device side; and mounting on a substrate the mountable assembly. | 12-20-2012 |
20120326291 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip. | 12-27-2012 |
20130049184 | ELECTRIC DEVICE AND PRODUCTION METHOD THEREFOR - An electronic device includes a support substrate | 02-28-2013 |
20130069215 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip, a buffer body, and a terminal lead. The first semiconductor chip includes a first electrode and a second electrode provided on a side opposite to the first electrode. The first semiconductor chip is configured to allow a current to flow between the first electrode and the second electrode. The buffer body includes a lower metal foil, a ceramic piece, and an upper metal foil. The lower metal foil is electrically connected to the second electrode. The ceramic piece is provided on the second electrode with the lower metal foil interposed. The upper metal foil is provided on a side of the ceramic piece opposite to the lower metal foil to be electrically connected to the lower metal foil. The terminal lead has one end provided on the upper metal foil and electrically connected to the upper metal foil. | 03-21-2013 |
20130069216 | BASE PLATE AND SEMICONDUCTOR DEVICE - According to one embodiment, the base plate includes first and a second faces that are opposed to each other; the second face has a contoured rear surface, and the first area is set in the center of the plate. There is a second area with via holes in the peripheral areas of the center part. Also, the thickness of the second area is less than the thickness of the first area. | 03-21-2013 |
20130277819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a housing made of a thermoplastic resin and having an internal space that is opened on one side and an inner wall portion that has an inner peripheral surface defining the internal space; and a core portion engaged in the internal space of the housing. The core portion includes a substrate, a semiconductor element mounted on the substrate, a wire electrically connecting the substrate and the semiconductor element, and a mold resin sealing the substrate, the semiconductor element and the wire. The core portion has a side surface provided with a convex portion that is in contact with the inner peripheral surface of the inner wall portion. Accordingly, a semiconductor device allowing a lengthened life and improved productivity, and a method of manufacturing the semiconductor device can be provided. | 10-24-2013 |
20140319669 | POWER MODULE - Provided is a power module. The power module includes a power semiconductor chip. The power module further includes a case that accommodates the power semiconductor chip. A silicone gel seals the power semiconductor chip within the case. The silicone gel including a heat-resistant silicone gel containing 20 to 100 mass ppm of a metal complex comprising a metal selected from a group consisting of iron and platinum. | 10-30-2014 |
20150008570 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole. | 01-08-2015 |
20150028468 | NON-LEADED TYPE SEMICONDUCTOR PACKAGE AND METHOD OF ASSEMBLING SAME - A no-lead type semiconductor package has a mold cap that forms a mold body. The corners of the mold body are reinforced with mold columns such that the corners have rounded protrusions and do not form 90° angles. The mold columns prevent the corner pads from peeling. | 01-29-2015 |
20150115428 | POWER SEMICONDUCTOR MODULE - A power semiconductor module available under environments of high temperature has enhanced heat resistance of silicone gel filled up in a case. A power semiconductor module comprises a power semiconductor element, an insulating substrate mounted with the power semiconductor element, a resin case containing the power semiconductor element and the insulating substrate, a silicone gel injected into the resin case, and a sheet composed of a silicone rubber or silicone resin, disposed between the resin case and the silicone gel within the resin case. | 04-30-2015 |
20150303178 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip package includes a semiconductor chip, a first chip, a first connection portion, a molding layer, a metal redistribution layer and a packaging layer. The semiconductor chip includes a first conductive pad and a second conductive pad disposed on an upper surface of the semiconductor chip. The first chip is disposed on the upper surface, and the first chip has at least a first chip conductive pad. The first connection portion directly electrically connects the first chip conductive pad and the first conductive pad. The molding layer covers the upper surface, the first chip and the first connection portion, and the molding layer is formed with an opening exposing a second conductive pad. The metal redistribution layer is disposed in the opening, electrically connected to the second conductive pad and extending to the molding layer. The packaging layer covers the metal redistribution layer and the molding layer. | 10-22-2015 |
20160071778 | Semiconductor Device and Manufacturing Method Thereof - It is possible to provide a semiconductor device which can be obtained at a high reliability by warping an insulating substrate stably into a convex shape while ensuring a close contact between a cooling member and the insulating substrate. The semiconductor device includes an insulating substrate, a semiconductor element disposed on a first surface of the insulating substrate, a case connected to the insulating substrate, and a resin filled inside the case. Assuming that the thickness of the insulating substrate is denoted by t1, the thickness of the resin is denoted by t2, the linear expansion coefficient of the insulating substrate is denoted by α1, and the linear expansion coefficient of the resin is denoted by α2, the relationship therebetween satisfies t2≧t1 and α2≧α1, and a second surface of the insulating substrate opposite to the first surface thereof is warped into a convex shape. | 03-10-2016 |
20160181175 | ELECTRONIC MODULE AND METHOD OF MANUFACTURING THE SAME | 06-23-2016 |