Entries |
Document | Title | Date |
20080211085 | Semiconductor package having insulating substrate - A semiconductor package having an insulating substrate includes a dielectric layer, a set of metal layers, a set of supporting elements, and an electronic component. The set of metal layers includes a first metal layer and a second metal layer respectively located on the upper surface and the lower surface of the dielectric layer. The set of supporting elements includes a first supporting element and a second supporting element respectively located on the first metal layer and the second metal layer. The electronic component is electrically connected with the first supporting element. The dielectric layer and the set of metal layers form an insulating substrate. Furthermore, a package resin is disposed on the second supporting element to package the dielectric layer, the set of metal layers, the first supporting element, and the electronic component into one piece and fasten it on to the second supporting element. | 09-04-2008 |
20080217763 | MICROELECTRONIC WORKPIECES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES USING SUCH WORKPIECES - Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating has a major outer surface at a second distance from the first side of the support member. The second distance is approximately the same as the first distance such that the outer surface of the protective coating is generally co-planar with the outer surface of the bond sites carried by the projection. In several embodiments, a microelectronic die can be coupled to the corresponding bond sites carried by the projection in a flip-chip configuration. | 09-11-2008 |
20080224302 | Semiconductor Module - A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip. | 09-18-2008 |
20080224303 | Power Semiconductor Module - A power semiconductor module with its thermal resistance and overall size reduced. Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering. Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing. Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders. The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader. | 09-18-2008 |
20080237837 | Integrated Circuit Arrangement - An integrated circuit arrangement including a nonplanar substrate on which an integrated circuit is formed on at least one side, wherein the side of the substrate a which has the integrated circuit is arranged on a carrier and the carrier is produced from a chemically resistant material. | 10-02-2008 |
20080258293 | SEMICONDUCTOR DEVICE PACKAGE TO IMPROVE FUNCTIONS OF HEAT SINK AND GROUND SHIELD - The present invention provides a package structure and a method for forming the same. The structure comprises a substrate with contact pads and through holes filled with conducting metals for performing heat dissipation and ground shielding A chip with bonding pads is attached on the contact pad by an adhesive with high thermal conductivity to achieve heat dissipation. A RDL is formed on the substrate and the chip to couple the bonding pad and the contact pad formed on the substrate. The structure of present invention can improve the thickness thereof, and the heat dissipation and ground shielding of the structure are enhanced. Furthermore, the structure can achieve package on package (PoP) structure. | 10-23-2008 |
20080315400 | MICROELECTROMECHANICAL SYSTEMS DESIGN FEATURE - A device for reducing the chance that a microelectromechanical systems (MEMS) device with moving parts will have those parts stick to a glass cover of the MEMS device, and a method for making the device. An example embodiment of the invention includes a MEMS device wafer, a substrate wafer, and a glass cover. The MEMS device wafer includes perforations corresponding to the location(s) of exposed glass on the cover. An example embodiment of a method of the invention includes applying metal layers to a glass cover, perforating a device wafer at locations corresponding to areas of exposed glass on the glass cover, mounting the device wafer to the substrate wafer, and anodically bonding the glass cover to the substrate wafer or to the device wafer. | 12-25-2008 |
20090001551 | NOVEL BUILD-UP-PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body. | 01-01-2009 |
20090032935 | Semiconductor device - Embodiments of a semiconductor device are disclosed. | 02-05-2009 |
20090057874 | SEMICONDUCTOR MODULE INCLUDING SEMICONDUCTOR CHIPS IN A PLASTIC HOUSING IN SEPARATE REGIONS - Semiconductor module comprising semiconductor chips in a plastic housing in separate regions and method for producing the same | 03-05-2009 |
20090102045 | Packaging substrate having capacitor embedded therein - A packaging substrate having capacitors embedded therein, comprising: two capacitor disposition layers, each respectively consisting of a high dielectric layer and two first circuit layers disposed on two opposite surfaces of the high dielectric layer, wherein each of the first circuit layers has a plurality of electrode plates and a plurality of circuits; an adhesive layer disposed between the capacitor disposition layers to adhere the capacitor disposition layers to form a core board structure, wherein spaces between the circuits of every first circuit layer are filled with the adhesive layer; and a plurality of conductive through holes penetrating the capacitor disposition layers and the adhesive layer, and electrically connecting the circuits of the capacitor disposition layers respectively; wherein, pairs of the electrode plates on the opposite surfaces of each of the capacitor disposition layers are parallel and correspond to each other to form capacitors. | 04-23-2009 |
20090115050 | Interposer And Semiconductor Device - An interposer and a semiconductor device including the interposer are provided, which can prevent thermal warpage of an insulative substrate thereof. The interposer is to be provided together with a semiconductor chip in a semiconductor device and, when the semiconductor device is mounted on a mount board, disposed between the semiconductor chip and the mount board. The interposer includes: an insulative substrate of an insulative resin; an island provided on one surface of the insulative substrate to be bonded to a rear surface of the semiconductor chip via a bonding agent; a thermal pad provided on the other surface of the insulative substrate opposite from the one surface in generally opposed relation to the island with the intervention of the insulative substrate; and a thermal via extending through the insulative substrate from the one surface to the other surface to connect the island to the thermal pad in a thermally conductive manner. | 05-07-2009 |
20090115051 | Electronic Circuit Package - An electronic circuit package has a thin-film circuit integrated with the ceramic substrate. The thin-film circuit includes at least two passive circuit elements joined by an integrated electrical interconnect. At least one active power electronic component mounted on the ceramic substrate and is electrically connected with the integrated thin-film circuit. | 05-07-2009 |
20090121341 | COMPONENT FOR SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF COMPONENT FOR SEMICONDUCTOR PACKAGE - A component for semiconductor package which has a protective insulating layer on at least one surface of a component body and exposes a conductive material of the component body to an opening part of the protective insulating layer is manufactured by a method including the steps of (a) forming a mask on at least one surface of the component body, (b) forming the protective insulating layer by filling an opening part of the mask with a protective insulating material by a molding method using a metal mold comprising a mold release film, and (c) removing the metal mold and removing the mask. A typical component is a lead frame or a substrate for semiconductor package. | 05-14-2009 |
20090146289 | THERMOSET POLYIMIDES FOR MICROELECTRONIC APPLICATIONS - Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications. | 06-11-2009 |
20090194867 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE ADHESIVE - An integrated circuit package system comprising: providing a substrate; forming a base assembled package over the substrate; forming a top package over the base assemble package; and applying a top package stacking material for stand-off or insulation to the base assembled package and the top package. | 08-06-2009 |
20090236730 | Die substrate with reinforcement structure - Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate. | 09-24-2009 |
20090289350 | SEMICONDUCTOR PACKAGE, SUBSTRATE, ELECTRONIC DEVICE USING SUCH SEMICONDUCTOR PACKAGE OR SUBSTRATE, AND METHOD FOR CORRECTING WARPING OF SEMICONDUCTOR PACKAGE - Disclosed is a semiconductor package wherein a semiconductor chip is mounted on one surface of a substrate. In this semiconductor package, an inflection point forming portion made of a material having a higher coefficient of thermal expansion than the substrate is formed in a part of the substrate surface on which the semiconductor chip is mounted. | 11-26-2009 |
20090302456 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a simple method for manufacturing a semiconductor device in which deterioration in characteristics due to electrostatic discharge is reduced, a plurality of element layers each having a semiconductor integrated circuit and an antenna are sealed between a first insulator and a second insulator; a layered structure having a first conductive layer formed on a surface of the first insulator, the first insulator, the element layers, the second insulator, and a second conductive layer formed on a surface of the second insulator is formed; and the first insulator and the second insulator are melted, whereby the layered structure is divided so as to include at least one of the semiconductor integrated circuits and one of the antennas. | 12-10-2009 |
20090321921 | EMBEDDED WIRING BOARD, SEMICONDUCTOR PACKAGE INCLUDING THE SAME AND METHOD OF FABRICATING THE SAME - Provided are an embedded wiring board and a method of manufacturing the same. The embedded wiring board includes: a printed circuit board (PCB) including a first surface and a second surface, the first surface having a concave portion; through electrodes penetrating the PCB; a semiconductor device group embedded in the concave portion of the PCB, the semiconductor device group including bonding pads exposed in a direction of the first surface of the PCB; bumps disposed on the bonding pads, exposed in the direction of the first surface of the PCB; and a film substrate including a first surface and a second surface, the first surface including connection electrode patterns that are electrically connected to the bumps and the through electrodes, the film substrate having penetrated openings. | 12-31-2009 |
20100013088 | METHOD FOR PACKAGING SEMICONDUCTORS AT A WAFER LEVEL - A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material. | 01-21-2010 |
20100072610 | Process for Precision Placement of Integrated Circuit Overcoat Material - The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration. | 03-25-2010 |
20100096745 | BONDED WAFER STRUCTURE AND METHOD OF FABRICATION - A method of packaging electronics comprises providing a first wafer and providing a second wafer. The method also comprises depositing a polymer material over a surface of the first wafer; and selectively removing a portion of the polymer from the first wafer to create a void in the polymer. The method also comprises placing the first wafer over the second wafer and in contact with the polymer; and curing the polymer to bond the first wafer to the second wafer. A bonded wafer structure is also described. | 04-22-2010 |
20100109151 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a semiconductor chip having a first electrode on one face; a circuit board having a second electrode on a mounting face; a warp suppressing layer to suppress a warp of at least the semiconductor chip; and a stress relaxing layer to relax stress arising between the semiconductor chip and the warp suppressing layer. The semiconductor chip is mounted on the circuit board so as to electrically connect the first electrode with the second electrode of the circuit board and to oppose the one face to the mounting face: the stress relaxing layer is provided on a back face of the one face in the semiconductor chip; the warp suppressing layer is laminated on the semiconductor chip via the stress relaxing layer; the stress relaxing layer has a spacer to maintain a predetermined gap between the semiconductor chip and the warp suppressing layer; the stress relaxing layer has a Young's modulus lower than that of the warp suppressing layer; and the stress relaxing layer and the warp suppressing layer have coefficients of linear expansion greater than that of the semiconductor chip. | 05-06-2010 |
20100117220 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor package includes at least: a workpiece at least one surface of which is equipped with a device; a wall portion provided along an outer circumference of the device and is spaced apart from the device; and a cover member that is arranged above the device so as to form a first space and is supported by the workpiece via the wall portion, in which the first space includes at least one second space that communicates with an external space. | 05-13-2010 |
20100148355 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING WAFER LEVEL CHIP SCALE PACKAGING - An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system. | 06-17-2010 |
20100193940 | Wafer level package and method of manufacturing the same - The present invention relates to a wafer level package and a method of manufacturing the same. The wafer level package includes a first substrate including a first region and second regions with grooves around the first region; a semiconductor device positioned in the first region; first sealing members positioned in the grooves; a second substrate including projection units corresponding to the second regions in order to form a cavity corresponding to the first region; and second sealing members which are positioned above the projection units and laminate the first and second substrates to each other by being bonded to the first sealing members, and can prevent the sealing members from flowing to any region except for the sealing regions. | 08-05-2010 |
20140027897 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion. | 01-30-2014 |
20140061890 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package may include a semiconductor chip mounted on a substrate, a molding part protecting the semiconductor chip and having a top surface at a substantially equal height to a top surface of the semiconductor chip, a heat exhausting part on the molding part and the semiconductor chip, and an adhesive part between the heat exhausting part and the molding part and between the heat exhausting part and the semiconductor chip. An interface between the heat exhausting part and the adhesive part has a concave-convex structure. | 03-06-2014 |
20150130044 | NOVEL MECHANISM FOR MEMS BUMP SIDE WALL ANGLE IMPROVEMENT - The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided. | 05-14-2015 |
20160043040 | INTEGRATED CIRCUIT STRESS RELEASING STRUCTURE - The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate. | 02-11-2016 |
20160126153 | PRINTED CIRCUIT BOARD AND ELECTRONIC EQUIPMENT - A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a surface of a printed wiring board. The surface of the package substrate and the surface of the printed wiring board face each other. The plurality of lands and another plurality of lands are bonded to each other with solder having a height of 30% or less of a diameter of a solder bonding portion at the corresponding land. A ratio of a solder bonded area of at least each of lands, among another plurality of the lands, of which distance value to a corresponding one of the lands is larger than an average distance value between the lands and another lands, to a solder bonded area of the corresponding one of the lands is 56% or more and 81% or less. | 05-05-2016 |