Class / Patent application number | Description | Number of patent applications / Date published |
257775000 | Varying width or thickness of conductor | 53 |
20080203580 | SEMICONDUCTOR CHIP AND SHIELDING STRUCTURE THEREOF - A semiconductor chip including a substrate, a metal interconnection structure and a circuit region is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring, wherein the guard ring comprises a plurality of individual segments, and the individual segments are individually and electrically coupled to the ground contacts. The circuit region disposed on the substrate. A projection of the dielectric ring on the substrate surface surrounds a projection of the circuit region on the substrate surface, and the projection of the guard ring on the substrate surface surrounds that of the dielectric ring and that of the circuit region on the substrate surface. | 08-28-2008 |
20080251933 | METAL INTERCONNECT STRUCTURE - A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction. | 10-16-2008 |
20080284042 | ANISOTROPICALLY CONDUCTIVE MEMBER AND METHOD OF MANUFACTURE - An anisotropically conductive member has an insulating base material, and conductive paths composed of a conductive material which pass in a mutually insulated state through the insulating base material in a thickness direction thereof and which are provided in such a way that a first end of each conductive path is exposed on a first side of the insulating base material and a second end of each conductive path is exposed on a second side of the insulating base material. The conductive paths have a density of at least 2 million paths/mm | 11-20-2008 |
20090051042 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate that has an integrated circuit; a plurality of electrodes that is formed on the semiconductor substrate, the plurality of the electrodes being electrically coupled to the integrated circuit; a passivation film that is formed on the semiconductor substrate, the passivation film having an opening on at least a part of one of the plurality of electrodes; a resin protrusion that is disposed on the passivation film; and a plurality of wiring lines that extend to a surface of the resin protrusion, each of the plurality of wiring lines extending from one of the plurality of the electrodes, a first portion of each of the plurality of wiring lines being positioned at an uppermost edge of the resin protrusion, a second portion of each of the plurality of wiring lines being positioned between one of the plurality of electrodes and the uppermost edge of the resin protrusion, a width of the first portion of each of the plurality of wiring lines being narrower than a width of at least a part of the second portion of each of the plurality of wiring lines. | 02-26-2009 |
20090261479 | METHODS FOR PITCH REDUCTION - An integrated circuit described herein includes a substrate and a plurality of lines overlying the substrate. The lines define a plurality of first trenches and a plurality of second trenches. The plurality of first trenches extend into the substrate a distance different than that of the plurality of second trenches. Adjacent pairs of lines are separated by a first trench in the plurality of first trenches, and each pair of lines comprises a first line and a second line defining a corresponding second trench in the plurality of second trenches. | 10-22-2009 |
20100059896 | Coplaner waveguide and fabrication method thereof - A coplanar waveguide includes a substrate, a signal line formed on the substrate, a pair of ground conductors formed on the substrate on mutually opposite sides of the signal line, a signal line insulating film disposed between the signal line and the substrate, and a ground conductor insulating film disposed between the pair of ground conductors and the substrate. No corresponding insulating film is present on the substrate between the signal line and the ground conductors. Even if a silicon substrate is used, the attenuation characteristics of the coplanar waveguide are comparable to the attenuation characteristics of coplanar waveguides formed on compound semiconductor substrates. | 03-11-2010 |
20100065971 | Laser assisted chemical vapor deposition for backside die marking and structures formed thereby - Methods of forming a microelectronic structure are described. Embodiments of those methods include forming an identification mark on a portion of a backside of an individual die of a wafer by utilizing laser assisted CVD, wherein the formation of the identification mark is localized to a focal spot of the laser. | 03-18-2010 |
20100109165 | SEMICONDUCTOR DEVICE - A semiconductor device having a GaAsFET and input and output matching circuits connected to the FET is provided. In the semiconductor device, a line, including a wire connection portion connected to the input or output matching circuit and a lead connection portion connected to an input or output lead which is connected to an external circuit, is formed in such a manner that a line width at the wire connection portion is wider than that at the lead connection portion. With the semiconductor device, the number of wires connecting the input or output matching circuits with the wire connection portion can be increased. | 05-06-2010 |
20100181685 | INTEGRATED CLOCK AND POWER DISTRIBUTION - An integrated clock and power distribution network in a semiconductor device includes assigning a first tile to a location on a placement grid corresponding to a top metal layer. An orientation is assigned to the first tile relative to the top metal layer placement grid. The first tile is placed on a representation corresponding to the top metal layer in accordance with the assignments. A second tile is assigned to a location on a placement grid corresponding to a top-1 metal layer. The orientation is assigned to the second tile relative to the top-1 metal layer placement grid. The second tile is placed on a representation corresponding to the top-1 metal layer in accordance with the assignments. The first and second tile are arranged as a full-dense-mesh distribution structure. The first tile includes an integrated clock and power distribution structure. The second tile includes a low impedance underpass structure. | 07-22-2010 |
20100308472 | SEMICONDUCTOR CHIP HAVING POWER SUPPLY LINE WITH MINIMIZED VOLTAGE DROP - Disclosed is a power supply line in which a voltage drop generated in a resistance component of a metal line which delivers a power voltage is minimized so that the level of the power supply voltage delivered to a semiconductor chip becomes constant in the entire area of the semiconductor chip. The semiconductor chip includes: at least two power supply pads to which a power voltage applied from an external unit of the semiconductor chip is supplied; power supply main metal lines connected to each of the power supply pads; power supply branch metal lines extended from each of the power supply main metal lines to deliver a power voltage to a circuit in the semiconductor chip; and at least an electrostatic discharge (ESD) improvement dummy pad, wherein the ESD improvement dummy pad is electrically connected to the corresponding power supply main metal line and the corresponding power supply branch metal line to minimize a voltage drop. | 12-09-2010 |
20100327458 | Semiconductor device - There is provided a semiconductor device including: a metal wiring line formed on a semiconductor substrate; an inside chamfer provided only at the inside of a bend in the metal wiring line, widening the wiring line width at the inside of the bend; and a protection film covering the metal wiring line. | 12-30-2010 |
20110062595 | PATTERN STRUCTURES IN SEMICONDUCTOR DEVICES - A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width that is larger than a width of the extending line. The pad includes a protruding portion extending from a lateral portion of the pad. The pattern structure may be formed by simplified processes and may be employed in various semiconductor devices requiring minute patterns and pads. | 03-17-2011 |
20110121464 | Semiconductor Device and Method of Forming Electrical Interconnect with Stress Relief Void - A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate. | 05-26-2011 |
20110156274 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device capable of suppressing degradation in connection reliability due to the decrease in thickness of a conductive adhesive caused by the movement of a connecting plate in a semiconductor device to which a power transistor is mounted. A step is provided in the thin part of the connecting plate connected to a lead post to lock the connecting plate by contacting the step to the tip of the lead post. Alternatively, a groove is provided in the thin part of the connecting plate to lock the connecting plate by connecting the lead post to only the part of the connecting plate on the tip side from the groove. | 06-30-2011 |
20110227232 | CRENULATED WIRING STRUCTURE AND METHOD FOR INTEGRATED CIRCUIT INTERCONNECTS - A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line. | 09-22-2011 |
20110254174 | Semiconductor device - A semiconductor device having a via chain circuit including a plurality of fine interconnections and an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the via chain circuit. One or more of the fine interconnections becomes wider gradually towards the connection to the extension interconnection. The extension interconnection is formed in a same layer as the one or more of the fine interconnections connected to the extension interconnection. The one or more of the fine interconnections connected to the extension interconnection is connected to the extension interconnections at a position where the fine interconnections become wider. | 10-20-2011 |
20110266698 | SEMICONDUCTOR DEVICE COMPRISING VARIABLE-SIZED CONTACT, METHOD OF FORMING SAME, AND APPARATUS COMPRISING SAME - A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed. | 11-03-2011 |
20120104630 | Methods for Pitch Reduction - An integrated circuit described herein includes a substrate and a plurality of lines overlying the substrate. The lines define a plurality of first trenches and a plurality of second trenches. The plurality of first trenches extend into the substrate a distance different than that of the plurality of second trenches. Adjacent pairs of lines are separated by a first trench in the plurality of first trenches, and each pair of lines comprises a first line and a second line defining a corresponding second trench in the plurality of second trenches. | 05-03-2012 |
20120112364 | WIRING STRUCTURE OF SEMICONDUCTOR DEVICE - A wiring structure may include a first wiring having a first width that extends in a first direction, and a second wiring intersecting the first wiring, the second wiring extending in a second direction and having a second width that is equal to or less than the first width. Furthermore, the first wiring may have a third width that is smaller than the first width and the second wiring may have a fourth width that is smaller than the second width. Portions of the first and second wirings having the third and fourth widths may extend from an intersecting region in which the first wiring and the second wiring intersect each other. | 05-10-2012 |
20120126426 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line. | 05-24-2012 |
20120211898 | SEMICONDUCTOR DEVICE - Certain embodiments provide a semiconductor device including a first line, a second line, and a sacrificial line. The second line is connected to the first line, and has a narrower linewidth than the first line. The sacrificial line is a wiring having its one end connected to the first line, and its another end as an open end. Further, the sacrificial line at least partially has a portion with a narrower linewidth than the second line. | 08-23-2012 |
20120241978 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a first insulating film formed above a semiconductor substrate and having a first relative dielectric constant; a second insulating film formed above the first insulating film and having a second relative dielectric constant greater than the first relative dielectric constant; a plurality of columnar plugs extending longitudinally through the first and the second insulating films having a first sidewall extending through the first insulating film and a second sidewall extending through the second insulating film, wherein the second sidewall is tapered; a third insulating film formed above the second insulating film and having a third relative dielectric constant less than the second relative dielectric constant of the second insulating film; trenches extending through the third insulating film and reaching an upper portion of the plugs; and an interconnect wiring comprising metal formed within the trenches and contacting the upper portion of the plugs. | 09-27-2012 |
20120299196 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead. | 11-29-2012 |
20130032951 | SEMICONDUCTOR DEVICE COMPRISING VARIABLE-SIZED CONTACT, METHOD OF FORMING SAME, AND APPARATUS COMPRISING SAME - A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed. | 02-07-2013 |
20130075934 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a first wiring provided in a first wiring layer along a first direction, a second wiring provided in a second wiring layer along a second direction orthogonal to the first direction, the second wiring intersecting with the first wiring at a first intersect portion, and a third wiring provided close to and along the second wiring in the second wiring layer, the third wiring intersecting with the first wiring at a second intersect portion, wherein a distance between the second wiring in the first intersection portion and the third wiring in the second intersection portion is narrower than a distance between the second wiring another than the first intersection portion and the third wiring another than the second intersection portion. | 03-28-2013 |
20130127068 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first interconnection including a first end, a second interconnection connected to the first interconnection and including a width being gradually wider towards the first end, a third interconnection and a fourth interconnection, the third interconnection and the fourth interconnection being arranged to sandwich the second interconnection. The first interconnection, the second interconnection, the third interconnection, and the fourth interconnection are each formed in a same layer and a width of the first interconnection is wider than a width of the second interconnection. | 05-23-2013 |
20130140712 | Array Substrate, LCD Device, and Method for Manufacturing Array Substrate - The invention discloses an array substrate, an LCD device, and a method for manufacturing the array substrate. The array substrate comprises scan line(s) and data line(s); the width of data line at the junction of the data line and the scan line is more than the width of the rest part of the data line. The invention can improve the final passed yield of LCD devices on the premise of not adding additional processes, and has the advantages of simple technology and low cost. | 06-06-2013 |
20130154114 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME - A semiconductor circuit pattern includes an angled conductive pattern having a line portion and a pad portion at an end of the line portion extending normal to the line portion on a first side of the line portion. The pad portion has a width greater than a width of the line portion. A spacing has a first portion adjacent the first side of the pad portion, and a second portion adjacent a second side of the pad portion opposite the first side. The first portion of the spacing has a width greater than the width of the second portion of the spacing. | 06-20-2013 |
20130161831 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed. | 06-27-2013 |
20130270716 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including conductive lines configured to include first lines extending generally in parallel in a first direction and second lines extending generally in parallel in a second direction to intersect the first direction from the respective ends of the first lines and each second line having a width wider than the first line, and dummy patterns formed between the second lines. | 10-17-2013 |
20140042641 | MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES - An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions. | 02-13-2014 |
20140042642 | CONDUCTIVE LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A conductive line of a semiconductor device includes a conductive layer disposed on a semiconductor substrate. A thickness of the conductive layer is substantially larger than 10000 angstrom (Å), and at least a side of the conductive layer has at least two different values of curvature. | 02-13-2014 |
20140054794 | MEMORY PROCESS AND MEMORY STRUCTURE MADE THEREBY - A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer. | 02-27-2014 |
20140131893 | METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY - Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer. | 05-15-2014 |
20140159252 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the semiconductor structure, a via structure penetrating the intermetallic insulating layer, and a second wire extending on the intermetallic insulating layer in a second direction at a predetermined angle with respect to the first direction, the second wire being connected to the first wire through the via structure and including first and second portions on each other, and a protruding portion protruding from at least one of the first and second portions, the protruding portion being at a boundary of the first and second portions. | 06-12-2014 |
20140167290 | METHODS OF FORMING FINE PATTERNS IN THE FABRICATION OF SEMICONDUCTOR DEVICES - In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region. | 06-19-2014 |
20140217612 | ELECTRONIC FUSE HAVING A DAMAGED REGION - An electronic fuse structure including an M | 08-07-2014 |
20140232013 | Backside Through Vias in a Bonded Structure - A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set. | 08-21-2014 |
20140264942 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140264943 | MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width. | 09-18-2014 |
20140319700 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a method of manufacturing a semiconductor device includes forming one or more first patterns and one or more second patterns adjacent to the first patterns on a substrate, each first pattern including a linear portion extending in a first direction, and each second pattern including first and second linear portions extending in the first direction and a connection portion connecting end portions of the first and second linear portions with each other. The method further includes forming a resist layer on the first and second patterns. The method further includes forming a resist opening in the resist layer so that at least a part of a contour line of the resist opening is a curved line and the curved line overlaps the second patterns. The method further includes dividing the second patterns into the first and second linear portions by etching using the resist layer. | 10-30-2014 |
20140367864 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A method for producing a semiconductor device includes: a process for forming a first conductor on a first interlayer insulating film provided on a semiconductor substrate, a process for forming in order a first stopper interlayer film, a second interlayer insulating film, a second stopper interlayer film, and a third interlayer insulating film on the first interlayer insulating film to cover the first conductor, a process for penetrating the third interlayer insulating film, the second stopper interlayer film, and the second interlayer insulating film, and forming a first contact hole having a first inner diameter on a position corresponding to the first conductor, a process for expanding the inner diameter of the first contact hole on the second interlayer insulating film to a second inner diameter larger than the first inner diameter, and a process for forming on the first stopper interlayer film a second contact hole. | 12-18-2014 |
20150014862 | SEMICONDUCTOR PACKAGES INCLUDING A METAL LAYER BETWEEN FIRST AND SECOND SEMICONDUCTOR CHIPS - Semiconductor packages are provided. A semiconductor package may include a wiring board and a first semiconductor chip on the wiring board. Moreover, the semiconductor package may include a metal layer on the first semiconductor chip and a second semiconductor chip on the metal layer. The metal layer may be between the first and second semiconductor chips. | 01-15-2015 |
20150021790 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first conductive line and a second conductive line including a first extension region in which the first conductive line and the second conductive line extend in a first direction, and a bend region in which the first conductive line and the second conductive line bend with respect to the first direction, a first dummy pattern and a second dummy pattern arranged on extension regions beyond the bend region of the first conductive line and the second conductive line, respectively, in the first direction, a first contact pad and a second contact pad formed beyond the bend region in the first direction, and connected to the first conductive line and the second conductive line, respectively. | 01-22-2015 |
20150054176 | Methods of Fabricating Semiconductor Devices and Devices Fabricated Thereby - Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided. | 02-26-2015 |
20150054177 | RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING - A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking. | 02-26-2015 |
20150091191 | Contact Pad for Semiconductor Devices - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region. | 04-02-2015 |
20150091192 | SEMICONDUCTOR DEVICE CONNECTED BY ANISOTROPIC CONDUCTIVE FILM - A semiconductor device connected by an anisotropic conductive film including a first insulation layer, a conductive layer, and a second insulation layer one above another, wherein the conductive layer has an expansion length of 20% or less in a width direction thereof, and the second insulation layer has an expansion length of 50% or more in a width direction thereof, the expansion length is calculated according to Equation 1, below, after glass substrates are placed on upper and lower sides of the anisotropic conductive film respectively, followed by compression at 110° C. to 200° C. for 3 to 7 seconds under a load of 1 MPa to 7 MPa per unit area of a sample, | 04-02-2015 |
20150303145 | BACK END OF LINE (BEOL) LOCAL OPTIMIZATION TO IMPROVE PRODUCT PERFORMANCE - The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit. | 10-22-2015 |
20150348909 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - Provided is a semiconductor device that occupies a small area, a highly integrated semiconductor device, or a semiconductor device with high productivity. To fabricate an integrated circuit, a first insulating film is formed over a p-channel transistor; a transistor including an oxide semiconductor is formed over the first insulating film; a second insulating film is formed over the transistor; an opening, that is, a contact hole part of a sidewall of which is formed of the oxide semiconductor of the transistor, is formed in the first insulating film and the second insulating film; and an electrode connecting the p-channel transistor and the transistor including an oxide semiconductor to each other is formed. | 12-03-2015 |
20150364420 | INTERCONNECT STRUCTURE WITH FOOTING REGION - In some embodiments, an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers. | 12-17-2015 |
20160079158 | Contact Pad for Semiconductor Devices - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line. | 03-17-2016 |
20160099247 | SEMICONDUCTOR DEVICES WITH CAPACITORS - A semiconductor device includes bottom electrodes two-dimensionally arranged on a substrate and transistors connected to the bottom electrodes, respectively. Each of the bottom electrodes may include first side surfaces facing each other in a first direction and second side surfaces facing each other in a second direction crossing the first direction. At least one of the first and second side surfaces may have a concave shape, when viewed in a plan view. | 04-07-2016 |