Entries |
Document | Title | Date |
20090002035 | COMPARATOR CIRCUIT - A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage. | 01-01-2009 |
20090128196 | Data Holding Circuit - A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element. | 05-21-2009 |
20090206885 | TRACK AND HOLD CIRCUIT - A track and hold circuit ( | 08-20-2009 |
20090284285 | SWITCHED-CAPACITOR DECIMATOR - A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading. | 11-19-2009 |
20100271076 | PRECISION SAMPLING CIRCUIT - A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input. | 10-28-2010 |
20110043256 | SAMPLING FILTER USING MULTIPLE CLOCKS - Methods and devices for forming a series of samples of a filtered version of an input signal. Multiple tap current cells each generate a tap current from the signal. Multiple distribution means couple the tap current cells with multiple integrating means. The distribution means is controlled by a first clock signal. The multiple integrating means integrate tap currents that they receive and these integrating means form the samples. The tap currents generated are each sent to each integrating means in a predetermined sequence according to the first clock signal. The integrating means each use integrating and sampling phases controlled by a second clock signal. During the integrating phase an integrating means receives tap currents in sequence, while during the rest phase, no tap currents are received and the contents of the circuit are sampled and the integrator means is reset. | 02-24-2011 |
20110089978 | Sampling Device And Circuit Having A Single Voltage Supply - In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage. | 04-21-2011 |
20110210763 | COMMON-MODE INSENSITIVE SAMPLER - An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi. | 09-01-2011 |
20110254592 | SAMPLING CIRCUIT AND IMAGE SIGNAL AMPLIFYING CIRCUIT EACH INCLUDING FEEDBACK CLAMP BLOCK AND IMAGE SENSOR INCLUDING THE IMAGE SIGNAL AMPLIFYING CIRCUIT - A sampling circuit samples an input signal by using at least one switch, at least one capacitor, an amplifier, and a clamp block connected between an output terminal and a negative input terminal of the amplifier. The clamp block prevents a difference between a voltage level of the output terminal of the amplifier and a voltage level of the negative input terminal of the amplifier during sampling from exceeding a maximum voltage difference. | 10-20-2011 |
20120081153 | QUANTIZING SAMPLED INPUTS USING FIXED FREQUENCY ANALOG TO DIGITAL CONVERSIONS THROUGH INTERPOLATION - A system and methods for synchronizing quantized sampled data in a monitoring device. A variable frequency output signal is coupled to an analog to digital converter. A fixed frequency clock is coupled to the analog to digital converter. The analog to digital converter samples the output signal at a fixed frequency to produce high speed samples. A group of initial high speed samples is stored from the analog to digital converter over a fixed window of time. The group of initial high speed samples is interpolated to produce a group of fewer low speed samples from the initial group of high speed samples over the fixed window of time. The group of low speed samples is stored as a representation of the variable frequency output signal. | 04-05-2012 |
20130076402 | TECHNIQUES FOR REDUCING CORRELATED ERRORS IN MULTI-CHANNEL SAMPLING SYSTEMS - Techniques to reduce correlated errors in a multi-channel sampling system. A plurality of clock signals may be generated from a master clock signal, each with edges offset from each other. The offset clock signals may be distributed to a plurality of sampling devices. Each sampling device may capture a respective input signal according to its offset clock. In this manner, the sampling units may sample their inputs signals over a distributed window of time rather than sampling in response to a common clock edge. By distributing the switching operations performed by the sampling units, noise effects are likely to be reduced. | 03-28-2013 |
20130099828 | DIRECT SAMPLING CIRCUIT - Provided is a direct sampling circuit in which signal mixing between systems is avoided, even when signal systems in which time sharing is integrated are used together by time sharing. History capacitors ( | 04-25-2013 |
20130169314 | METHODS AND CIRCUITS FOR ADJUSTING PARAMETERS OF A TRANSCEIVER - Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold. | 07-04-2013 |
20130187682 | SUB-NYQUIST SAMPLING OF SHORT PULSES - A method for signal processing includes accepting an analog signal, which consists of a sequence of pulses ( | 07-25-2013 |
20140118030 | SAMPLING CIRCUIT AND SAMPLING METHOD - A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal. | 05-01-2014 |
20140184273 | Energy-Efficient Time-Stampless Adaptive Nonuniform Sampling - Described herein is a sampling system and related sampling scheme. The system and sampling scheme is based upon a framework for adaptive non-uniform sampling schemes. In the system and schemes described herein, time intervals between samples can be computed by using a function of previously taken samples. Therefore, keeping sampling times (time-stamps), except initialization times, is not necessary. One aim of this sampling framework is to provide a balance between reconstruction distortion and average sampling rate. The function by which sampling time intervals can be computed is called the sampling function. The sampling scheme described herein can be applied appropriately on different signal models such as deterministic or stochastic, and continuous or discrete signals. For each different signal model, sampling functions can be derived. | 07-03-2014 |
20140266316 | METHODS OF AND APPARATUS FOR DETERMINING PARTICLE INCLUSION AND SIZE IN MOLTEN METAL - Methods and apparatus for measuring the cleanliness of molten metal. Direct current is passed through molten metal advancing through a passage. A voltage signal is analyzed for the presence of solid generally non-metallic inclusions in the metal. A method includes sampling digital data of the voltage signal to generate data samples; updating a delayed running average of the data samples to establish a baseline for identifying sudden changes in amplitude of the data samples; determining a threshold by adding a prescribed value to the baseline; identifying a possible inclusion when a significant number of data samples exceeds the threshold; storing a maximum count as the data samples using peak detection until a prescribed number of the data samples fall below the threshold; and comparing a parameter of the possible inclusion with a lookup table to categorize the possible inclusion as either (i) an actual inclusion or (ii) noise. | 09-18-2014 |