Class / Patent application number | Description | Number of patent applications / Date published |
327174000 | Pulse broadening | 7 |
20090212836 | FRAME PULSE SIGNAL LATCH CIRCUIT AND PHASE ADJUSTMENT METHOD - A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLKâ²; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit. | 08-27-2009 |
20110006823 | SIGNAL DELAY CIRCUIT, CLOCK TRANSFER CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal. | 01-13-2011 |
20110204947 | METHOD AND APPARATUS FOR ADAPTIVELY MODIFYING A PULSE WIDTH OF A PULSE WIDTH MODULATED OUTPUT - Systems, methods, and apparatus for improving steady state operation of a pulse width modulator during transient and soft start events are described herein. An apparatus can include a phase component configured to adaptively modify a pulse width of a first pulse width modulated (PWM) output signal based on a pulse width of a PWM input signal. Further, the apparatus can include a power stage component configured to source at least one of a voltage or a current to a load based on the first PWM output signal. In one example, the phase component can be configured to linearly extend the pulse width of the first PWM output signal based on the pulse width of the PWM input signal. In another example, the phase component can be configured to adaptively modify the pulse width of the first PWM output signal based on a predetermined maximum pulse width. | 08-25-2011 |
20120169391 | DUTY CYCLE CORRECTOR AND DUTY CYCLE CORRECTION METHOD - The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay. The duty cycle corrector may comprise a duty cycle detector for generating a control signal as a function of the duty cycle of the output clock signal, and a feedback path for delivering the control signal to the pulse stretching stage so as to increase the controlled delay when the duty cycle is less than the desired duty cycle and to decrease the controlled delay when the duty cycle is greater than the desired duty cycle. The invention also relates to a method of generating from an input clock signal an output clock signal having a desired duty cycle. | 07-05-2012 |
20130141148 | PULSE STRETCHING CIRCUIT AND METHOD - A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal. | 06-06-2013 |
20150303905 | Slew Based Process and Bias Monitors and Related Methods - An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse. | 10-22-2015 |
20150349754 | PULSE STRETCHING CIRCUIT AND METHOD - A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal. | 12-03-2015 |