Entries |
Document | Title | Date |
20080197906 | Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling - A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal. | 08-21-2008 |
20080197907 | DRIVER AMPLIFIER CIRCUIT - A driver amplifier circuit is provided which includes a voltage level shifting circuit and an Op-Amp. A positive power supply terminal and a negative power supply terminal of the Op-Amp receive a first reference voltage and a second reference voltage outputted from the voltage level shifting circuit, causing a DC voltage level of an output signal to be equal to 0V. Meanwhile, the absolute value of a voltage difference between the first reference voltage and the second reference voltage is equal to V | 08-21-2008 |
20080204109 | High-performance level shifter - A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching. | 08-28-2008 |
20080204110 | LEVEL SHIFT CIRCUIT - A level shift circuit for converting a first signal level into a second signal level, includes a load circuit connected to the second power supply voltage, a first high voltage-resistant transistor in which a drain is connected to the load circuit, and a predetermined constant voltage is applied to a gate, a source voltage control circuit controls a voltage level of the source of the first high voltage-resistant transistor in accordance with an input signal at the first signal level, and has a second low voltage-resistant transistor, and an output terminal which is connected between the drain of the first high voltage-resistant transistor and the load circuit for outputting an output signal at the second signal level. A gate insulating film of the low voltage-resistant transistor has a voltage resistance lower than that of a gate insulating film of the high voltage-resistant transistor. | 08-28-2008 |
20080204111 | HIGH-IMPEDANCE LEVEL-SHIFTING AMPLIFIER CAPABLE OF HANDLING INPUT SIGNALS WITH A VOLTAGE MAGNITUDE THAT EXCEEDS A SUPPLY VOLTAGE - A level-shifting amplifier is provided for level-shifting an input signal with a voltage magnitude that exceeds a supply voltage of the amplifier. In operation, the amplifier has an input impedance of greater than 100 MOhms. | 08-28-2008 |
20080211563 | Interface Circuit, Power Conversion Device, and Vehicle-Mounted Electric Machinery System - An interface circuit capable of reliably transmitting signal even when there is fluctuation in the potential difference in reference potentials between circuits between which signal transmission is carried out. An interface circuit | 09-04-2008 |
20080218240 | CURRENT CONTROL CIRCUIT USED FOR VOLTAGE BOOSTER CIRCUIT - When a low level voltage is inputted to an input terminal IN, a transistor EF | 09-11-2008 |
20080224755 | LEVEL-SHIFT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND LEVEL SHIFT METHOD - A level shift circuit that converts a level of an input signal having a logic level at a first input electric potential and a logic level at a second input electric potential and that generates an output signal having a logic level at a first output electric potential corresponding to the first input electric potential and a logic level at a second output electric potential corresponding to the second input electric potential. The level shift circuit includes a first power-supply node to which the first output electric potential is supplied, a second power-supply node to which the second output electric potential is supplied, a latch unit having an input node and an output node from which the output signal is output, the latch unit being configured to receive power from the first power-supply node and the second power-supply node and to maintain, if an electric potential of the input node is identical to one of the first output electric potential and the second output electric potential, an electric potential of the output node to be the other one of the first output electric potential and the second output electric potential, a switching element that is provided between the first power-supply node and the input node and controlled to be in an ON state or an OFF state, a control unit that controls the switching element to be in the ON state at a timing corresponding to the time when a level of the input signal changes from the first input electric potential to the second input electric potential, and a setting unit that changes an electric potential of the output node to the first output electric potential in a predetermined period just before the logic level of the input signal changes. | 09-18-2008 |
20080231340 | Level shift circuit - A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit. | 09-25-2008 |
20080238522 | METHOD FOR INCORPORATING TRANSISTOR SNAP-BACK PROTECTION IN A LEVEL SHIFTER CIRCUIT - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail. | 10-02-2008 |
20080238523 | LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail. | 10-02-2008 |
20080238524 | LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driving circuit is provided by the present invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between the level shifter and the buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter. | 10-02-2008 |
20080238525 | High Speed Level Shifter - The invention relates to a level shifter comprising an input stage having a parasitic capacitance and a first input terminal for applying an input signal, a limiter stage having a second input terminal for applying a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage, an output stage being coupled between a second supply terminal and said limiter stage and providing an output signal which is a level shifted version of said input signal, and a current source being adapted for injecting a current pulse into said parasitic capacitance dependent on variations of said switching signal over time. | 10-02-2008 |
20080246528 | Level shift device - The level shift device of the present invention comprises: a level shift circuit which converts a voltage level of a single input signal; and a duty correcting circuit which offsets a difference in the duty of an output signal of the level shift circuit with respect to the duty of the input signal. | 10-09-2008 |
20080246529 | MULTI-CHANNEL SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a high-side transistor, a low-side transistor, a level shift circuit for driving the high-side transistor, and a pre-driver circuit for driving the low-side transistor. A connection point of the high-side transistor and the low-side transistor serves as an output terminal. The level shift circuit has first and second N-type MOS transistors whose gates are driven by the pre-driver circuit. The semiconductor integrated circuit further includes a diode whose anode is connected to the drain of the first or second N-type MOS transistor to which the gate of the high-side transistor is not connected, and whose cathode is connected to the output terminal. | 10-09-2008 |
20080246530 | LEVEL SHIFTER - The present invention provides a level shifter that prevents through currents thereat. In the level shifter, a holding circuit is provided which comprises an inverter made up of transistors connected between an internal node and a ground potential and an inverter made up of transistors connected between an internal node and the ground potential. These inverters are connected in loop form thereby to hold signals of nodes. Thus, even when input signals complementary to each other originally are both brought to a level āLā, the signals of the nodes are held at the immediately preceding level, thus making it possible to prevent through currents from flowing through the transistors respectively. | 10-09-2008 |
20080258798 | ANALOG LEVEL SHIFTER - An analog level shifter is provided, receiving an input voltage to generate an output voltage. In the analog level shifter, a NMOS transistor has a gate coupled to an input node where the input voltage is input. A resistance device comprises a first end coupled to source of the NMOS transistor, and a second end coupled to an output node where the output voltage is output. A current source is coupled to the output node, sinking a first current therefrom to ground. | 10-23-2008 |
20080265970 | VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME - A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer. | 10-30-2008 |
20080265971 | Voltage level shift circuits - A voltage level shift circuit has a plurality of input voltage sources, a reference voltage source, a voltage level shift unit, a stabilizing unit, a first output voltage terminal, and a second output voltage terminal. The input voltage sources provide a plurality of input voltages. The reference voltage source provides a reference voltage. The voltage level shift unit raises the input voltages to a level of the reference voltage. The stabilizing unit prevents power leakage and resulting abnormal voltage levels in the voltage level shift unit. The first output voltage terminal provides a first output voltage. The second output voltage terminal provides a second output voltage inverse to the first output voltage. | 10-30-2008 |
20080265972 | OUTPUT CIRCUIT AND MULTI-OUTPUT CIRCUIT - An output circuit includes a high-side transistor, a low-side transistor, a gate protection circuit, a level shift circuit, and a pre-driver circuit. The level shift circuit interrupts a current path from an output terminal to the level shift circuit after a predetermined time has passed since the high-side transistor was switched OFF. | 10-30-2008 |
20080265973 | Semiconductor Device Having Transmitter/Receiver Circuit Between Circuit Blocks - A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means. | 10-30-2008 |
20080284485 | Method for determining a switch-on threshold and electronic circuit arrangement for carrying out the method - An electronic circuit arrangement is disclosed for converting an input voltage signal having a first voltage level into an output signal having a second voltage level. An input unit is provided for inputting the input voltage signal at the first voltage level, while an output unit is arranged for outputting the output signal at the output of the electronic circuit arrangement. A threshold value comparison unit serves for comparing the first voltage level of the input signal with a switch-on threshold value. The circuit arrangement furthermore contains an input impedance changeover unit for changing over an input impedance of the circuit arrangement from a low value to a high value after a predetermined delay duration after the first voltage level of the input voltage signal exceeded the switch-on threshold value. | 11-20-2008 |
20080284486 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR DEVICE AND METHOD FOR GENERATING INTERNAL VOLTAGE - An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal. | 11-20-2008 |
20080297223 | LEVEL SHIFT CIRCUIT WITH IMPROVED DV/DT SENSING AND NOISE BLOCKING - A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit. | 12-04-2008 |
20080297224 | Minimizing Static Current Consumption While Providing Higher-Swing Output Signals when Components of an Integrated Circuit are Fabricated using a Lower-Voltage Process - An aspect of the present invention minimizes static current consumption in an output block which receives a lower strength input signal and drives a corresponding output signal with a higher strength. Such a feature may be obtained while ensuring that no closed path exists between a first and second reference potentials (having voltage levels equaling upper and lower limits of the swing of the output signal) used by a circuit portion driving a pair of transistors operating as an inverter in the output block. In one embodiment, such a closed path is avoided during the steady state of the output signal, while in an alternative embodiment, the closed path is avoided during the transitions as well. | 12-04-2008 |
20080303578 | BOOST CIRCUIT AND LEVEL SHIFTER - A level shifter including a first boost circuit, an inverter, a second boost circuit and a level shift circuit is disclosed. The first boost circuit receives an input signal, and a first amplification factor for the input signal is determined based on a control signal. The inverter receives the input signal to generate an inverted input signal. The second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and a second amplification factor for the inverted input signal is determined based on the control signal. The level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level. | 12-11-2008 |
20080309395 | Systems and Methods for Level Shifting using AC Coupling - Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value. | 12-18-2008 |
20080315936 | Level Shifting - Various aspects are described, such as a method for operating a level shifter, in which the level shifter is coupled to a first supply voltage and a second supply voltage different from the first supply voltage. The method may include detecting whether the first supply voltage is present, and decoupling an input of the level shifter from an output of the level shifter responsive to detecting that the first supply voltage is not present. | 12-25-2008 |
20080315937 | APPARATUS FOR GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for generating an internal voltage in a semiconductor integrated circuit includes a first voltage generating unit configured to detect a feedback voltage level of a first internal voltage and perform a pumping operation, thereby generating a first internal voltage, and a second voltage generating unit configured to generate a second internal voltage by detecting a feedback voltage level of the second internal voltage, performing level shifting on the detected feedback voltage level, receiving the first internal voltage, and generating the second internal voltage based on the level shifted feedback voltage signal and the received first internal voltage. | 12-25-2008 |
20080315938 | DRIVING CIRCUIT FOR SWITCHING ELEMENTS - A level shifting circuit, satisfying a requirement of a high tolerated dV/dt level, and a highly reliable inverter circuit, wherein a set pulse signal and a reset pulse signal, both of which are level-shifted to a potential side taking as reference a reference potential of a gate control terminal of a switching terminal, are obtained differentially and integrated, and, in case these pulse signals equal or exceed stipulated integrated values, are transmitted as regular control signals controlling the on/off state. | 12-25-2008 |
20090002049 | Voltage Output Device for an Electronic System - The present invention discloses a voltage output device for an electronic system, for transforming an input voltage for generating an output voltage for a load, which includes a first node, a second node, a third node, a first transistor, a second transistor, a first driving unit, a second driving unit, a control unit, a first diode, an inductor, a first capacitor, and a boost circuit. | 01-01-2009 |
20090002050 | Voltage Output Device for an Electronic System - The present invention discloses a voltage output device for an electronic system, for transforming an input voltage for generating an output voltage for a load, which includes a first transistor, a second transistor, a first driving unit, a second driving unit, a control unit, a diode, an inductor, a first capacitor, and a boost circuit. The boost circuit includes a level shifter, a third transistor, and a second capacitor. Whether the third transistor | 01-01-2009 |
20090002051 | INPUT CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT - An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal. | 01-01-2009 |
20090002052 | SEMICONDUCTOR DEVICE - A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply. | 01-01-2009 |
20090009229 | HIGH/LOW VOLTAGE TOLERANT INTERFACE CIRCUIT AND CRYSTAL OSCILLATOR CIRCUIT - A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor. | 01-08-2009 |
20090009230 | Semiconductor device - A semiconductor device includes a level shift circuit to convert an input signal having an amplitude from a first power supply potential to a second power supply potential to a signal having an amplitude from the first power supply potential to a third power supply potential, a first output portion to output voltage generated from the third power supply potential to an output terminal based on the output of the level shift circuit, the first output portion including a NMOS transistor, and a second output portion to output voltage generated from the third power supply potential to an output terminal based on the output of the level shift circuit, the second output portion including a PMOS transistor. | 01-08-2009 |
20090015313 | Level Shift Circuit and Semiconductor Integrated Circuit Including the Same - In a level shift circuit, including two Nch transistors Tn | 01-15-2009 |
20090021292 | RELIABLE LEVEL SHIFTER OF ULTRA-HIGH VOLTAGE DEVICE USED IN LOW POWER APPLICATION - The present invention relates to integrated circuits. In particular, it relates to an IC comprising a receiving stage for receiving an input signal, an output stage for generating an output signal having a larger voltage range than the input signal and a level shifter. Embodiments of the invention provide a structure and a method for fabricating the IC wherein the level shifter is incorporated within the IC to improve reliability of the IC. | 01-22-2009 |
20090021293 | Low-Power Integrated-Circuit Signal Processor With Wide Dynamic Range - An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal. | 01-22-2009 |
20090027100 | LEVEL SHIFTER AND FLAT PANEL DISPLAY USING THE SAME - A level shifter for a flat panel display device includes: first and second transistors that are different type transistors and serially coupled between first and second power supplies, the second power supply for supplying a lower voltage power than the first power supply; a first capacitor between gate electrodes of the first and second transistors; an input line for a first input signal coupled to the gate electrode of the first or second transistor; a third transistor between a second electrode of the first capacitor and a third power supply, the third transistor having a gate electrode coupled to an input line of a second input signal; and a fourth transistor between the second electrode of the first capacitor and the third transistor, the fourth transistor having first and gate electrodes that are coupled to the second electrode of the first capacitor, such that the fourth transistor is diode-connected. | 01-29-2009 |
20090027101 | LEVEL SHIFT CIRCUIT - The present invention provides a level shift circuit that can reliably cut off the path of a through current regardless of the state of supply of power to plural circuit sections that operate by different power supplies. The level shift circuit is provided with an input circuit section that operates by a power supply voltage VDD | 01-29-2009 |
20090027102 | Low-Leakage Level-Shifters with Supply Detection - Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage is described, including a level-shifter configured to shift a voltage of an digital input signal based on a first supply voltage to a digital output signal based on a second supply voltage, comprising a first transistor and a second transistor configured to set the digital output signal based on the digital input signal, a supply detector configured to generate a detection signal based on the first supply voltage, a disabler configured to, based on the detection signal, set the digital output signal of the level-shifter to a predetermined state, and a leakage reducer configured to, based on the detection signal, electrically disconnect the first and second transistors from the level-shifter. | 01-29-2009 |
20090027103 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source V | 01-29-2009 |
20090027104 | Methods and apparatus for predictable level shifter power-up state - In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided. The level shifter comprises a first input and a second input forming a differential input to receive signals at the first voltage level, a first output and a second output forming a differential output to provide output signals at the second voltage level, and at least one circuit element coupled between the differential input and the differential output to pull the first output to a lower voltage level than the second output during power-up so that the level shifter powers-up in a desired state | 01-29-2009 |
20090033400 | VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT - Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state. | 02-05-2009 |
20090033401 | Level Shifting Circuit With Symmetrical Topology - A shifter circuit includes a pair of feed forward sections and a pair of feedback sections. The sections are arranged and coupled to form a balanced symmetrical topology. The feed forward sections each include inverter pairs of PMOS and NMOS devices. The feedback sections each include a pair of cross-coupled devices. A pair of output nodes are operatively positioned between the pair of feedback sections. A method for using the circuit to generate output signals at respective output ports is also disclosed. | 02-05-2009 |
20090033402 | LEVEL CONVERSION CIRCUIT - A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero. | 02-05-2009 |
20090033403 | LEVEL CONVERTING CIRCUIT - A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. | 02-05-2009 |
20090039942 | LEVEL SHIFTER - A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node. | 02-12-2009 |
20090051402 | MULTI-FUNCTION CIRCUIT MODULE HAVING VOLTAGE LEVEL SHIFTING FUNCTION AND DATA LATCHING FUNCTION - The present invention discloses a multi-function circuit module having voltage level shifting function and data latching function via switching a plurality of switch elements. The multi-function circuit module includes a first circuit module, a fourth switch element, and a fifth switch module, wherein the first circuit module further includes a first switch module, a second switch module, and a third switch module. The multi-function circuit module can substantially reduce the circuit layout area. For example, when the multi-function circuit module of the present invention is applied in a source driving chip circuit, the multi-function circuit module can replace the original low-to-high voltage level shifting circuit and data latching circuit, so as to attain the purpose of reducing the chip area. | 02-26-2009 |
20090051403 | Signal process circuit, level-shifter, display panel driver circuit, display device, and signal processing method - In one embodiment of the present invention, a signal process circuit in accordance with the present invention includes: a first input terminal via which an input signal is supplied; a second input terminal via which a predetermined signal is supplied; a cross-coupled inverter circuit, including first and second CMOS inverter circuits, in which an input of the first CMOS inverter circuit and an output of the second CMOS inverter circuit are interconnected to each other and an output of the first CMOS inverter circuit and an input of the second CMOS inverter circuit are interconnected to each other; a current control circuit that applies currents to the first and second CMOS inverter circuits in accordance with a timing signal, the input signal, and the predetermined signal; output terminals which are connected to the outputs of the first and second CMOS inverter circuits, respectively, and from which an output signal is supplied; and a reset circuit that resets the output signal based on the timing signal. With the arrangement, it is possible to cause a signal of a small amplitude to be level-shifted and latched at low power consumption. | 02-26-2009 |
20090058491 | HIGH-TO-LOW LEVEL SHIFTER - A high-to-low level shifter is disclosed, comprising a high voltage unit and a low voltage unit. The high voltage unit receives an input signal from an input node. The high voltage unit outputs a first output signal to an output node when the high voltage unit receives a low-voltage-level input signal. The low voltage unit outputs a second output signal to the output node when the high voltage unit receives a high-voltage-level input signal. | 03-05-2009 |
20090058492 | ELECTRONIC ISOLATOR - The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system. | 03-05-2009 |
20090058493 | Signal Level Converter - An electronic device with a supply voltage level converter converts a signal from a first low supply voltage level to a second high supply voltage level includes; a first pair of cross coupled MOS transistors compliant with the second supply voltage level, each having a source coupled to the second supply voltage level and providing complementary output signals at respective drains; driven by a second pair of common gate MOS transistors compliant with the second supply voltage; driven by a third pair of common gate MOS transistors compliant with the first voltage level; and driven by first and second inverters coupled in a chain and supplied by the first supply voltage level, each having an output connected to the source of a transistor in a third pair. | 03-05-2009 |
20090058494 | HEAD SUBSTRATE, PRINTHEAD, AND HEAD CARTRIDGE - The following arrangement is added to a head substrate including a plurality of electrothermal transducers, a plurality of switching elements which drive the plurality of electrothermal transducers, and a logic circuit which drives the plurality of switching elements. That is, the head substrate includes a plurality of level converters which correspond to the respective switching elements, and apply a voltage obtained by boosting a logic voltage. Further, the head substrate includes a bias circuit which applies a bias voltage lower than the boosted voltage to the plurality of level converters. | 03-05-2009 |
20090066396 | LEVEL SHIFTING CIRCUIT - A level shifting circuit is provided. Thin oxide devices are utilized to reduce the threshold, and thick oxide devices are utilized to protect the thin oxides from breakdown. An input voltage input voltage swings between a low supply voltage and ground. An output voltage swings between a high supply voltage and the ground. An inverter with input connected to the input voltage, outputs an inverted input voltage. The input voltage is subsequently between 0.5V to 2.5V, and the output voltage is subsequently between 3V to 10V. | 03-12-2009 |
20090066397 | LEVEL SHIFT CIRCUIT - In a level shift circuit, even when a power supply voltage of an input signal is reduced, a level shift operation is reliably performed without causing increase in circuit area and process costs. For a pair of n-type transistors which receive an input signal and a reverse signal of the input signal as a pair of complementary signals at their gates, respectively, a layout which allows reduction in unit gate width size is adopted. The layout configuration includes a plurality of divided rectangular doped regions which function as drains and sources and a plurality of gates arranged to align in a gate length direction with a gate width direction according with a short side direction of the doped regions. The gates are electrically connected with one another, the drains are electrically connected with one another, and the sources are electrically connected with one another. | 03-12-2009 |
20090066398 | Voltage Level Shifter Circuit - A voltage level shifter circuit is provided. A high power voltage is input to a first power voltage terminal, an enable signal is input to an enable terminal, and an intermediate voltage level between the first power voltage and a high enable signal voltage is input to a second power voltage terminal. First and second inverters are connected to the enable terminal. A first transistor has a source connected to the second inverter. A second transistor has a drain connected to a drain of the first transistor, a source connected to the second power voltage terminal, and a gate connected to an output terminal of the first inverter. Third and fourth transistors have gates connected to the outputs of the first and second transistors, the fourth transistor having a source connected to the first power voltage terminal. | 03-12-2009 |
20090066399 | Level shift circuit - A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption. | 03-12-2009 |
20090072879 | SHORT-CIRCUIT CHARGE-SHARING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES - A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor. | 03-19-2009 |
20090072880 | OUTPUT CIRCUIT, OUTPUT CIRCUIT GROUP, AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An output circuit group comprises at least one first output circuit that outputs a pair of differential signals, the first output circuit including a first reversing circuit operated by applying a first power supply potential and a second power supply potential to reverse a first driving signal so as to output a first reverse driving signal, a first signal level converting circuit operated by applying the first power supply potential and a third power supply potential to convert the first driving signal to a signal having a predetermined level to output, a second signal level converting circuit operated by applying the first and the third power supply potentials to convert the first reverse driving signal to a signal having a predetermined level to output, a first differential circuit operated by applying the first and the third power supply potentials to output a signal having a first polarity corresponding to a difference between the signal output from the first signal level converting circuit and the signal output from the second signal level converting circuit, a second differential circuit operated by applying the first and the third power supply potentials to output a signal having a second polarity that is opposite to the first polarity and corresponding to a difference between the signal output from the second signal level converting circuit and the signal output from the first signal level converting circuit, a first output signal generating circuit operated by applying the first and the third power supply potentials to generate a first output signal based on the signal having the first polarity output from the first differential circuit, and a second output signal generating circuit operated by applying the first and the third power supply potentials to generate a second output signal based on the signal having the second polarity output from the second differential circuit, the first and the second output signals being included in the differential signals; and at least one second output circuit that outputs a single forward or reverse signal, the second output circuit including a second reversing circuit operated by applying the first and the second power supply potentials to reverse a second driving signal so as to output a second reverse driving signal, a third signal level converting circuit operated by applying the first and the third power supply potentials to convert the second driving signal to a signal having a predetermined level to output, a fourth signal level converting circuit operated by applying the first and the third power supply potentials to convert the second reverse driving signal to a signal having a predetermined level to output, a third differential circuit operated by applying the first and the third power supply potentials to output a signal having a first polarity corresponding to a difference between the signal output from the third signal level converting circuit and the signal output from the fourth signal level converting circuit, a loading circuit connected to an output terminal of each of the third and the fourth signal level converting circuits to have a load capacitance approximately equal to a load capacitance of the third differential circuit, and a third output signal generating circuit operated by applying the first and the third power supply potentials to generate the forward or reverse signal based on the signal having the first polarity output from the third differential circuit. | 03-19-2009 |
20090085635 | HIGH FREQUENCY DIFFERENTIAL VOLTAGE LEVEL SHIFTER - A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages. | 04-02-2009 |
20090085636 | Pre-driver circuit and apparatus using same - In one embodiment, a pre-driver circuit comprises input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of the digital input signal and a second inverted signal that is an inversion of the first inverted signal. The pre-driver circuit also includes actuation circuitry connected to be driven by the digital input signal, the first inverted signal, and the second inverted signal to produce a digital output signal that alternates between an upper limit that is less than the upper rail and a lower limit that is greater than the lower rail by at least an amount, wherein all transistors forming the actuation circuitry comprise a single channel type. | 04-02-2009 |
20090085637 | Apparatus effecting interface between differing signal levels - An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value. | 04-02-2009 |
20090085638 | Semiconductor Device - It is an object of the present invention to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width in a semiconductor device capable of communicating data wirelessly. In a semiconductor device, a level shift circuit is provided between a data demodulation circuit and each circuit block where demodulated signals are outputted from the data demodulation circuit. In such a manner, voltage amplitude of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, a pulse width of the demodulated signal is made almost equal to that of signals in each circuit block, or a pulse width of the demodulated signal is made almost equal to that of the outputted signals from each circuit block. Accordingly, it is possible to prevent an error or malfunction such as nonresponse which is caused due to difference in pulse width. | 04-02-2009 |
20090085639 | OUTPUT BUFFER CIRCUIT - An output buffer circuit is provided that outputs an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage. The output buffer circuit includes an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage. A first driving circuit outputs a first control signal to control the pull-down transistor. A second driving circuit includes a latch circuit to latch signals and outputs a second control signal to control the pull-up transistor based on retained data in that latch circuit. A level shifter changes the retained data in the latch circuit when logic of the input signal changes. | 04-02-2009 |
20090085640 | Level shift device and method for the same - The present invention discloses a level shift device which comprises: a level shift circuit for receiving an input with a first voltage level and generating a first signal and a second signal with a second voltage level; and an output circuit which generates an output according to the first signal and the second signal. | 04-02-2009 |
20090091367 | LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driver including a first level shifter group and a second level shifter group is provided. The first level shifter group includes at least one first level shifter to receive a first input signal. The second level shifter group includes at least one second level shifter to receive a second input signal. The driver sequentially enables the first level shifter group and the second level shifter group to sequentially transfer voltage levels of the first input signal and the second input signal. | 04-09-2009 |
20090091368 | DESIGN STRUCTURE FOR A HIGH-SPEED LEVEL SHIFTER - Disclosed are embodiments of a design structure for a voltage level shifter circuit that operates without forward biasing junction diodes, regardless of the sequence in which different power supplies are powered up. The circuit embodiments incorporate a pair of series connected switches (e.g., transistors) between an input terminal and a voltage adjusting circuit. Each switch is controlled by a different supply voltage from a different power supply. Only when both power supplies are powered-up and the different supply voltages are received at both switches will a first signal generated using one of the supply voltages be passed to a voltage adjusting circuit and thereafter converted into a second signal representative of the first signal, but generated using the second supply voltage. Incorporation of the pair of series connected switches into the voltage level shifter circuit prevents forward biasing of junction diodes in the circuit and thereby prevents current leakage from the power supplies. | 04-09-2009 |
20090102537 | METHOD OF FORMING A SIGNAL LEVEL TRANSLATOR AND STRUCTURE THEREFOR - In one embodiment, a first portion ( | 04-23-2009 |
20090108903 | LEVEL SHIFTER DEVICE - A first transistor of a level shifter provides conductivity between a reference voltage and a node of the level shifter to hold a state of the level shifter output. When an input signal of the level shifter switches, additional transistors assist in reducing the conductivity of the first transistor. This enhances the ability of the level shifter to change the state of the output in response to the change in the input signal, thereby improving the writeability of the level shifter. | 04-30-2009 |
20090108904 | Shifting of a voltage level between different voltage level domains - A voltage level shifter for receiving a digital signal from a first voltage domain and converting said signal to a digital signal in a second voltage domain is disclosed. The voltage level shifter comprises: an input for receiving said digital signal from said first voltage domain; a device connected to said input of said voltage level shifter for receiving said digital signal from said first voltage domain and for outputting a digital signal in said second voltage domain, said device being powered by said second voltage domain; a first switching device arranged to connect a high level voltage source of said second domain to an input of said device in response to said input digital signal having a high level and to isolate said high level voltage source of said second domain from said input of said device in response to said input digital signal having a low level; and a second switching device arranged between said voltage level shifter input and said input of said device for inhibiting current flow from said high level voltage source of said second domain to said voltage level shifter input in response to a high level signal at said voltage level shifter input and for allowing current flow in both directions between said voltage level shifter input and said input of said device in response to said voltage level shifter input having a low level signal. | 04-30-2009 |
20090115487 | Level Converter - A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal. | 05-07-2009 |
20090121771 | LEVEL SHIFT CIRCUIT AND METHOD THEREOF - A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal. | 05-14-2009 |
20090128215 | LEVEL SHIFTER, INTERFACE DRIVING CIRCUIT AND IMAGE DISPLAYING SYSTEM - The present invention relates to a level shifter for receiving a control signal to produce a driving voltage, comprising: a storage capacitor, one end of the storage capacitor coupled to the control signal and a reference voltage, another end of the storage capacitor coupled to the driving voltage and a assisting voltage; and a set of selecting switches for selecting one of the driving voltage and the assisting voltage to two ends of the storage capacitor, so that the storage capacitor is capable of boosting the voltage level of the control signal while the two ends of the storage capacitor coupled to the control signal and the driving voltage. The present invention further provides an interface driving circuit and an image displaying system. | 05-21-2009 |
20090134929 | Level shifter for high-speed and low-leakage operation - The present invention discloses a voltage level shifter capable of interfacing between two circuit systems having different operating voltage swings. The voltage level shifter comprises an input buffer having a low supply voltage for inverting an external input signal to an internal input signal, and an output buffer having a high supply voltage for inverting the internal input signal to an external output signal. The high level of the external input signal is lower than the high level of the external output signal. The voltage level shifter is designed such that the input buffer is operating to achieve a low-leakage and high-speed performance. | 05-28-2009 |
20090134930 | LEVEL SHIFT CIRCUIT - A level shift circuit prevents a through current in an output circuit connected to a high-voltage power supply, thereby reducing power consumption and noise and enabling a high-speed operation. The level shift circuit includes first and second bias generating circuits that supply a gate bias voltage to each of a PMOS transistor as a first transistor and a NMOS transistor as a second transistor. Each of the first and second bias voltage generating circuits includes a series connection of a diode-connected PMOS transistor and a diode-connected NMOS transistor. The discharge of a capacitor to the high-voltage power supply is prevented, and a through current is prevented when an output signal transitions from a high-level to a low-level and vice versa, whereby power consumption and noise can be reduced. | 05-28-2009 |
20090134931 | MULTIPHASE LEVEL SHIFT SYSTEM - Each of n level shifters (LS | 05-28-2009 |
20090146723 | BUFFER CIRCUIT - Disclosed is a buffer circuit including a source follower circuit comprising a MOS transistor which is driven by a current source. The MOS transistor has a gate to which an input voltage is supplied, a source from which an output voltage is output and a back gate supplied with a back gate voltage for being controlled to provide for a desired value of the source voltage. There is provided a second MOS transistor, to a gate of which a bias voltage is supplied, and a source of which is connected to a non-inverting input terminal of an OP amp. An output voltage of the OP amp is supplied as the back gate voltage | 06-11-2009 |
20090153218 | LEVEL SHIFT CIRCUIT WITH POWER SEQUENCE CONTROL - A level shift circuit for providing predictable outputs when VDDH is powering up and minimizing DC current when VDDL is powering up. The level shift circuit may have a control circuit that includes a first inverter with an input coupled to VDDL, one or more diodes coupled between the first inverter and its powering voltage supply, a second inverter coupled to an output of the first inverter (optionally coupled to its voltage supply via one or more diodes), a third inverter coupled to an output of the second control inverter, an NMOS transistor coupled to an output of the third inverter that forces the output of the level shift circuit to the ground voltage when enabled, and a PMOS transistor coupled to an output of the third inverter that disconnects a portion of the level shift circuit, and thus the output of the level shift circuit, from VDDH when disabled. | 06-18-2009 |
20090153219 | Replica bias circuit for high speed low voltage common mode driver - A transmitter provides fast settling times, slew rate control, and power efficiency while reducing the need for large external capacitors. The transmitter typically includes a pre-driver, driver, and replica circuit. The pre-driver can shift the voltage level of an input signal to produce a shifted signal. The pre-driver can shift the voltage level in response to a selectable load resistance circuit and a voltage regulation feedback signal. The driver receives the shifted signal and generates a driver output signal in response to the received shifted signal. The replica circuit can be a scaled replica of the pre-driver and the driver using scaled components from the pre-driver and driver circuits. The scaled components can be used to generate the voltage regulation feedback signal. The generated voltage regulation feedback signal represents, for example, whether the output voltage of the driver output is above a reference voltage. | 06-18-2009 |
20090153220 | SOURCE DRIVER AND POWER DOWN DETECTOR THEREOF - The present invention discloses a source driver powered by a power supply comprising at least one channel, at least one output pad coupled to the channel, at least one switch connected between the output pad and a predetermined voltage, and a power down detector for detecting whether a first supply voltage from the power supply is insufficient and generating a reset signal to turn on the switch if yes. | 06-18-2009 |
20090160523 | Receiving Higher-Swing Input Signals When Components Of An Integrated Circuit Are Fabricated Using A Lower-Voltage Process - An aspect of the present invention provides an input block which can receive input signals of a higher voltage swing when the internal components are fabricated using a lower voltage process. In an embodiment, the input block is designed to prevent current flow into an input signal path when the input signal is at a logic low level. In another embodiment, the input block is designed to recognize a logic value corresponding to a logic high level of input signals at a higher voltage level during a transition from logic low to logic high. | 06-25-2009 |
20090160524 | LEVEL SLIDER CIRCUIT - The invention relates to a level slider circuit having a first level slider ( | 06-25-2009 |
20090160525 | LEVEL SHIFT CIRCUIT - An amplifier including the transistors of a first set operates by a power source VCC | 06-25-2009 |
20090167405 | Reduced Leakage Voltage Level Shifting Circuit - A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback. | 07-02-2009 |
20090174457 | IMPLEMENTING LOW POWER LEVEL SHIFTER FOR HIGH PERFORMANCE INTEGRATED CIRCUITS - A low power level shifter circuit for high performance integrated circuits includes an input inverter operating in a domain of a first voltage supply and receiving an input signal and a design structure on which the subject circuit resides is provided. An output stage operating in a domain of a higher second voltage supply includes a first output inverter connected to the input inverter and a second output inverter connected in series with the first output inverter. The second output inverter provides a level shifted output signal having a voltage level corresponding to the second voltage supply. A series connected finisher transistor and finisher control transistor are connected between the second voltage supply and an input to the first output inverter. The finisher control transistor is activated responsive to the input signal. A path control transistor controls a path between the first voltage supply and the input inverter. The path control transistor being activated responsive to the level shifted output signal. | 07-09-2009 |
20090174458 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 07-09-2009 |
20090189669 | METHODS AND APPARATUS TO REDUCE PROPAGATION DELAY OF CIRCUITS - Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off. | 07-30-2009 |
20090189670 | LEVEL SHIFTER WITH REDUCED POWER CONSUMPTION AND LOW PROPAGATION DELAY - A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level. | 07-30-2009 |
20090195291 | Level shift circuit, and driver and display system using the same - Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level. When the input signal supplied in the predetermined time interval assumes a value that sets the output terminal to the second voltage level, the second level shifter sets the output terminal to the second voltage level with the first level shifter deactivated. | 08-06-2009 |
20090195292 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost. | 08-06-2009 |
20090201069 | LEVEL SHIFTING CIRCUIT - A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal. | 08-13-2009 |
20090201070 | PRE-DRIVER CIRCUIT USING TRANSISTORS OF A SINGLE CHANNEL TYPE - A serial interface apparatus comprises a driver for generating a differential communication signal and a pre-driver for driving the driver circuit. The pre-driver receives an input signal that alternates between VDD and ground and produces an output signal that alternates between a lower limit that is greater than ground and an upper limit that is less than VDD. The pre-driver comprises input circuitry and actuation circuitry, and the actuation circuitry comprises transistors of a single channel type. | 08-13-2009 |
20090212841 | LEVEL SHIFT CIRCUIT AND METHOD FOR THE SAME - The present invention discloses a level shift circuit which comprises: an input driver circuit; a capacitor having a first end electrically connected with the output of the input driver circuit; an output driver circuit electrically connected with a second end of the capacitor; and a feedback latch circuit electrically connected between the output of the output driver circuit and the second end of the capacitor, for maintaining the voltage level at the second end of the capacitor. | 08-27-2009 |
20090212842 | Level Shifter with Memory Interfacing Two Supply Domains - A level-shifter circuit configured to transfer data between two voltage supply domains may eliminate crowbar current while simultaneously providing a valid output signal. The level-shifter circuit may transfer a data signal between the two voltage domains using a latch that is capable of maintaining its output levelābased on the destination supply railāto correspond to the same state to which the level of the input signalābased on the originating supply railācorresponds, even when the originating supply is decreased to a zero-volt state, or to a voltage equivalent to a low state. During normal operation, when both power supplies are available, the signal at the output of the latch, and hence at the output of the level-shifter circuit may toggle to always track the input signal. Thus, the level of the signal at the output of the level-shifter may always represent the same state (e.g. binary value) as the level of the input signal, during normal operation and also when the originating power supply is powered down. | 08-27-2009 |
20090219074 | Capacitive Coupling Type Level Shift Circuit of Low Power Consumption and Small Size - Provided is a level shift circuit. The level shift circuit includes an inverter including a first transistor having a first polarity to which an input signal from an input port is applied through a gate and a second transistor having a second polarity which is an opposite polarity to the first polarity, the second transistor being connected in series to the first transistor between a positive source voltage and a negative source voltage and a connection node between the first and second transistors being an output port, a capacitor connected between a gate of the first transistor and a gate of the second transistor, and a voltage adjusting means for accurately adjusting a voltage applied to the gate of the second transistor according to an exact switching operation time of the second transistor, using a clock signal and an output port signal of the inverter. A stable and high-speed operation can be performed with a comparatively small size and low power consumption can be achieved. | 09-03-2009 |
20090231014 | LEVEL SHIFTER CIRCUIT - A level shifter circuit which amplifies the amplitude of an input signal, includes a CMOS inverter which is composed of a p-type transistor and an n-type transistor, a first and a second capacitor one electrode of each of which is connected to the gate of the p-type transistor and that of the n-type transistor, respectively, a first switch which supplies the input signal to the other electrodes of the first and second capacitors, a second switch which applies a direct-current voltage whose amplitude is nearly half of the amplitude of the input signal to the other electrodes of the first and second capacitors, and a third and a fourth switch which apply a first and a second preset voltage to one electrode of each of the first and second capacitors, respectively. | 09-17-2009 |
20090231015 | DRIVER CIRCUIT - An object is to provide a driver circuit as well as a level converting circuit, capable of reducing current consumption and accelerating an operation, and in the driver circuit that changes a voltage level of an output signal in correspondence with a change in voltage level of an input signal, when a transistor is turned on and a voltage level of an output signal changes, a positive feedback operation of raising a voltage of an output node of an input stage circuit that drives the transistor is performed, whereby a gate-source voltage of the transistor increases while an on-resistance thereof decreases, and a change in voltage level of the output node in the positive feedback operation is accelerated due to a bootstrap action in the input stage circuit. | 09-17-2009 |
20090231016 | GATE OXIDE PROTECTED I/O CIRCUIT - An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of a second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage. | 09-17-2009 |
20090237139 | Level shifter with reduced current consumption - A level shifter includes a level shifting unit for level-shifting an input signal at a first voltage level into a signal at a second voltage level, and an output controller for controlling the level shifting unit to maintain output at a predetermined logic level in response to a deep power down mode signal generated from power which is not turned off in a deep power down mode. | 09-24-2009 |
20090243692 | Two Voltage Input Level Shifter with Switches for Core Power Off Application - A voltage level shifter includes a first switch module having a first transistor and a second transistor, each transistor having a drain, a gate, and a source, wherein the drains of the first and the second transistors are coupled to a first voltage terminal. The voltage level shifter further includes a second switch module coupled between the first switch module and a second voltage terminal, the second switch module including at least six transistors coupled each other, wherein each transistor of the second switch module having a gate for receiving a GATE signal, a GATEb signal, a CORE_INPUT signal, a CORE_INPUTb signal, an IO_INPUT signal, or an IO_INPUTb signal, respectively, wherein the second switch module is designed to produce an output signal at an output node in response to the IO_INPUTb signal and the IO_INPUT signal respectively, irrespective of the CORE_INPUTb signal and the CORE_INPUT signal when the GATE signal is logic low, thereby reducing a leakage current flowing from the first voltage terminal to the second voltage terminal. | 10-01-2009 |
20090243693 | CIRCUIT FOR PROVIDING DETERMINISTIC LOGIC LEVEL IN OUTPUT CIRCUIT WHEN A POWER SUPPLY IS GROUNDED - A high voltage analog interface circuit capable of producing a determinate zero or other low voltage when the high voltage power supply is turned off or grounded. | 10-01-2009 |
20090243694 | VOLTAGE CONVERTING DRIVER APPARATUS - A voltage converting apparatus is provided that includes a dynamic driver circuit and a voltage converting circuit. The dynamic driver circuit may receive a clock signal and input signals and provide a dynamic signal based on the clock signal and the input signals. The voltage converting circuit may receive the dynamic signal from the dynamic driver circuit and provide an output signal based on the received dynamic signal. The dynamic driver circuit may be powered by a first voltage source and the voltage converting circuit may be powered by a second voltage source. | 10-01-2009 |
20090243695 | BI-DIRECTIONAL LEVEL SHIFTED INTERRUPT CONTROL - The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one āread onlyā and another āinput/outputā pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin. | 10-01-2009 |
20090243696 | HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING SHIFTERS AND METHOD OF FABRICATING THE SAME - Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters. | 10-01-2009 |
20090243697 | LEVEL SHIFT CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR CIRCUIT DEVICE HAVING THE SAME - A level shift circuit includes a level shift section for receiving a low potential signal oscillating between a high potential and a ground potential and converting it into a high potential signal oscillating between the high potential and the ground potential, the level shift section being connected to at least a high potential power supply for generating the high potential, a low potential power supply for generating the low potential, and a ground power supply for generating the ground potential, an inverter section for inverting-amplifying the high potential signal from the level shift section, and an N-type MOS transistor for supplying the ground potential to the inverter section, the N-type MOS transistor being connected in series to the inverter section between the high potential power supply and the ground power supply and having its gate electrode connected to the low potential power supply. | 10-01-2009 |
20090251193 | LEVEL SHIFTER AND CIRCUIT USING THE SAME - A level shifter consisting of first to fifth transistors is provided. First ends of the first and second transistors are coupled to a first supply voltage. Control ends of third and fourth transistors respectively receive first and second input signals. First ends of the third and fourth transistors are respectively coupled to control ends of the second and first transistors, and are respectively coupled to second ends of the first and second transistors. Second ends of the third and fourth transistors are coupled to a second supply voltage. The first ends of the third and fourth transistors respectively output first and second output signals. A first end and a control end of the fifth transistor are coupled to the control ends of one and the other of the first and second transistors. A second end of the fifth transistor is coupled to the second supply voltage. | 10-08-2009 |
20090251194 | DC COMMON MODE LEVEL SHIFTER - A switched-mode level-shifter shifts a differential voltage superimposed on a common-mode voltage. In the level shifter, a common-mode inductive reactor has at least two windings, and at least one of the differential voltage and the common-mode voltage are applied to at least one of the windings of the reactor. A switch charges the inductive reactor when caused to be in a first state, where the inductive reactor when charged experiences a change of flux according to the applied voltage. The switch also actuates a reset of the charged inductive reactor when caused to be in a second state, where the inductive reactor when reset reverses the change of flux experienced thereby. A source of a chopping signal is provided to alternately drive the switch between the first and second states, where each of the first and second states is one of in and out of conduction. | 10-08-2009 |
20090256617 | VOLTAGE LEVEL SHIFTER - Methods, systems, and devices are described for providing voltage level shifting that may operate reliably and at low power, even at high voltages and/or high switching frequencies. Embodiments receive an input signal representing input information, and effectively generate two voltage responses as a function of the input signal. Each voltage response includes exponential terms as a function of resistive and capacitive loading effects of components of the embodiments. A combined response signal is generated substantially as a superposition of the first response signal and the second response signal. A high-side driver signal is then generated as a function of the combined response signal, such that the high-side driver signal substantially preserves the input information represented by the input signal, and such that the first exponential response and the second exponential response are substantially absent from the high-side driver signal. | 10-15-2009 |
20090261884 | Level shifter using coupling phenomenon - A level shifter removes delay, which is generated at the time of transition of an input signal level, by adjusting a size of NMOS transistors to perform pull-down and pull-up operations. The level shifter includes a coupling unit for setting up a voltage level of a first node according to a voltage level of an input signal, a first buffer for transferring an output signal by buffering a signal from the first node, and a driving unit configured to receive the input signal and the output signal and drive the first node. | 10-22-2009 |
20090261885 | POWER-ON DETECTING CIRCUIT AND LEVEL CONVERTING CIRCUIT - When a low supply potential has risen while a high supply potential has not risen, a logical value ā0ā is output as an output signal by applying a ground potential to an input terminal of a latch circuit through a capacitor. On the other hand, when the high supply potential has risen while the low supply potential has not risen, a logical value ā0ā is output as an output signal by converting the high supply potential into the ground potential by the level shifter. If both the low supply potential and the high supply potential have risen, the logical value ā1ā is output as an output signal by converting the ground potential into the high supply potential by the level shifter. | 10-22-2009 |
20090278586 | LEVEL SHIFT CIRCUIT - A level shift circuit for adjusting voltage level of an input signal includes a voltage dividing circuit coupled to a input terminal for outputting a first voltage signal in response to the input signal at the input terminal, and a buffer coupled to a first node for generating a second voltage signal by adjusting voltage level of the first voltage signal. The voltage dividing circuit includes a first load coupled between the first node and the first supply voltage, and a second load coupled between the input terminal and the first node. | 11-12-2009 |
20090278587 | LEVEL SHIFT CIRCUIT - A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit | 11-12-2009 |
20090289685 | Bias voltage generation for capacitor-coupled level shifter with supply voltage tracking and compensation for input duty-cycle variation - A circuit architecture, or topology, that provides a level shifter substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled input terminals connected to the gates of the high-side transistors and circuitry to set the bias voltage at the gates of the high-side transistors, wherein the bias voltage generation circuitry receives at least information indicative of both the H-bridge power supply voltage and the modulation of the input signal. Various embodiments include a switchable element coupled in series with a voltage divider portion in the bias voltage generation circuitry. The ratio of on to off time of the switchable element determines the average current through the voltage divider and thus the bias voltage. To prevent excessive short-circuit current flow through the high-side transistors, the switchable elements are turned off responsive to detection of a short-circuit condition. | 11-26-2009 |
20090289686 | VOLTAGE LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M | 11-26-2009 |
20090295451 | Systems and Methods of Digital Isolation with AC/DC Channel Merging - Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal. | 12-03-2009 |
20090295452 | BOOSTING CIRCUIT - A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (Mā§4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1ā¦Kā¦M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(Kā1) when (Kā1)>0, and KA=M when (Kā1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from āLā to āHā, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented. | 12-03-2009 |
20090302924 | Level shifter capable of improving current drivability - A level shifter circuit is provided that is capable of improving current drivability and executing stable operation with a low voltage by boosting a voltage level of an input signal. The level shifter circuit includes a level shifting unit for producing a boosted voltage by boosting an input signal and shifting a voltage level of the boosted voltage to output an output signal. | 12-10-2009 |
20090315609 | Level shift circuit and power semiconductor device - A level shift circuit includes a drive transistor, a first PMOS transistor, and first and second clamp transistors of PMOS type. The drive transistor, which drives the gate of the high-side NMOS transistor in a power semiconductor device, has a source-drain path coupled between a boot potential generated by a bootstrap circuit provided in the semiconductor device and a source potential of the high-side NMOS transistor. The first PMOS transistor has a source coupled to the boot potential, and a drain coupled to the gate of the drive transistor. The first clamp transistor has a gate coupled to the source potential of the high-side NMOS transistor, and a source coupled to the drain of the first PMOS transistor. The second clamp transistor has a gate coupled to the source potential of the high-side NMOS transistor, and a source coupled to the gate of the first PMOS transistor. | 12-24-2009 |
20090315610 | Integrated Circuit Devices Having Level Shifting Circuits Therein - Level shifting circuits generate multiple tracking signals that are in-phase with an input signal, but are also level-shifted with wider voltage swings relative to the input signal. These input tracking signals are provided as separate inputs to an inverter having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein. A level shifting circuit may include a differential input circuit, which is responsive to true and complementary input signals. A first load circuit is electrically coupled to the differential input circuit. This first load circuit is configured to generate first and second tracking signals at respective first and second nodes therein. These first and second tracking signals are in-phase, level-shifted versions of each other, and have respective voltage swings that are greater than a voltage swing of the complementary input signals. The inverter includes a pull-up transistor responsive to the first tracking signal and a pull-down transistor responsive to the second tracking signal. | 12-24-2009 |
20090322402 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK | 12-31-2009 |
20100001779 | Constant-ON State High Side Switch Circuit - An electrical switching circuit for controlling current flow to an electrical load from a primary power source with a first electrical potential difference relative to a circuit ground comprises: a primary electrical switch coupled between the primary power source and the electrical load with a control input that is responsive to a control signal of predetermined potential difference relative to the electrical load; a primary energy storage device with a low side coupled to the electrical load; a primary switch controller coupled to the primary energy storage unit with a controller output coupled to the primary switch control input that develops a controller output signal that approximates the potential difference across the primary energy storage unit in response to a controller input signal; a secondary electrical energy storage device with a high side and a low side; a controllable electrical switch that toggles the low side of the secondary energy storage device from the circuit ground to the low side of the primary energy storage device; a primary unidirectional current gate coupled between the high side of the secondary energy storage device and the high side of the primary energy storage device to let current flow from the secondary energy storage device to the primary energy storage device when the potential difference of the high side of the secondary energy storage device is higher than the high side of the primary energy storage device; a secondary unidirectional current gate coupled between a secondary power source with an electrical potential difference of at least the predetermined potential relative to the circuit ground and the high side of the secondary energy storage device to let current flow from the secondary power source to the high side of the secondary energy storage device when the potential difference of the secondary power source is higher than the high side of the secondary energy storage device; wherein periodic operation of the secondary electrical switch charges the secondary energy storage device when the secondary switch toggles its low side to the circuit ground and the secondary energy storage device charges the primary storage device when the secondary switch toggles its low side to the low side of the primary energy storage device. | 01-07-2010 |
20100013539 | COMMUNICATION CIRCUIT WITH SELECTABLE SIGNAL VOLTAGE - The disclosed embodiments relate to a communication circuit. An exemplary embodiment of the communication circuit comprises a first branch adapted to operate at a first signal voltage level, a first source voltage contact adapted to deliver a voltage corresponding to the first signal voltage level to the first branch, a second branch adapted to operate at a second signal voltage level that is higher than the first signal voltage level, a second source voltage contact adapted to receive a voltage corresponding to the second signal voltage level via an external connector and to deliver the voltage corresponding to the second signal voltage level to the second branch, and a voltage selection circuit coupled to the first source voltage contact and the second source voltage contact, the voltage selection circuit configured to provide the first signal voltage level to the first branch and the second signal voltage level to the second branch. | 01-21-2010 |
20100019824 | Low Power Level Shifting Latch Circuits With Gated Feedback for High Speed Integrated Circuits - Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage. | 01-28-2010 |
20100019825 | NOVEL SINGLE SUPPLY LEVEL SHIFTER CIRCUIT FOR MULTI-VOLTAGE DESIGNS, CAPABLE OF UP/DOWN SHIFTING - A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage. | 01-28-2010 |
20100026361 | LEVEL SHIFTER AND DRIVING CIRCUIT INCLUDING THE SAME - The present invention related to a driving circuit including a level shifter. The driving circuit according to exemplary embodiment of the present invention includes a first level shifter, a second level shifter, and a gate driver. The first level shifter includes a path along which a pulse-on current flows in response to an on-control signal and a path along which a pulse-off control flows in response to an off-control signal. The second level shifter includes a path along which an on-current flows in response to the on-control signal and a path along which an off-control flows in response to the off-control signal. The gate driver turns on the switch in response to the pulse-on current, maintains the turned-on switch in the turn-on state in response to the on-control current, turns off the switch in response to the pulse-off current, and maintains the turned-off switch in the turn-off state in response to the off-control current. | 02-04-2010 |
20100026362 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal. | 02-04-2010 |
20100026363 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits. | 02-04-2010 |
20100026364 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level. | 02-04-2010 |
20100026365 | ROBUST CURRENT MIRROR WITH IMPROVED INPUT VOLTAGE HEADROOM - An apparatus comprising an input current source device, a first transistor, a second transistor and a level shifter device. The input current source device may provide a input current source. The first transistor may be configured to operate in saturation for mirroring the input current source to an output current source. The first transistor may have (i) a source node connected to a supply, and (ii) a drain connected to the input current source. The second transistor may also be configured to operate in saturation. The second transistor may have (i) a gate connected to a gate of the first transistor, (ii) a source connected to the supply, and (iii) a drain configured as an output current node. The level shifter device may comprise a third transistor, a first bias current source and a second bias current source. | 02-04-2010 |
20100026366 | Low Leakage Voltage Level Shifting Circuit - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level. | 02-04-2010 |
20100033224 | Level Shifter, Standard Cell, System And Method For Level Shifting - Implementations are presented herein that include a level shifter circuit. | 02-11-2010 |
20100033225 | Gate Driving Circuit - A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane. | 02-11-2010 |
20100033226 | Level shifter with output spike reduction - A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs. | 02-11-2010 |
20100033227 | ANALOG SWITCH CONTROLLER - Methods and systems for implementing an analog switch controller to improve linearity of analog switches are described. | 02-11-2010 |
20100045358 | LEVEL SHIFT CIRCUIT - The present invention provides a level shift circuit capable of operating at low input voltage. The level shift circuit comprises: a first switch element coupled to a first output terminal, a second switch element coupled to a second output terminal, a third switch element coupled to the second output terminal and the first output terminal, a fourth switch element coupled to the first output terminal and the second output terminal, a first current source module for letting a current passing through the third switch element smaller than a current passing through the first switch element when the first switch element and the third switch element are conducted, and a second current source module for let a current passing through the fourth switch element smaller than a current passing through the second switch element when the second switch element and the fourth switch element are conducted. | 02-25-2010 |
20100052763 | CMOS Level Shifter Circuit Design - A level shifting circuit has a pair of assist circuits. The level shifting circuit includes an input point, an output point, a pair of cross-coupled PMOS transistors coupled to the output point, and a pair of NMOS transistors coupled between the input and output points. Each assist circuit includes a pair of PMOS transistors, one responsive to an input applied to the input point, the other responsive to the drain voltage of one of the NMOS transistors. The assist circuits temporarily weaken the cross-coupled PMOS transistors when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output. | 03-04-2010 |
20100052764 | LEVEL SHIFTER CONCEPT FOR FAST LEVEL TRANSIENT DESIGN - A driving circuit is provided by the invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between an operation voltage and a power supply terminal of the first buffer for controlling a power-supplying time of the first buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter. | 03-04-2010 |
20100060337 | POWER SUPPLY INSENSITIVE VOLTAGE LEVEL TRANSLATOR - A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off. | 03-11-2010 |
20100060338 | LEVEL SHIFTER WITH REDUCED LEAKAGE - The present invention relates generally to the level shifter circuits and more specifically to improved level shifter circuits providing for reduced leakage current and reduced power consumption. In one or more implementations, a method, apparatus and computer program product for level shifting input voltages by minimizing current leakage of a circuit coupled with an improved level shifting circuit is provided for. In one implementation the method includes providing a low voltage domain of the circuit, and providing for turning off the transistor if the low voltage domain of the circuit is not stable, and turning on the transistor if the low voltage domain of the circuit is stable. | 03-11-2010 |
20100060339 | VOLTAGE LEVEL SHIFTER WITH VOLTAGE BOOST MECHANISM - A voltage level shifter with voltage boost mechanism is disclosed for interfacing two circuit units having different operating voltage swings. The voltage level shifter includes a first inverter, a second inverter, a first capacitor, a second capacitor and a plurality of transistors. The input and power ends of the first inverter function to receive an input voltage and a first voltage respectively. The output end of the second inverter functions to provide an output voltage. When the input voltage is a ground voltage, the output voltage is also a ground voltage; meanwhile, the switches are controlled for charging the first and second capacitors to a second voltage and a third voltage respectively. When the input voltage is the first voltage, a sum voltage of the first, second, and third voltages is furnished to the power end of the second inverter for providing the sum voltage as the output voltage. | 03-11-2010 |
20100079186 | Adaptive Drive Signal Adjustment for Bridge EMI Control - An embodiment of the invention relates to a driver adapted to provide a drive signal with an adjustable waveform for an external bridge to control EMI. The driver includes a detector configured to measure a switching characteristic of a switch in the external bridge to produce the drive signal with an adjustable waveform characteristic. The driver includes an adjustable circuit element to adjust the waveform characteristic in response to the measured switching characteristic. The measured switching characteristic may be a derivative of a voltage of the switch in the bridge such as a derivative of a drain-to-source voltage of a half-bridge circuit. The driver may be formed with an amplifier with an adjustable gain controlled by the signal produced by the detector. The adjustable gain amplifier may be formed with a transistor coupled in series with a leg of a current mirror. | 04-01-2010 |
20100097116 | HIGH SIDE DRIVER WITH SHORT TO GROUND PROTECTION - A protection circuit for a high side driver includes an exclusive-OR gate adapted to receive a first input and a second input, analyze each of the inputs and transmit an output in response to the analysis of the inputs, wherein the first input represents an electric power output of the high side driver and the second input represents a control signal for operating the high side driver, and a switching device adapted to control an electrical output of the high side driver in response to the output of the exclusive-OR gate. | 04-22-2010 |
20100097117 | Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current. | 04-22-2010 |
20100109742 | Level shift circuit - A level shift circuit includes a first resistor with one end connected to GND, a first transistor with a drain and a gate connected to the other end of the first resistor, and a source connected to a first power supply, a second transistor with a source connected to the first power supply, and a gate connected to the drain and the gate of the first transistor, a second resistor with one end connected to a drain of the second transistor, a third transistor with a source connected to the other end of the second resistor, and a gate connected to an input terminal, a first current source connected between a second power supply and a drain of the third transistor; and a fourth transistor connected between an output terminal and the first power supply with a gate connected to the drain of the second transistor. | 05-06-2010 |
20100109743 | LEVEL SHIFTER HAVING NATIVE TRANSISTORS - A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS | 05-06-2010 |
20100109744 | LEVEL SHIFTER HAVING A CASCODE CIRCUIT AND DYNAMIC GATE CONTROL - A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS | 05-06-2010 |
20100109745 | LEVEL CONVERSION CIRCUIT FOR CONVERTING VOLTAGE AMPLITUDE OF SIGNAL - In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the āLā level to the āHā level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the āLā level to the āHā level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the āHā level, which prevents the potential of the node from becoming unstable. | 05-06-2010 |
20100117708 | Voltage Level Converter without Phase Distortion - A voltage level converter with reduced signal phase distortion is provided. The voltage level converter includes a level shifting circuit followed by a unit interval retrieval circuit. The level shifting circuit takes complementary input voltage signals and converts to signals with different voltage levels. The unit interval retrieval circuit responds to the output complementary signals from the level shifting circuit and generates one or more output signals that restore the period of the original input voltage signals with no or negligible phase distortion. | 05-13-2010 |
20100117709 | VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME - A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer. | 05-13-2010 |
20100123505 | ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH. | 05-20-2010 |
20100123506 | MULTISTAGE LEVEL TRANSLATOR - Multistage signal amplification, including level translation, improves signal integrity, e.g., slew rate, complementary signal delay and duty cycle performance, by mirroring complementary output current in an output stage based on a signal developed in an input stage pull-up network. A multistage amplifier may comprise a first stage comprising a differential input circuit coupled, respectively, between first and second inputs and first and second nodes, wherein the first node is coupled to a first pull-up circuit controlled by the first node and the second node is coupled to a second pull-up circuit controlled by the second node; and a second stage comprising a complementary output circuit coupled, respectively, between first and second nodes and first and second outputs, wherein a current mirror sinks essentially the same current at the first output as is sourced at the second output and vice versa. The pull-up network may further comprise a cross-coupled pull-up circuit. | 05-20-2010 |
20100127751 | LEVEL SHIFTER ADAPTIVE FOR USE IN A POWER-SAVING OPERATION MODE - A level shifter adaptive for use in a power-saving operation mode is disclosed for interfacing two circuit units powered by a first supply voltage and a second supply voltage respectively. The level shifter includes a preliminary level shifting circuit and an output auxiliary circuit. With the aid of the two supply voltages, the preliminary level shifting circuit is employed to receive an input signal having a first operating voltage swing and functions to convert the input signal into a first output signal and a second output signal both having a second operating voltage swing. The first output signal and the second output signal have opposite voltage levels relative to each other. The output auxiliary circuit is utilized for retaining the voltage level of the first output signal based on the second supply voltage regardless of whether the level shifter is still powered by the first supply voltage or not. | 05-27-2010 |
20100127752 | LEVEL SHIFTER WITH LOW VOLTAGE DEVICES - A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs. | 05-27-2010 |
20100127753 | Level shift circuit and display device having the same - A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit. | 05-27-2010 |
20100141324 | Mixed-Voltage Tolerant I/O Buffer and Output Buffer Circuit Thereof - An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein. | 06-10-2010 |
20100156498 | LEVEL SHIFTER - A level shifter with high performance, low power and reduced duty cycle distortion. The level shifter includes an input stage having a first circuit coupled to a second circuit. The first circuit includes a first pull up transistor receiving an input signal coupled to a first pull down transistor. The second circuit includes a second pull up transistor coupled to a second pull down transistor. An output of the input stage coupled to a first node in the first circuit. The level shifter further includes an inverter receiving the input signal. An output of the inverter and the second pull down transistor coupled to a second node. An output stage of the level shifter generates an output signal. The output stage includes a first transistor coupled to the first node and a second transistor coupled to the second node. | 06-24-2010 |
20100156499 | LOGIC LEVEL CONVERTER - A logic level converter includes two first electronic switches coupled in a bi-stable flip-flop arrangement having at least one output line, and a forcing circuitry including two second electronic switches to force switching of the first electronic switches in the flip-flop arrangement. The forcing circuitry has an input terminal to receive a logic input signal having a given level to produce switching of the flip-flop arrangement and generate at the output line(s) of the flip-flop arrangement, a logic output signal(s) whose voltage level is converted with respect to the level of the logic input signal. The converter includes, interposed between each of the two first electronic switches in the flip-flop arrangement and a respective one of the second electronic switches in the forcing circuitry, at least one respective cascode electronic switch to limit the voltage across the two first electronic switches in the flip-flop arrangement. | 06-24-2010 |
20100156500 | SEMICONDUCTOR DEVICE, OUTPUT CIRCUIT AND METHOD FOR CONTROLLING INPUT/OUTPUT BUFFER CIRCUIT IN SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having an output circuit that may be used to advantage in case the semiconductor device may possibly be used under different power supply voltages. The semiconductor device includes a signal terminal having at least the function of an output terminal, a power supply terminal, and an output circuit having first and second output buffer circuits. The first and second output buffer circuits are supplied with a supply power voltage from the power supply terminal and receive an inner output signal to drive the signal terminal. The semiconductor device also includes a power supply voltage discrimination circuit that discriminates the potential level of the power supply voltage to control the operation of the output circuit based on the result of discrimination. A first output buffer circuit is activated and a second output buffer circuit is deactivated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a first potential. Both of the first and second output buffer circuits are activated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a second potential. | 06-24-2010 |
20100164591 | POWER DETECTION SYSTEM AND CIRCUIT FOR HIGH VOLTAGE SUPPLY AND LOW VOLTAGE DEVICES - A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage. | 07-01-2010 |
20100164592 | LEVEL SHIFT CIRCUIT - A level shift circuit. A level shift circuit may include a first voltage supply control unit connected to a first voltage terminal to control a supply of a first voltage via a first and/or second path according to statuses of first and/or second input signals inputted differentially, a second voltage supply control unit connected to a second voltage terminal to control a supply of a second voltage via a first and/or second path, a switching unit controlling a connection between first and second voltage supply control units on a first and/or second path, and/or a buffer unit outputting an output signal corresponding to a first voltage and/or a second voltage in response to a first potential outputted between a first voltage supply control unit and a switching unit and/or a second potential output between a second voltage supply control unit and a switching unit. | 07-01-2010 |
20100164593 | FAST DIFFERENTIAL LEVEL SHIFTER AND BOOT STRAP DRIVER INCLUDING THE SAME - A boot strap driver including a fast differential level shifter are disclosed. The fast differential level shifter may include a first differential amplifier differentially amplifying a pulse width modulation signal and an inverted pulse width modulation signal and outputting a first differential amplification voltage and a second differential amplification voltage based on the amplified result. The fast differential level shifter may also include a second differential amplifier differentially amplifying the first differential amplification voltage and the second differential amplification voltage, and shifting the differential amplification voltages to voltages having an output range between a first voltage and a second voltage based on the amplified result. | 07-01-2010 |
20100176864 | LEVEL SHIFTER CIRCUIT - A level shifter circuit is disclosed. The circuit receives a digital input signal characterized by a logical high state having a first high voltage level and generates an output node for driving a digital output signal characterized by a logical high state having a second high voltage level. The output signal logical state mirrors the input signal logical state. The circuit includes a short circuit current reduction mechanism for charging a first internal node of level shifter circuit following a first transition of the input signal logical state. The circuit further includes a performance enhancement mechanism for discharging the first internal node of the level shifter circuit following a second transition of the input signal logical state. The performance enhancement mechanism may comprise a transistor driven by the input signal and connected between the first internal node and ground. The current limiting mechanism may comprise a transistor having a source/drain terminal connected to the first internal node. | 07-15-2010 |
20100188131 | LEVEL SHIFTER FOR CHANGE OF BOTH HIGH AND LOW VOLTAGE - A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit. | 07-29-2010 |
20100201425 | LEVEL SHIFT CIRCUIT - A level shift circuit includes: a first transistor coupled to a first reference voltage for receiving a first voltage input signal; a second transistor coupled to a second reference voltage; a first diode-connected transistor coupled between the second transistor and the first diode-connected transistor; a third transistor coupled to the first reference voltage and the second transistor, for receiving a second voltage input signal, wherein the first voltage input signal is an inverse version of the second voltage input signal; a fourth transistor coupled to the second reference voltage and the first transistor; a second diode-connected transistor coupled between the fourth transistor and the third transistor; and a fifth transistor coupled to the second voltage input signal, the first reference voltage, and the fourth transistor, wherein a level-shifted output signal corresponding to the first voltage input signal is generated at an output node of the fourth transistor. | 08-12-2010 |
20100201426 | LEVEL SHIFTER CIRCUIT - A level shifter circuit converts a signal generated by an internal circuit which operates with a first power supply, into a signal by a second power supply having voltage higher than that of the first power supply. The voltages at substrate terminals of two NMOS transistors, to which complementary two signals by the first power supply are input, is boosted to voltage higher than circuit ground potential in a period in which a voltage level of one of the two input signals and a voltage level of an output signal by the second power supply do not coincide with each other. | 08-12-2010 |
20100201427 | Level Shifter Circuits For Integrated Circuits - A level shifter circuit for integrated circuits has one or more inputs that operate in a first voltage domain, and a signal output that operates in a second voltage domain. In some embodiments, the level shifter circuit receives two complementary input signals. The level shifter uses cross-coupled PMOS transistors with drain-bulk breakdown voltage less than the gate-oxide breakdown voltage of high-voltage PMOS transistors to prevent gate-oxide breakdown caused by sub-threshold leakage of auxiliary high-voltage PMOS transistors in the off state. Permanent gate-oxide breakdown is prevented through non-permanent sub-nanoamp drain-bulk junction breakdown. The level shifter circuit has the advantages of small circuit size and low static power consumption. | 08-12-2010 |
20100214000 | Systems and Methods for Driving High Power Stages Using Lower Voltage Processes - In today's environment class-D amplifiers are used to provide an integrated solution for applications such as powered audio devices due to their advantages in power consumption and size over more traditional analog amplifiers. Due to power output requirements, the output stages of power drivers such as class-D amplifiers require a supply voltage in excess of the technologically allowed voltage for the switches in the output stage. A level shifter is used to ensure voltages supplied to the output switches do not exceed the technological limits. An ideal level shifter should provide the optimal voltage swing to output switches under all process, supply voltage and temperature (PVT) variations. The ideal level shifter should also provide fast transitions when the control signal changes from high to low and low to high. | 08-26-2010 |
20100214001 | Level Shift Circuit - A level shift circuit includes an inverter, a shifting circuit, a first transistor, and a second transistor. The inverter inverts an original input signal into an inverted input signal. The shifting circuit generates a control signal according to the original input signal, the inverted input signal, and a reference voltage. The first transistor has a gate, a source, and a drain, in which the gate of the first transistor receives the control signal, and the source of the first transistor is connected to a high supply voltage. The second transistor has a gate, a source, and a drain, in which the gate of the second transistor receives the inverted input signal, the drain of the second transistor is connected to the drain of the first transistor, and the source of the second transistor is connected to a ground terminal or a low supply voltage. | 08-26-2010 |
20100214002 | SIGNAL LEVEL CONVERSION CIRCUIT - A signal level conversion circuit includes three or more level shift circuits to output internal output signals upon receiving input signals, respectively. Each of the level shift circuits is formed of a common electrical element and an electrical element connected to the common electrical element. A voltage higher than that supplied to the common electrical element is supplied to the electrical element. A buffer circuit having an input tolerant function is provided in each of the common electrical elements. The internal output signals are set at lower level than the input signals by the buffer circuits, and the internal output signal outputted from one of the level shift circuits is further outputted via other level shift circuits. | 08-26-2010 |
20100219873 | SIGNAL SOURCE DEVICES - A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units. The voltage-shifting unit has a first terminal coupled to the inverter unit and one of the latch units and a second terminal receiving a first input signal, for shifting a voltage level at the first terminal according to the first input signal. | 09-02-2010 |
20100219874 | LEVEL SHIFT CIRCUIT AND SWITCHING CIRCUIT INCLUDING THE SAME - The level shift circuit that converts a level of an input signal into a level between a first and a second voltage, which is higher than the first voltage includes a select circuit that generates an oscillation signal, where at least a frequency or an amplitude of the oscillation signal changes according to an input signal, a filter circuit that removes a DC component of the oscillation signal output from the select circuit and outputs an AC component, a detect circuit that operates between the first voltage and an output side voltage of the filter circuit, and generates a control signal including a signal voltage that changes according to at least a frequency or an amplitude of the AC component of the oscillation signal, and an output circuit that generates an output signal having a level between the first voltage and the second voltage according to the control signal. | 09-02-2010 |
20100244923 | SEMICONDUCTOR DEVICE - A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node. | 09-30-2010 |
20100244924 | SEMICONDUCTOR DEVICE - A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply. | 09-30-2010 |
20100259311 | LEVEL SHIFTERS, INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR OPERATING THE LEVEL SHIFTERS - A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor. | 10-14-2010 |
20100264975 | Level Shifter with Rise/Fall Delay Matching - In one embodiment, a level shifter circuit is provided that may include approximately matched rising edge and falling edge delays through the level shifter. The level shifter may also have a low delay and low power consumption. The level shifter circuit may include a pair of low voltage input inverters coupled to a pulldown transistor, where a node between the low voltage input inverters is coupled through another pulldown stack to a pullup transistor. Including an output inverter, both rising transitions and falling transitions may include about 4 gate delays in one embodiment. The level shifter may include keeper transistors to turn off the pullup transistor after the pullup is performed, and the pulldown transistor may be turned off as the pullup transistor is turned on. The pullup and pulldown transistors may not drive against each other during operation, which may reduce power consumption in the circuit. | 10-21-2010 |
20100264976 | Circuitry for processing signals from a higher voltage domain using devices designed to operate in a lower voltage domain - An apparatus is disclosed for receiving input signals in a first higher voltage domain and for generating and outputting signals in a second lower voltage domain, said apparatus comprising: an input pad for receiving said input signals in said first higher voltage domain; output circuitry comprising a plurality of devices arranged between a high voltage source of said second lower voltage domain and a low voltage source, said plurality of devices being arranged in a first set and a second set, said first set being arranged between said high voltage source and said output and said second set being arranged between said output and said low voltage source, said output circuitry being configured to switch to output a first predetermined value in response to a rising input signal exceeding an upper threshold value and to switch to output a second predetermined value in response to a falling input signal falling below a lower threshold value; a first input path for sending said received input signals to a first input of said first set; a second input path for sending said received input signals to a second input of said second set; wherein said second input path comprises a switch delay device for reducing a voltage of said received input signal such that on a rising input signal, said input signal has reached a higher value when said output circuitry switches in response to said input signal than it would have reached had said input signal voltage not been reduced; and a controllable connecting path between said first and second inputs for connecting said first and second inputs together in response to detection of said first predetermined value at said output and for not connecting said first and second inputs together in response to detection of said second predetermined value at said output. | 10-21-2010 |
20100264977 | Cascoded level shifter protection - A cascoded level shifter for receiving an input signal in a low voltage range and for generating an output signal in a high voltage range is disclosed. The cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range, the cascoded level shifter comprising: an input node configured to receive an input signal; a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device comprising a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal; and reference voltage perturbation circuitry, configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch. | 10-21-2010 |
20100271103 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown. | 10-28-2010 |
20100271104 | IMAGE SIGNAL INPUT CIRCUIT - An image signal input circuit includes an input terminal configured to receive an image signal, a clamp circuit configured to hold a sink chip voltage contained in the image signal to be a constant value, a level shift circuit that includes a first emitter follower having a first transistor and a first current source, and a second emitter follower having a second transistor and a second current source, a base of the second transistor being connected to an emitter of the first transistor, and that is configured to shift a level of the sink chip voltage which is held constant, and an electric current source configured to attract a base current of the first transistor. | 10-28-2010 |
20100271105 | High Boosting-Ratio/Low-Switching-Delay Level Shifter - A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor. | 10-28-2010 |
20100277215 | Wideband Voltage Translators - In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth. | 11-04-2010 |
20100277216 | I/O Buffer Circuit - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 11-04-2010 |
20100289552 | SYSTEMS INCLUDING LEVEL SHIFTER HAVING VOLTAGE DISTRIBUTOR - An exemplary embodiment of such a system includes: a level shifter operative to transform an input signal into an output signal, the level shifter includes: a voltage distributor operative to receive the input signal and distribute potential levels at a first node and a second node to respectively output a first signal and a second signal, and the voltage distributor includes: a current limiter, operative to provide a limited current passing through the first node; a switch, operative to selectively establish an electrical connection between the first node and the second node; and a first transistor having a first electrode, a second electrode, and a first control electrode, wherein the first electrode is connected to the second node, the second electrode is utilized to receive the input signal, and the first control electrode is coupled to the first node; and an output circuit, operative to generate the output signal. | 11-18-2010 |
20100295596 | LEVEL SHIFT CIRCUIT - A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit | 11-25-2010 |
20100301917 | LEVEL SHIFT CIRCUIT - The invention provides a level shift circuit that prevents an offset when the supply voltage changes. A level shift circuit has a differential amplification circuit, a current generation circuit, a capacitor and a holding circuit. An input signal from the optical pickup is inputted to the non-inversion input terminal of the differential amplification circuit. First, by turning on a first switch, a feedback loop is formed by the differential amplification circuit, the current generation circuit and the capacitor to perform a level shift, and the voltage charged in the capacitor is held by the holding circuit. Then by turning off the first switch and turning on a second switch, the voltage held by the holding circuit is applied to the non-inversion input terminal of the differential amplification circuit to perform a level shift. | 12-02-2010 |
20100301918 | Level Shifter and Level Shifting Method Thereof - A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage. | 12-02-2010 |
20100308887 | APPARATUS AND METHOD FOR TESTING LEVEL SHIFTER VOLTAGE THRESHOLDS ON AN INTEGRATED CIRCUIT - An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage. | 12-09-2010 |
20100308888 | Driver circuit - A driver circuit including a pre-driver B | 12-09-2010 |
20100315150 | VOLTAGE LEVEL SHIFTER FOR ARBITRARY INPUT SIGNALS - Methods, systems, and devices are described for providing voltage level shifting that may operate reliably and at low power, even at high voltages and/or high switching frequencies. Embodiments receive an input signal representing input information, and effectively generate two voltage responses as a function of the input signal. Each voltage response includes exponential terms as a function of resistive and capacitive loading effects of components of the embodiments. A combined response signal is generated substantially as a superposition of the first response signal and the second response signal. A high-side driver signal is then generated as a function of the combined response signal, such that the high-side driver signal substantially preserves the input information represented by the input signal, and such that the first exponential response and the second exponential response are substantially absent from the high-side driver signal. | 12-16-2010 |
20100321083 | Voltage Level Translating Circuit - A voltage level translating circuit that allows low voltage signals to be translated to higher voltages, a design structure utilized in the design, manufacture, and/or testing of the voltage level translating circuit, and a method of manufacturing the voltage level translating circuit are described. The translating circuit utilizes two different voltage domains. The high voltage rail of the low voltage domain acts as the ground of the high voltage domain. The translating circuit also utilizes a voltage buffer electrically connected to the high voltage domain and to the low voltage domain to prevent the circuit devices in either domain from seeing too high of a voltage. The translating circuit allows the circuits after the translating circuit to work with signals utilizing the high voltage rail of the high voltage domain. | 12-23-2010 |
20100321084 | Level shift circuit - A level shift circuit includes a level shift voltage generation circuit that receives an input signal having an amplitude between a first voltage system power supply voltage and a ground potential and outputs an output signal voltage having an amplitude between a second voltage system power supply voltage and the ground potential, a replica circuit configured to be a replica of the level shift voltage generation circuit, the replica circuit monitoring a threshold voltage of a first voltage system and a threshold voltage of a second voltage system, and enabling the level shift voltage generation circuit to generate of the output voltage synchronized in such a manner that, when the input voltage crosses the logic threshold of the first voltage system, the output voltage crosses the logic threshold of the second voltage system, and a bias generation circuit that generates a bias for adjusting variations of the output voltages of the level shift voltage generation circuit and the replica circuit, and supplies the bias to the level shift voltage generation circuit and the replica circuit. | 12-23-2010 |
20110001538 | Voltage level shifter - A voltage level shifter is provided for receiving an input signal from an input voltage domain and converting said signal to a shifted signal in a shifted voltage domain. The voltage level shifter has an input, switching circuitry, a pass transistor and an output. The switching circuitry is configured to isolate an output of said pass transistor from said supply voltage rail when said input voltage domain corresponds to a logical zero. | 01-06-2011 |
20110006828 | DIFFERENTIAL TYPE LEVEL SHIFTER - This patent discloses a differential type level shifter, comprising: a differential pair of transistors, having a pair of gate terminals, a pair of drain terminals and a common source terminal, with the pair of gate terminals coupled to a first clock signal and a second clock signal; a current source, coupled between the common source terminal and a reference ground, used to provide a bias current; and a pair of loading resistors, having a common end and a pair of output ends, with the common end coupled to a power line, the pair of output ends coupled to the pair of drain terminals; wherein the pair of drain terminals are used to generate a set signal and a reset signal in response to the first clock signal and the second clock signal. | 01-13-2011 |
20110018606 | LEVEL SHIFTERS AND HIGH VOLTAGE LOGIC CIRCUITS - Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes a driver circuit and a latch. The driver circuit receives an input signal having a first voltage range and provides a drive signal having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal having the second voltage range. The driver circuit may generate a control signal having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit. | 01-27-2011 |
20110025397 | DRIVER CIRCUIT FOR GALLIUM NITRIDE (GaN) HETEROJUNCTION FIELD EFFECT TRANSISTORS (HFETs) - A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state. | 02-03-2011 |
20110025398 | Level Shifting Circuit - A level shifting circuit including a driving circuit, a reset circuit, a coupling circuit and an output-stage circuit is provided. The driving circuit, controlled by the input signal, controls the first driving signal having a high voltage level in the first period and controls the first driving signal having a low reference level in the second period. The reset circuit, controlled by the first driving signal in the first period, resets the second driving signal having the low reference level. The coupling circuit, controlled by the falling edge of the input-inversed signal, controls the second driving signal having a low voltage coupling level in the second period. The output-stage circuit, controlled by the first and the second driving signal, controls the output signal having a high voltage level in the second period and controls the output signal having a low voltage level in the first period. | 02-03-2011 |
20110025399 | AMPLITUDE CONVERSION CIRCUIT - In an amplitude conversion circuit that converts an input signal having a small amplitude into an output signal having a large amplitude, the input signal is supplied to a gate of a transistor that discharges an output terminal through a capacitance element. A charging/discharging circuit causes a gate voltage of the transistor to be substantially equal to a threshold voltage during an inactive period of the input signal. | 02-03-2011 |
20110032019 | LEVEL SHIFTER WITH OUTPUT LATCH - A level shifter for a microcontroller shifts an input voltage in a first power domain to an output voltage level consistent with a second power domain. The level shifter is enabled to shift the voltages when both power domains are operative. | 02-10-2011 |
20110032020 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 02-10-2011 |
20110037508 | REGISTERS WITH REDUCED VOLTAGE CLOCKS - A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level. | 02-17-2011 |
20110037509 | APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT - An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element. | 02-17-2011 |
20110043268 | LEVEL SHIFTER WITH NATIVE DEVICE - A level shifter includes an inverter, a first native device, a second native device, a first transistor, and a second transistor. First ends of the first and the second transistors are coupled to a first voltage. A second end and a control end of the first transistor are respectively coupled to the first ends of the first and the second native devices. A second end and a control end of the second transistor are respectively coupled to the first ends of the second and the first native devices. A second end and a control end of the first native device are respectively coupled to an output end and an input end of the inverter. A second end and a control end of the second native device are respectively coupled to the input end and the output end of the inverter. | 02-24-2011 |
20110043269 | Level shift circuit - In a level shift circuit in a high electric potential side driving circuit, a latch circuit and a transmission circuit located at the front stage of the latch circuit are provided. The transmission circuit makes its output impedance high when two inputs V | 02-24-2011 |
20110050317 | BOOTSTRAP CIRCUIT - A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor. | 03-03-2011 |
20110050318 | HIGH VOLTAGE DIFFERENTIAL PAIR AND OP AMP IN LOW VOLTAGE PROCESS - A high voltage differential pair and op amp implemented in a low voltage semiconductor process. The high voltage differential pair expands the incoming common mode voltage of a differential pair to multiple times the normal operating voltage of the differential pair through the use of high voltage current sources, current sinks and stacks of transistors. The high voltage op amp includes a high voltage input stage and a high voltage common source amplifier to expand the output voltage range to multiple times the normal operating voltage of the op amp. | 03-03-2011 |
20110057708 | Semicondutor Integrated Circuit Device - A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost. | 03-10-2011 |
20110063012 | CIRCUIT ARRANGEMENT - A circuit arrangement is provided. The circuit arrangement includes a first transistor, a second transistor, a third transistor, and a fourth transistor respectively comprising a first terminal, a second terminal, and a control terminal, a first capacitor and a second capacitor respectively comprising a first terminal and a second terminal, an inverter comprising an input terminal and an output terminal, and a circuit arrangement input terminal and a first circuit arrangement output terminal, wherein the first terminals of the first transistor, the second transistor and the third transistor are connected with each other, wherein the second terminal of the first transistor is connected to the control terminal of the second transistor and to the first terminal of the first capacitor, and wherein the second terminal of the second transistor is connected to the control terminal of the first transistor, to the control terminal of the third transistor, and to the first terminal of the second capacitor, wherein the second terminal of the first capacitor is connected to the input terminal of the inverter, and wherein the second terminal of the second capacitor is connected to the output terminal of the inverter, wherein the output terminal of the inverter is connected to the control terminal of the fourth transistor, wherein the second terminal of the third transistor is coupled to the first terminal of the fourth transistor, wherein the circuit arrangement input terminal is connected to the input terminal of the inverter, wherein the first circuit arrangement output terminal is connected between the second terminal of the third transistor and the first terminal of the fourth transistor. | 03-17-2011 |
20110074485 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit is provided in which no error signal is generated even when the circuit is exposed to a transient voltage noise that occurs with a transition from a first state indicating a conduction of a high-potential side switching device to a second state indicating a non-conduction of the high potential side switching device, or vice versa. A high potential switching device drive circuit | 03-31-2011 |
20110074486 | METHOD AND APPARATUS FOR TRACKING POWER SUPPLIES - A method for tracking power supplies includes the following steps: receiving, by a controller, a signal to be tracked and outputting, according to the signal to be tracked, a control signal. The control signal controls at least two sets of voltage level selection circuits in selecting at least one tracking voltage level from at least two groups of isolation voltage levels and controls each set of the voltage level selection circuits selecting at most one tracking voltage level from a group of isolation voltage levels. An isolation power supply provides the at least two groups of isolation voltage levels according to the voltage level interval of the signal to be tracked. Each group of isolation voltage levels includes at least two tracking voltage levels. The voltage level selection circuits provide the selected tracking voltage level to supply power to a load circuit. An apparatus for tracking power supplies is also provided. The present disclosure is applicable to the power supply tracking on a reference signal. | 03-31-2011 |
20110095804 | Apparatus and method providing an interface between a first voltage domain and a second voltage domain - An interface between first and second voltage domains is provided. A level shifter is configured to receive an input signal from the first voltage domain and to level shift the input signal to provide an output signal for passing to the second voltage domain. A control signal generator is configured to generate a second voltage domain control signal in dependence on at least one first voltage domain control signal from a controller in the first voltage domain. The level shifter is configured to be in a retention state when the second voltage domain control signal has a first value, such that its output signal is held constant even when the controller becomes not actively driven by the first voltage supply. The level shifter is configured to be in a transmission state when the second voltage domain control signal has a second value, wherein the output signal depends on the input signal. | 04-28-2011 |
20110095805 | LEVEL SHIFTERS AND INTEGRATED CIRCUITS THEREOF - An integrated circuit includes a level shifter configured to receive a first voltage signal that swings between a first voltage level and a second voltage level, outputting a second voltage signal that swings between the first voltage level and a third voltage level. The third voltage level is higher than the second voltage level. An inverter is coupled with the level shifter. The inverter can receive the second voltage, outputting a third voltage signal that swings between the third voltage level and a fourth voltage level. The fourth voltage level is lower than the third voltage level and higher than the first voltage level. | 04-28-2011 |
20110095806 | SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a voltage generator, a driver, a switch section, and a power supply controller. The voltage generator is configured to generate a first potential and a negative second potential. The first potential is higher than a power supply voltage supplied to a power supply terminal. The driver is connected to an output of the voltage generator and includes a first level shifter and a second level shifter. The first level shifter is configured to output the first potential in response to input of high level and to output low level in response to input of low level. The second level shifter is configured to output the first potential in response to input of the first potential an output of the first level shifter and to output the second potential in response to input of low level of the output of the first level shifter. The switch section is configured to switch connection between terminals in response to an output of the driver. The power supply controller is configured to control the output of the voltage generator to be connected to the power supply terminal during a first period after supplying the power supply voltage to the power supply terminal and control the output of the voltage generator to be disconnected from the power supply terminal after expiration of the first period. | 04-28-2011 |
20110109369 | Low voltage input level shifter circuit and method for utilizing same - According to one embodiment, a level shifter circuit operable with a low voltage input comprises first and second pull-down switches configured to receive the low voltage input as respective non-inverted and inverted control voltages, first and second pull-up switches coupled between the respective first and second pull-down switches and an output supply voltage, and a pull-up boost switching stage coupled to a node between the first pull-up switch and the first pull-down switch. The pull-up boost switching stage is configured to turn ON in response to the second pull-down switch turning ON, and to turn OFF before the first pull-up switch turns OFF. In one embodiment, the level shifter circuit may be implemented as part of an input/output (IO) pad of an integrated circuit (IC) fabricated on a semiconductor die. | 05-12-2011 |
20110109370 | Level Converter - A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal. | 05-12-2011 |
20110115541 | APPARATUSES AND METHODS FOR A LEVEL SHIFTER WITH REDUCED SHOOT-THROUGH CURRENT - A level shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time. | 05-19-2011 |
20110115542 | LEVEL SHIFT CIRCUIT AND SWITCHING POWER SOURCE APPARATUS - A level shift circuit includes a first resistor connected to a level shift power source, a first transistor having a drain connected to a second end of the first resistor and a source to the ground, a second resistor connected to the level shift power source, a second transistor having a drain connected to a second end of the second resistor and a source to the ground, a pulse generator controlling ON/OFF of the first and second transistors according to an input signal, a control part generating a set signal if the first transistor is ON, a reset signal if the second transistor is ON, and no signal if there is no voltage difference between a voltage at the drain of the first transistor and a voltage at the drain of the second transistor, and a flip-flop providing an output signal according to the set and reset signals. | 05-19-2011 |
20110128063 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal. | 06-02-2011 |
20110133810 | System and Method for a Semiconductor Switch - In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node. | 06-09-2011 |
20110133811 | CLOCK DISTRIBUTION NETWORK - Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components. | 06-09-2011 |
20110169543 | SYSTEM AND METHOD OF CONTROLLING DEVICES OPERATING WITHIN DIFFERENT VOLTAGE RANGES - Semiconductor devices, systems, and methods are disclosed to facilitate power management. A semiconductor device includes a first voltage island configured to operate within a first voltage range, where the first voltage range has a first midpoint. A second voltage island of the semiconductor device is configured to operate within a second voltage range, where the second voltage range has a second midpoint. The first voltage range is different than the second voltage range, and the first midpoint is substantially equal to the second midpoint. | 07-14-2011 |
20110169544 | SOURCE DRIVER - A source driver, which has a first resistor string, a first digital-to-analog converter, and a channel buffer, is provided. The first resistor string has a plurality of resistors connected in series, wherein each of the resistors of the first resistor string provides a corresponding gamma voltage. The first digital-to-analog converter is coupled to the resistors of the first resistor string. The digital-to-analog converter selectively outputs one of gamma voltages provided by the resistors as a first output voltage according to a data code. The channel buffer is coupled to an output terminal of the first digital-to-analog converter to output a second output voltage by shifting a voltage level of the first output voltage. | 07-14-2011 |
20110175663 | GAMMA VOLTAGE GENERATION CIRCUIT - A gamma voltage generation circuit is provided. An offset voltage generator generates a first offset voltage by dividing a voltage difference between a first input voltage and a second input voltage based on a first code. A first voltage shifting circuit of a voltage level shifter shifts down a first reference voltage by the first offset voltage to output a first level-shifted voltage. A second voltage shifting circuit of the voltage level shifter shifts down a second reference voltage by the first offset voltage to output a second level-shifted voltage. Each of resistors of a resistor string outputs one of the gamma voltages. A first end and a second end of the resistor string are respectively coupled to a first output terminal and a second output terminal of the voltage level shifter. | 07-21-2011 |
20110175664 | ELECTRONIC CIRCUIT - A power-supply sequence-free electronic circuit is realized without the increase of the number of power supply detectors for detecting the rising of the power supply. The electronic circuit operated by supplying three or more types of power supply voltages to the ground voltage of the circuit generates a first detection signal indicating whether any one of other power supply voltages does not rise by a first detection circuit which is operated with a predetermined power supply voltage as an operation power supply. The electronic circuit generates a second detection signal indicating whether the predetermined power supply voltage rises by a second detection circuit which is provided for each of the other power supply voltages and operated with one power supply voltage of the other power supply voltages as an operation power supply. The electronic circuit generates a control signal for ensuring the rising of other power supply voltages for each of the other power supply voltages based on the first and second detection signals. | 07-21-2011 |
20110175665 | INTEGRATED CIRCUIT CONNECTION DEVICE - The integrated circuit connection device ( | 07-21-2011 |
20110181338 | Dual path level shifter - Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters. | 07-28-2011 |
20110181339 | LEVEL SHIFT CIRCUIT - A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level. | 07-28-2011 |
20110181340 | Fast Voltage Level Shifter Circuit - A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate. | 07-28-2011 |
20110181341 | PUSH-PULL DRIVER CIRCUIT - A push-pull driver circuit includes a control circuit which controls switching operations of a plurality of high-side transistors, a level-shift circuit which shifts a control signal, output by the control circuit when the control circuit performs turn-off control on the plurality of transistors, to a first voltage by which the plurality of transistors are turned off, and which inputs the shifted signal to a gate of one of the plurality of transistors, and a conduction-state selection circuit which, if an output of the level-shift circuit is the first voltage, inputs the output to gates of the rest of the transistors, and otherwise, according to the control by the control circuit, sets each of gate inputs of the rest of the transistors to either a high-impedance state or a second voltage by which the plurality of transistors are turned on. | 07-28-2011 |
20110193609 | Voltage Level Shifter with Dynamic Circuit Structure having Discharge Delay Tracking - In a particular embodiment, an apparatus includes a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit. | 08-11-2011 |
20110204953 | LEVEL SHIFTER CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit. | 08-25-2011 |
20110204954 | Voltage Level Shifter - A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved. | 08-25-2011 |
20110210781 | LEVEL SHIFTER - A level shifter ( | 09-01-2011 |
20110221502 | TESTABLE INTEGRATED CIRCUIT AND TEST METHOD THEREFOR - Disclosed is an integrated circuit ( | 09-15-2011 |
20110227626 | LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT - In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes. | 09-22-2011 |
20110234291 | Level shifter - A level shifter converts an input signal having an amplitude between a ground and a first power supply voltage into an output signal having an amplitude between the ground and a second power supply voltage. The level shifter includes an input unit, driven by the first power supply voltage, that raises a first pulse signal at a rise of the input signal and raises a second pulse signal having the same polarity as the first pulse signal at a fall of the input signal, and a level shift unit that converts a signal level of the first pulse signal into an amplitude level of the second power supply voltage, and converts a signal level of the second pulse signal into an amplitude level of the second power supply voltage. | 09-29-2011 |
20110241754 | LEVEL SHIFTER AND METHOD OF CONTROLLING LEVEL SHIFTER - A level shifter converts an input signal changing between a first potential level and a second potential level into an output signal changing between the first potential level and a third potential level. The level shifter includes: a first circuit configured to be able to hold a potential at an input terminal to which the input signal is input at the first potential level; and a second circuit configured to be able to hold a potential at an output terminal from which the output signal is output at the first potential level. | 10-06-2011 |
20110260770 | METHOD AND SEMICONDUCTOR DEVICE FOR MONITORING BATTERY VOLTAGES - A semiconductor device for monitoring batteries or cells connected in series has a selector switch that selects one of the batteries or cells and outputs voltages obtained from its positive and negative terminals. A pair of buffer amplifiers receives these voltages at high-impedance input terminals and output corresponding voltages to a level shifter. The level shifter generates an output voltage equal to the difference between the outputs of the buffer amplifiers. By preventing current flow between the selector switch and the level shifter, the buffer amplifiers reduce the output droop that occurs at the beginning of a voltage measurement, even if the semiconductor device is connected to the batteries or cells through a low-pass filter circuit with a comparatively large time constant. Measurement time is shortened accordingly. | 10-27-2011 |
20110273219 | VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage. | 11-10-2011 |
20110285448 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a level shift circuit which is located so that a second IO cell region is interposed between the level shift circuit and a first IO cell region, and converts a signal output from an IO cell of the first IO cell region into a signal having an amplitude of a second voltage and outputs the resultant signal, and an internal circuit which is operated using the signal having the amplitude of the second voltage output from the level shift circuit. A signal interconnect via which the signal output from the IO cell of the first IO cell region is input to the level shift circuit is provided between the IO cell of the first IO cell region and the level shift circuit, extending over or in an IO cell of the second IO cell region. | 11-24-2011 |
20110285449 | APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT - An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element. | 11-24-2011 |
20110298519 | LEVEL SHIFTER - The present invention provides a level shifter. In an embodiment, the level shifter includes first to sixth transistors. The first and second transistors have common control nodes coupled to a first bias voltage, receive a pair of input signals and respectively provide a first output node and a second output node. The fifth and sixth transistors have common control nodes coupled to a second bias voltage to form a current mirror. The third transistor is coupled between the first and the fifth transistors and has a control node coupled to the second output node. The fourth transistor is couple between the second and the sixth transistors and has a control node coupled to the first output node. | 12-08-2011 |
20110309873 | CIRCUIT HAVING GATE DRIVERS HAVING A LEVEL SHIFTER - A circuit comprises a first level shifting circuit. The level shifting circuit comprises a first and second latching differential pairs. The first latching differential pair has first and second inputs for receiving first and second input signals, first and second outputs, and first and second power supply voltage terminals for receiving a first power supply voltage. The second latching differential pair has first and second inputs coupled to the first and second outputs of the first latching differential pair, an output, and first and second power supply voltage terminals for receiving a second power supply voltage, the second power supply voltage being different from the first power supply voltage. In one embodiment, the level shifting circuit protects transistor gates of the circuit from an overvoltage. | 12-22-2011 |
20110316604 | INPUT BUFFER CIRCUIT - An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal. | 12-29-2011 |
20110316605 | CIRCUIT APPARATUS AND SYSTEM - A circuit apparatus includes an output circuit that outputs a signal to a host apparatus via a bus, and an output control circuit that controls the output circuit. The output circuit has a first conductive transistor provided between an output node and a first power source node, and a second conductive transistor provided between the output node and a second power source node. In a first output mode, the output control circuit controls one of the first conductive transistor and the second conductive transistor to go to off and controls the other transistor to go to on/off, whereas in a second output mode, the output control circuit controls the first conductive transistor to go to on and the second conductive transistor to go to off or vice versa. | 12-29-2011 |
20120001672 | Apparatuses and methods for a voltage level shifting - Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal. | 01-05-2012 |
20120001673 | LOW POWER FAST LEVEL SHIFTER - A lever shifter is provided for receiving a signal in a first voltage domain and providing an output signal in a second voltage domain. The level shifter reduces propagation delay and power consumption by mitigating contention between NFETs and PFETs during signal propagation. | 01-05-2012 |
20120013386 | LEVEL SHIFTER - A level shifter includes an output stage transistor and a level controller. The level controller receives a selection signal and provides a reference voltage at a gate terminal of the output stage transistor based on the selection signal. The output stage transistor, on being enabled by the reference voltage, provides a first level shifted output based on a first output reference voltage. | 01-19-2012 |
20120019302 | LOW MINIMUM POWER SUPPLY VOLTAGE LEVEL SHIFTER - A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0. | 01-26-2012 |
20120019303 | DC - DC CONVERTER - The invention relates to a DC-DC converter adapted to supply a MEMS device comprising an input for receiving a DC voltage (Vs), an output for transmitting a supplied voltage (V | 01-26-2012 |
20120025892 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK | 02-02-2012 |
20120032724 | CIRCUIT AND METHOD FOR GENERATING PUMPING VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node. | 02-09-2012 |
20120044008 | LEVEL SHIFTERS FOR IO INTERFACES - A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device. | 02-23-2012 |
20120044009 | Level-Shifting Latch - A level-shifting latch circuit is disclosed. The level-shifting latch circuit may provide a level-shifting function, a data state retention function, and a dynamic-to-static conversion function. The level-shifting latch may receive two input signals from a dynamic logic circuit that are driven to the same state during a precharge phase. During an evaluation phase, one of the input signals may evaluate to a logic state complementary to the other input. The level-shifting latch circuit may generate an output signal corresponding to the input signal. On a precharge phase of a next cycle, the level-shifting latch may retain the state of the output when the two inputs are again driven to the same state. | 02-23-2012 |
20120044010 | SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance. | 02-23-2012 |
20120056656 | LEVEL SHIFTER - A level shifter includes first and second NMOS transistors with gates connected to inverted circuit and circuit inputs, respectively, sources connected to the ground, and drains connected to circuit and inverted circuit outputs, respectively. First and second PMOS transistors have their gates connected to the inverted circuit and circuit outputs, respectively, and sources connected to the high voltage supply. A third PMOS transistor of the multiple independent gate type has its source connected to the drain of the first PMOS transistor, drain and back-gate connected to the circuit output, and front-gate connected to the inverted circuit input. A fourth PMOS transistor of the multiple independent gate type has its source connected to the drain of the second PMOS transistor, drain and back-gate connected to the inverted circuit output, and front-gate connected to the circuit input. | 03-08-2012 |
20120056657 | INTERFACE CIRCUIT - An interface circuit according to one aspect of the present invention may include a receiving circuit operating on a supply voltage lower than a high-level voltage value of an input binary signal, an input level determination circuit generating an input level determination signal having a frequency higher than a frequency of the binary signal and controls whether to output the input level determination signal or not, based on a voltage level of the binary signal, and an AC coupling element connected between an output terminal of the input level determination circuit and an input terminal of the receiving circuit. | 03-08-2012 |
20120068755 | LEVEL SHIFTER - According to one embodiment, a level shifter includes a high-side switch and a low-side switch. The high-side switch is connected between a high-potential power supply and a connection point and turned on in accordance with an input signal. The low-side switch is connected between the connection point and a low-potential power supply and turned on in accordance with an input signal. A ratio between ON resistance of the high-side switch and ON resistance of the low-side switch is set in accordance with a signal difference between an output signal and the input signal. The output signal is outputted to the connection point. | 03-22-2012 |
20120068756 | Two-Terminal M2LC Subsystem and M2LC System Including Same - A two-level two-terminal modular multilevel converter subsystem. The subsystem includes a first capacitor and a second capacitor. The modular multilevel converter subsystem is configured to selectively place the first capacitor in series with the second capacitor. The modular multilevel converter subsystem is also configured to selectively place the first capacitor in parallel with the second capacitor relative to first and second output terminals of the modular multilevel converter subsystem. | 03-22-2012 |
20120075001 | LEVEL SHIFT CIRCUIT AND SWITCHING REGULATOR USING THE SAME - A level shift circuit includes an input port to which an input signal is input, a first signal amplifying unit configured to amplify the input signal input to the input port, a node at the first signal amplifying unit to output the amplified signal, a level shift input port to which a level shift voltage for controlling a DC level of the node is input, a first supply voltage configured to drive the first signal amplifying unit, and a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage. | 03-29-2012 |
20120081166 | Level Shifter Circuits and Methods - Some embodiments of the present disclosure relate to a level shifter that provides improved response time and/or low static power dissipation compared to conventional level shifters. In some embodiments, a level shifter circuit includes an input terminal coupled to a first semiconductor device, and an output terminal coupled to a second semiconductor device. The first semiconductor device is designed to operate over a first voltage range associated with an input signal, and the second semiconductor device is designed to operate over a second, different voltage range associated with an latched output signal. To transform the input voltage range to the output voltage range, the level shifter circuit includes a signal analyzer and an output latch, wherein the signal analyzer includes at least one state change element for setting a voltage level of the latched output signal. | 04-05-2012 |
20120081167 | SEMICONDUCTOR DEVICE, AND METHOD OF DIAGNOSING ABNORMALITY OF BOOSTING CIRCUIT OF SEMICONDUCTOR DEVICE - The battery monitoring IC is provided with the short circuiting switch that includes the switching element that shorts the input side and the output side of the boosting circuit that boosts the power supply voltage to the driving voltage, that can drive the MOS transistor within the buffer amplifier in the saturated region, and supplies the driving voltage as the driving voltage of the buffer amplifier. An abnormality of the boosting circuit can be diagnosed by comparing the output voltage, that is measured when the short circuiting switch is turned off and the driving voltage boosted by the boosting circuit is supplied to the buffer amplifier, and the output voltage, that is measured when the short circuiting switch is turned on and the power supply voltage is, without going through the boosting circuit, supplied as is to the buffer amplifier. | 04-05-2012 |
20120086495 | VOLTAGE LEVEL SHIFTER - An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node. | 04-12-2012 |
20120092058 | OPEN LOOP RAIL-TO-RAIL PRECHARGE BUFFER - A method and system that may include a pair of amplifier transistors and an output coupled to a load device. The precharge buffer may be controlled by an activation signal. The precharge buffer may also include a pair of level shifters. Each level shifter may be provided in association with a respective one of the transistors, and each may provide a respective level shift to an input signal at a common signal source based on a reference voltage. Outputs of the level shifters may be coupled to the respective transistors. The precharge buffer may also include a bypass signal path extending from the common signal source to the load device. A signal path may be controlled by another activation signal, and the precharge buffer and the bypass signal may be enabled during mutually exclusive states of the activation signal. | 04-19-2012 |
20120098584 | CIRCUIT AND METHOD FOR IMPROVEMENT OF A LEVEL SHIFTER - A current limiter is connected between a voltage source and the level shifting latch of a level shifter for limiting the driving current for the level shifting latch under a threshold, to thereby reduce the current consumption of the level shifter during logic transition, by which the level shifting latch can be implemented by transistors with shorter channels, thereby downsizing the circuit area of the level shifter. Preferably, the threshold is adjustable for adjusting the output driving capability of the level shifter and speeding up logic transition of the level shifter. | 04-26-2012 |
20120119812 | LEVEL SHIFTER WITH PRIMARY AND SECONDARY PULL-UP CIRCUITS - A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals. | 05-17-2012 |
20120126874 | INTEGRATED CIRCUIT - An integrated circuit includes a transfer unit configured to transfer an input signal having a first swing width between a first voltage and a second voltage, a driving unit configured to drive an output terminal to output an output signal having a second swing width in response to the input signal transferred from the transfer unit, and a control unit configured to control the driving unit in response to the output signal. | 05-24-2012 |
20120126875 | SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a power supply section, a driver, and a switch section. The power supply section is configured to generate a first potential higher than a positive power supply potential, and a negative second potential. The driver is connected to the power supply section and configured to output a control signal. A potential of the control signal is set to the first potential at high level and set to the second potential at low level according to a terminal switching signal. The switch section is configured to receive the control signal and switch a connection between terminals. The driver has a first level shifter, a second level shifter and a first circuit. The first level shifter has a first high-side switch and a first low-side switch. The second level shifter has a second high-side switch and a second low-side switch. | 05-24-2012 |
20120133413 | DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT - The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal. | 05-31-2012 |
20120133414 | COMPENSATING FOR WANDER IN AC COUPLING DATA INTERFACE - Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal. | 05-31-2012 |
20120133415 | LEVEL SHIFTER - A level shifter includes a driving signal generating unit, a driving unit, and a current path forming unit. The driving signal generating unit is configured to generate a pull-up signal and a pull-down signal in response to an input signal, which may swing between a first high level and a first low level. The driving unit is configured to generate an output signal swinging between a second high level and a second low level in response to the pull-up signal and the pull-down signal. The current path forming unit is configured to form a current path between the pull-up signal and the pull-down signal in response to the pull-up signal and the pull-down signal. | 05-31-2012 |
20120133416 | LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR DEVICE - A level shift circuit including a level conversion unit that converts an input signal having a signal level of a first voltage into a signal having a signal level of a second voltage that is higher than the first voltage. The level conversion unit includes first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, which differs from the first conductivity type and of which switching is controlled in accordance with the input signal. The third and fourth MOS transistors include drains supplied with the second voltage via the first and second MOS transistors, respectively. A control unit, when detecting a decrease in the first voltage, controls a body bias of the third and fourth MOS transistors to decrease a threshold voltage of the third and fourth MOS transistors. | 05-31-2012 |
20120139606 | MULTI-VOLTAGE INPUT BUFFER - In hard disc drive (HDD) applications, there is often a need for input buffers that can operate at a variety of voltages (i.e., 1.8V, 2.5V, and 3.3V) as well as tolerate high voltages (i.e., 5V). Traditional buffers, however, usually lack the ability to operate at these varying voltages and lack the ability to tolerate high voltages. Here, a buffer is provided that fits this criteria through the use of a switching circuit and an anti-saturation circuit (as well as other circuitry). | 06-07-2012 |
20120139607 | VOLTAGE LEVEL SHIFTER - Provided is a voltage level shifter changing an input voltage level and outputting the input voltage. There is provided the voltage level shifter, including: an operational amplifier having a first input having an applied input voltage thereto; a first MOSFET having a gate connected to an output of the operational amplifier, a source having an applied power thereto, and a drain outputting an output voltage; a voltage dividing resistor unit including a plurality of voltage dividing resistors sequentially connected to the drain of the first MOSFET in series, one connection node between the plurality of voltage dividing resistors being connected to the second input of the operational amplifier; and a second MOSFET having a source and a drain, respectively connected to both ends of at least one of the voltage dividing resistors, and a gate connected to the gate of the first MOSFET. | 06-07-2012 |
20120146704 | CASCODED LEVEL SHIFTER PROTECTION - A cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range. The shifter includes an input node receiving an input signal, a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device includes a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal, and reference voltage perturbation circuitry configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch. | 06-14-2012 |
20120146705 | CONTROL-VOLTAGE OF PASS-GATE FOLLOWS SIGNAL - A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal. | 06-14-2012 |
20120154013 | Power Converter for a Memory Module - An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage. | 06-21-2012 |
20120154014 | LEVEL SHIFT CIRCUIT AND SWITCHING POWER SUPPLY DEVICE - A level shift circuit includes a level changing unit which includes first and second MOS transistors connected in series between a first power supply voltage terminal and a grounding point, and receives a signal having a first amplitude which varies between a lower second voltage and a ground potential to convert the signal to a signal having a second amplitude, and an output stage which includes first and second MOS transistors connected in series between the first power supply voltage terminal and a third voltage terminal to which a third voltage lower than the first power supply voltage and higher than the ground potential is supplied, and which stage is connected to an output node of the level changing unit. A first MOS transistor is connected in series between the first MOS transistor and the second MOS transistor of the level changing unit. | 06-21-2012 |
20120169395 | LEVEL SHIFTER - A level shifter, converting an input signal into an output signal for level shifting, including a leakage blocking circuit having cascaded P-channel transistors and one N-channel transistor. The P-channel transistor at a beginning stage provides a gate for receiving the input signal and a source coupled to a gate of the P-channel transistor at a secondary stage. At intermediate stages, each P-channel transistor provides a source coupled to a gate of the subsequently cascaded P-channel transistor. At a final stage, the P-channel transistor provides a source coupled to a voltage source and a drain coupled to an output terminal of the leakage blocking circuit for the outputting of the output signal. The N-channel transistor has a gate which is coupled to receive the input signal as well, a source coupled to a common voltage, and a drain coupled to the output terminal of the leakage blocking circuit. | 07-05-2012 |
20120169396 | VOLTAGE DOWN CONVERTER - A voltage down converter includes a first driver having a first input terminal configured to generate a first voltage by using an external voltage in response to a first driving signal being inputted to the first input terminal, a control circuit configured to output the first driving signal to the first input terminal in response to a level of the first voltage, a second driver having a second input terminal configured to generate a second voltage by using the external voltage in response to the first driving signal or a second driving signal being inputted to the second input terminal, wherein the first driving signal is transferred from the first input terminal to the second input terminal through a conductive line, and a driving control circuit configured to generate the second driving signal and transferred to the second input terminal in response to a level of the second voltage. | 07-05-2012 |
20120182060 | NEGATIVE VOLTAGE LEVEL SHIFTER CIRCUIT - A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits. | 07-19-2012 |
20120187998 | MULTIPLE FUNCTION POWER DOMAIN LEVEL SHIFTER - A level shifter including input and output power nodes, input and output reference nodes, input and output signal nodes, and a lever shifter network. The input power and input reference nodes operate within a first power domain and the output power and output reference nodes operate within a second power domain. The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power and/or ground bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input to assert the output to a known level. | 07-26-2012 |
20120194253 | High Voltage Tolerant Differential Receiver - A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry. | 08-02-2012 |
20120194254 | High Voltage Tolerant Receiver - A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit. | 08-02-2012 |
20120194255 | MULTIVOLTAGE CLOCK SYNCHRONIZATION - A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal. | 08-02-2012 |
20120194256 | LEVEL SHIFTER - A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal. | 08-02-2012 |
20120206185 | LEVEL-DOWN SHIFTER - A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage. | 08-16-2012 |
20120212279 | Threshold Voltage Detection Apparatus - A threshold voltage detection apparatus comprises a voltage level up-shifter and a voltage level down-shifter. The threshold voltage detection apparatus is placed at a circuit fabricated in a low voltage semiconductor process. The threshold voltage detection apparatus receives an input signal having a wide range and generates output signals comprising the logic of the input signal, but having a voltage range suitable for the low voltage circuit. The threshold voltage detection apparatus ensures that the low voltage circuit operates in a range to which the low voltage semiconductor process is specified. | 08-23-2012 |
20120212280 | IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected. | 08-23-2012 |
20120212281 | LEVEL SHIFTER - A level shifter is provided. The level shifter includes a signal converter connected to an external power source and a ground, first and second output terminals connected to the signal converter, the first and second output terminals being configured to output a bias voltage applied from the external power source, and a switching unit configured to switch a connection state of the signal converter according to an input signal to adjust output voltage values of the first and second output terminals, the switching unit including first and second transistors, the first transistor being of a type that is different from a type of the second transistor, the first and second transistors being connected to each other in series between an input terminal, to which an input signal is applied, and the external power source, gates of the first and second transistors being commonly connected to the second output terminal. | 08-23-2012 |
20120223760 | LEVEL SHIFT CIRCUIT - A level shift circuit including a level shift voltage generation circuit that receives an input signal having an amplitude between a voltage of a first voltage system power supply and a ground potential and performs conversion of the amplitude of the input signal to produce an output signal voltage with an amplitude between a voltage of a second voltage system power supply and the ground potential, a replica circuit monitoring a voltage corresponding to a logic threshold of the first voltage system power supply, the replica circuit, with the logic threshold of the first voltage system power supply as an input, monitoring and outputting a voltage corresponding to a logic threshold of the second voltage system power supply, and a bias generation circuit that receives an output from the replica circuit and generates a bias. | 09-06-2012 |
20120229189 | HIGH SPEED LEVEL SHIFTERS AND METHOD OF OPERATION - A circuit comprising an inverter coupled to an input and receiving an input signal. A first pull-down transistor coupled to the inverter, pulling down an output when the input signal is low. A second pull-down transistor coupled to the input, pulling down a complementary output when the input signal is high. A first pull-up transistor coupled to the complementary output, pulling up the output when the input signal is high. A second pull-up transistor coupled to the output, pulling up the complementary output when the input signal is low. A first switch receiving a first control signal, coupled to the complementary output. A first strong pull-up transistor coupled to the first switch, assisting the pull up of the output. A second switch coupled to the output, receiving a second control signal. A second strong pull-up transistor coupled to the second switch, assisting the pull up of the complementary output. | 09-13-2012 |
20120235728 | Level Shifter Design - A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V | 09-20-2012 |
20120249210 | SWITCH CIRCUIT AND SEMICONDUCTOR CIRCUIT - A T/R switch applicable to an ultrasonograph and capable of transmitting a signal reflected from a living body over a wide band with low noise without causing erroneous operation of the switch or element destruction even when the potential of a transmission signal or reflected signal changes includes: a common source terminal commonly and serially coupling the source terminals of two MOS transistors; a common gate terminal commonly coupling the gate terminals of the two MOS transistors; a main switch, the drain terminals of which are connected to input/output terminals; and a floating voltage circuit which is connected to the common gate terminal and common source terminal, makes the common gate terminal potential follow, in phase, variation in the common source terminal potential, and sends a signal to turn the switch on or off to the common gate terminal. | 10-04-2012 |
20120249211 | SEMICONDUCTOR DEVICE - A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block. | 10-04-2012 |
20120256675 | INPUT REFERENCE VOLTAGE GENERATING METHOD AND INTEGRATED CIRCUIT USING THE SAME - An integrated circuit includes: a reference voltage generation unit configured to be driven in response to an enable signal, select one of a plurality of reference voltages generated by dividing a power supply voltage as an input reference voltage, and output the input reference voltage; and a reference voltage level compensation unit configured to be driven in response to the enable signal and change a level of the input reference voltage by an amount of change in a level of an external voltage. | 10-11-2012 |
20120268188 | VOLATGE LEVEL SHIFTING APPARATUS - A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage. | 10-25-2012 |
20120268189 | LOW VOLTAGE ISOLATION SWITCH, IN PARTICULAR FOR A TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS - A switching circuit is electrically coupled between a connection terminal and an output terminal of a transmission channel and includes first and second switching transistors electrically coupled in series to each other and having respective body diodes in anti-series, between the connection terminal and the output terminal. The switching circuit comprises a bootstrap circuit connected to respective first and second control terminals of these first and one second switching transistors, as well as to respective first and second voltage references. The bootstrap circuit includes a first parasitic capacitance electrically coupled between the first control terminal and a first bootstrap node, and a second parasitic capacitance electrically coupled between the second control terminal and a second bootstrap node. The parasitic capacitances have value of at least one order of magnitude lower with respect to the gate-source capacitances of the first and second switching transistors. | 10-25-2012 |
20120274382 | LEVEL-SHIFTER CIRCUIT USING LOW-VOLTAGE TRANSISTORS - A level-shifter circuit may include a pair of inputs which receive a first and a second low-voltage phase signal having a first voltage dynamic with a first maximum value. The level-shifter circuit may also include a pair of outputs which supply a first high-voltage phase signal and a second high-voltage phase signal, level-shifted with respect to the low-voltage signals and having a second voltage dynamic with a second maximum value, higher than the first maximum value. The level-shifter circuit may further include transfer transistors coupled between one of a first reference terminal and a second reference terminal, which are set at one of a first reference voltage and a second reference voltage, and the first output or second output. Protection elements may be coupled to a respective transfer transistor to protect from overvoltages between at least one of the corresponding conduction terminals and control terminals. | 11-01-2012 |
20120280739 | SYSTEM AND METHOD FOR LEVEL-SHIFTING VOLTAGE SIGNALS USING A DYNAMIC LEVEL-SHIFTING ARCHITECTURE - A system and method to level-shift multiple signals from a first voltage domain to a second voltage domain with minimized silicon area. A level-shifting system may be organized by implementing a static level-shifter coupled to a plurality of dynamic level-shifters. The static level-shifter may provide a voltage control signal for each of the dynamic level-shifters. Each of the dynamic level-shifters may level-shift an individual input signal from a first voltage domain to a second voltage domain. | 11-08-2012 |
20120280740 | OUTPUT BUFFER CIRCUIT AND INPUT/OUTPUT BUFFER CIRCUIT - An output buffer circuit includes first and second output circuits, and those output terminals are coupled to each other. The first output circuit outputs a first signal having a voltage level of a first high potential power supply or a low potential power supply and includes a first output transistor at a high potential side. The second output circuit outputs a second signal having a voltage level of a second high potential power supply, which is lower than the first high potential power supply, or the low potential power supply and includes a second output transistor at a high potential side. A control circuit sets the gate and back gate of at least one of the first and second output transistor to the voltage level of the second high potential power supply when the first high potential power supply is deactivated and the second high potential power supply is activated. | 11-08-2012 |
20120280741 | SEMICONDUCTOR DEVICE - A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered. | 11-08-2012 |
20120293231 | Semiconductor Device - An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied. | 11-22-2012 |
20120299631 | Level shifting circuitry - Level shifting circuitry comprises a first level shifter and a second level shifter. In response to a falling edge transition of an input signal, the first level shifter generates a primary transition of a first intermediate signal faster than the second level shifter generates a secondary transition of a second intermediate signal. In response to a rising edge of the input signal, the second level shifter generates a primary transition of the second intermediate signal faster than the first level shifter generates a secondary transition of the first intermediate signal. Output switching circuitry is provided to switch an output signal between an output high voltage level and an output low voltage level in response to the primary transition of the first intermediate signal and the primary transition of the second intermediate signal. | 11-29-2012 |
20120313684 | WIDE RANGE LEVEL SHIFT SYSTEM - A wide range level shift system receives an input signal with a first voltage level and a second voltage level. The wide range level shift system transforms the input signal to an output signal with a third voltage level and a fourth voltage level, wherein the first voltage level is smaller than the second voltage level, the second voltage level is smaller than the third voltage level, and the fourth voltage level is smaller than the first voltage level. The wide range level shift system has six transistors for reducing the number of transistors required, the layout area of the transistors, and the power consumption. | 12-13-2012 |
20120313685 | LEVEL SHIFTER AND METHOD OF USING THE SAME - A level shifter and a method of operating a level shifter are provided. The level shifter includes a first-level shifter unit configured to convert an external input signal into a signal in a preset first-voltage range using a plurality of transistors and output the converted signal and a second-level shifter unit configured to convert the signal output from the first-level shifter unit into a signal in a preset second-voltage range using a plurality of transistors and output the converted signal. | 12-13-2012 |
20120313686 | LEVEL SHIFT CIRCUIT - A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level. | 12-13-2012 |
20130021084 | LOW VOLTAGE SENSORS WITH INTEGRATED LEVEL TRANSLATORS - This disclosure provides techniques for integrating voltage level translators into sensors to provide compatibility between sensor output and inputs to devices that utilize the sensor outputs. According to these techniques, low voltage sensors may be integrated with voltage level translators into an integrated sensing unit that provides data outputs in both low voltage levels and high voltage levels. The integrated sensing unit may provide a selection pin for the output, which may allow utilizing a low voltage output and/or a high voltage output. | 01-24-2013 |
20130021085 | Voltage Level Translator Circuit for Reducing Jitter - A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node. | 01-24-2013 |
20130027108 | LEVEL SHIFT CIRCUIT - According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit. | 01-31-2013 |
20130027109 | VOLTAGE LEVEL SHIFTER HAVING A FIRST OPERATING MODE AND A SECOND OPERATING MODE - Embodiments of the present invention provide a voltage level shifter used to translate a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The input signal is provided by an input voltage varying between a first input voltage level and a second input voltage level. The output signal is provided by an output voltage varying between a first output voltage level and a second output voltage level. The output signal has a delay relative to the input signal, and the voltage level shifter has a leakage current. The voltage level shifter has a first operating mode and a second operating mode. In the second operating mode, the delay is shorter while the leakage current is higher than in the first operating mode. | 01-31-2013 |
20130033299 | APPARATUS FOR INTERFACING CIRCUIT DOMAINS - An interface circuit for controlling a cross-domain signal link between a first circuit domain and a second circuit domain in a circuit may include first and second controllers, each of the first and second controllers including a first input coupled to a first voltage source of the first circuit domain and a second input coupled to a second voltage source of the second circuit domain. The interface circuit may further include a first switch controlled by an output of the first controller, the first switch including a first end coupled to the cross-domain signal link and a second end coupled to a first defined voltage state, and a second switch controlled by an output of the second controller, the second switch including a first end coupled to the cross-domain signal link and a second end coupled to a second defined voltage state, in which during a power-up of the circuit, if one of the first and second voltage sources is unavailable, at least one of the first and second controllers generates a control signal to engage at least one of the first and second switches and pull the cross-domain signal link to one of the first and second defined voltage states, while providing cross-domain protection against field-induced charge device model (FICDM) stress conditions at small drivers and receiver inputs connected to the signal interface link. | 02-07-2013 |
20130038375 | VOLTAGE LEVEL SHIFTER - A circuit includes a power switch and a level shifter. The level shifter has a node and an assistant circuit. The node is configured to control the power switch. The assistant circuitry is coupled to the node and configured for the node to receive a first voltage value through the assistant circuit. The first voltage value is different from a second voltage value of an input signal received by the level shifter. | 02-14-2013 |
20130043926 | LEVEL SHIFT CIRCUIT - In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal IN transitions from a H (VDD) level to a L level, a node W | 02-21-2013 |
20130063198 | BUFFER CIRCUIT HAVING SWITCH CIRCUIT CAPABLE OF OUTPUTTING TWO AND MORE DIFFERENT HIGH VOLTAGE POTENTIALS - A buffer circuit includes a first node that receives a first voltage, a second node, an output node that receives the first voltage, a first transistor coupled between the first node and the second node, the first transistor having a backgate receiving the first voltage, and a second transistor coupled between the second node and the output node, the second transistor having a backgate receiving a second voltage being higher than the first voltage. | 03-14-2013 |
20130069706 | APPARATUS AND METHODS FOR ADAPTIVE COMMON-MODE LEVEL SHIFTING - Apparatus and methods for adaptive level shifting are provided. In one embodiment, a method of level shifting in an adaptive level shifter (ALS) is provided. The technique includes charging a first capacitor and a second capacitor each to a voltage that is about equal to a difference between a common mode voltage of a differential input voltage signal and a reference voltage. The technique can further include inserting the first capacitor between a first input and a first output of the ALS and the second capacitor between the second input and a second output of the ALS. The technique can further include switching the first capacitor and the second capacitor such that the first capacitor is inserted between the second input and the second output and the second capacitor is inserted between the first input and the first output. | 03-21-2013 |
20130069707 | LEVEL SHIFTER CIRCUIT - An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level. | 03-21-2013 |
20130076428 | LEVEL CONVERTER AND PROCESSOR - A level converter includes a level conversion circuit, which is provided between a reference power supply line having a reference voltage level and a first power supply line coupled to a first power supply outputting a first voltage level, which inputs a first signal and outputs a second signal, the first signal having a first logic level and a second logic level, the second signal having a first logic level and a second logic level; a control signal generating circuit to output a control signal having the reference voltage level when a second power supply outputting the second voltage level is turned off and the first voltage level when the second power supply is turned on; and a coupling circuit to control an electrically connection between the first power supply line and an output node of the level conversion circuit based on the control signal. | 03-28-2013 |
20130082758 | SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER CIRCUIT IN WHICH IMPEDANCE THEREOF CAN BE CONTROLLED - Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 04-04-2013 |
20130082759 | LEVEL SHIFTER AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SHIFTER - A level shifter for converting an input pulse signal of low-voltage amplitude to high-voltage amplitude includes a low voltage circuit configured to generate complementary-pulse signals of low-voltage amplitude from the input pulse signal, and a high voltage circuit configured to generate a pulse signal of high-voltage amplitude based on the complementary-pulse signals. The low voltage circuit, including high-threshold voltage transistors, includes a plurality of inverter circuits connected in cascade and at least one resistive-switch circuit connected between an input and an output of at least one of the plurality of inverter circuits configured to operate as a resistor when in a conductive state. | 04-04-2013 |
20130093491 | SEMICONDUCTOR DEVICE AND LEVEL SHIFTING CIRCUIT FOR THE SAME - A level shifting circuit includes an inverter inverting an input voltage of an input node and driving a first voltage of a first node, a first output driving unit driving an output voltage of an output node to a first level in response to the first voltage of the first node, a first connection unit electrically coupling the first node to a second node or electrically isolating the first node from the second node in response to the first voltage of the first node, an internal driving unit driving a second voltage of the second node to a second level in response to the input voltage of the input node and the output voltage of the output node, and a second output driving unit driving the output voltage of the output node to the second level in response to the second voltage of the second node. | 04-18-2013 |
20130093492 | DEVICE - A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit | 04-18-2013 |
20130099846 | DRIVING CIRCUIT, SEMICONDUCTOR DEVICE HAVING DRIVING CIRCUIT, AND SWITCHING REGULATOR AND ELECTRONIC EQUIPMENT USING DRIVING CIRCUIT AND SEMICONDUCTOR DEVICE - Disclosed is a driving circuit that includes a switching element configured to be connected between an input terminal and an output node; a first power supply circuit configured to generate a first voltage; and a first driving circuit configured to drive the switching element with an output thereof using a voltage of the output node as a reference negative-side power supply voltage and the first voltage as a positive-side power supply voltage. The voltage of the output node is used as a reference negative-side power supply voltage of the first power supply. | 04-25-2013 |
20130099847 | INPUT CIRCUIT - An input circuit includes an inverter, a first path control circuit and a second path control circuit. An input of the inverter is connected with a first node. A target inversion potential is higher than an inversion potential of the inverter. The first path control circuit electrically connects an input terminal and the first node when the input potential is higher than the target inversion potential, and blocks off an electrical connection between the input terminal and the first node when the input potential is lower than the target inversion potential. The second path control circuit electrically connects a ground terminal and the first node when the input potential is lower than a second inversion potential which is lower than the target inversion potential and blocks off the electrical connection between the ground terminal and the first node when the input potential is higher than the second inversion potential. | 04-25-2013 |
20130106485 | LEVEL SHIFTER | 05-02-2013 |
20130113540 | ELECTRONIC DEVICE AND METHOD FOR PROVIDING A DIGITAL SIGNAL AT A LEVEL SHIFTER OUTPUT - An electronic device comprising a level shifter and a method. The level shifter includes an input adapted to receive an input signal switching between a low input voltage level and a high input voltage level and a first switch and a second switch coupled in series between a low output voltage supply and a high output voltage supply. An output is coupled to an interconnection node between the first and the second switch and is adapted to be coupled to a load. The first and second switches are controlled by the input signal. The level shifter further includes a third switch which is coupled between the interconnection node and an auxiliary voltage supply which has a voltage level between the low output voltage level and the high output voltage level. | 05-09-2013 |
20130113541 | LOW POWER LEVEL SHIFTER WITH OUTPUT SWING CONTROL - A level shifter comprising a first driver transistor receiving an input signal. A gate-controlled transistor coupled to the first driver transistor. A second driver transistor coupled to the gate controlled transistor. An output coupled to the second driver transistor, wherein the gate-controlled transistor is for receiving a predetermined gate voltage when the output voltage exceeds a predetermined value. | 05-09-2013 |
20130113542 | OUTPUT BUFFER, OPERATING METHOD THEREOF AND DEVICES INCLUDING THE SAME - A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals. | 05-09-2013 |
20130127514 | LEVEL TRANSLATOR - A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value. | 05-23-2013 |
20130127515 | VOLTAGE DIVIDING CIRCUIT - A voltage divider is disclosed that includes a plurality of components connected in series having respective input terminals, respective output terminals, and a reference voltage node at the connection between one of the input terminals and one of the output terminals. The voltage divider also includes a level shifter having a input terminal coupled to the reference voltage node and having a output terminal supplying an output reference voltage. | 05-23-2013 |
20130135027 | LEVEL SHIFTER CIRCUIT, INTEGRATED CIRCUIT DEVICE, ELECTRONIC WATCH - A first circuit receives input signals of the first electric potential system which uses a first high potential and a first low potential as the power supply electric potential, and outputs a first signal which is a signal of the first electric potential system, a second circuit which generates output signals according to the input signal of the second electric potential system which uses as the power supply electric potential a second high potential of the first electric potential system, wherein the second circuit includes an initial stage inverter that receives the second signals and outputs third signals, and an initial stage switch that switches between connecting and disconnecting the initial stage inverter and a power supply that supplies the second high potential or a power supply that supplies the second low potential based on the first signals, and generates the output signals based on the third signals. | 05-30-2013 |
20130135028 | HIGH VOLTAGE SUSTAINABLE OUTPUT BUFFER - An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage. | 05-30-2013 |
20130154712 | Multiplexer with Level Shifter - A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter. | 06-20-2013 |
20130154713 | VOLTAGE LEVEL SHIFTER - A level shifter includes a latch supplied at a first voltage, and first and second series connections of first and second switch elements and first and second biased elements in series with first and second branches of the latch respectively. Third and fourth switch elements are connected in parallel with the first and second series connections respectively. The input signal, at a voltage different from the first voltage, activates the third or fourth switch element during a transition period after a change of state of the input signal one way or the other to change the state of the latch, and deactivates the third or fourth switch element and activates the first or second switch element to maintain the state of the latch during a stabilization period following the transition period. The transition periods are shortened, reducing current consumption and transfer delay times. | 06-20-2013 |
20130162318 | DIFFERENTIAL OUTPUT CIRCUIT - A differential output circuit is controlled according to its mode of operation. While in the first mode, the differential output circuit controls a current flow through a variable current source according to an impedance of the variable current source, and while in the second mode, the differential output circuit compares a voltage at a monitored node and a reference voltage and controls the current flow through the variable current source to make the voltage at the monitored node to be equal to the reference voltage. | 06-27-2013 |
20130169339 | LEVEL SHIFTING CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A level shifting circuit includes a first circuit, a second circuit and an output voltage controlling circuit. The first circuit is coupled to an input node, an output node and a first supply voltage node and configured to pull an output voltage at the output node toward the first supply voltage in accordance with an input voltage applied to the input node. The second circuit is coupled to the first circuit, the output node and the second supply voltage node and configured to pull the output voltage toward the second supply voltage in accordance with the input voltage from the first circuit. The output voltage controlling circuit is coupled to the output node and configured to control the output voltage within a range narrower than a range from the first voltage to the second voltage. | 07-04-2013 |
20130176066 | LEVEL SHIFT CIRCUIT - The invention provides a level shift circuit which uses a low supply voltage level shift circuit as a first level shift element and a high supply voltage level shift circuit as a second level shift element and which is configured to switch these level shift circuits in accordance with supply voltage. The low supply voltage level shift circuit is in an operating state with its power supply turned ON when supply voltage is low and in a shut-down state with the power supply turned OFF to ensure the breakdown voltages of the elements when supply voltage is high. The high supply voltage level shift circuit is in a shut-down state with its power supply turned OFF when supply voltage is low and comes into an operating state with the power supply turned ON while ensuring the breakdown voltages of elements when supply voltage is high. | 07-11-2013 |
20130181762 | CURRENT MIRROR MODIFIED LEVEL SHIFTER - A current mirror modified level shifter includes a pair of PMOS including a PMOS (M | 07-18-2013 |
20130181763 | LEVEL SHIFTER - A level shifter includes a resistor R | 07-18-2013 |
20130187699 | TECHNIQUES FOR SWITCHING BETWEEN AC-COUPLED CONNECTIVITY AND DC-COUPLED CONNECTIVITY - A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, wherein the current source and the termination resistor allows the setting of voltage levels of signals received at the sink line receiver to voltage levels defined by the multimedia interface thereby to switch to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates. | 07-25-2013 |
20130194020 | LEVEL SHIFTING CIRCUIT - An integrated circuit has a level shifter, a pull-circuit, and a voltage regulator. The level shifter and the pull-up circuit receive power from the same supply voltage. The voltage regulator changes the voltage level from the supply voltage to another voltage level used by the level shifter. | 08-01-2013 |
20130194021 | CAPACITIVE COUPLING, ASYNCHRONOUS ELECTRONIC LEVEL SHIFTER CIRCUIT - An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal. | 08-01-2013 |
20130214843 | BUFFER CIRCUIT FOR SEMICONDUCTOR DEVICE - A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved. | 08-22-2013 |
20130222035 | LEVEL-SHIFTING INTERFACE FOR A PROCESSOR-BASED DEVICE - An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together. | 08-29-2013 |
20130222036 | VOLTAGE LEVEL CONVERTING CIRCUIT - A voltage level converting circuit includes: a voltage level converting block configured to convert an input signal having a first voltage level into an output signal having a second voltage level; and a boosting block connected to an input stage and an inverting input stage of the voltage level converting block, and configured to provide a negative voltage to the input stage or the inverting input stage. | 08-29-2013 |
20130222037 | VOLTAGE LEVEL SHIFTER - A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation. | 08-29-2013 |
20130222038 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition. | 08-29-2013 |
20130222039 | INPUT BUFFER - An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal. | 08-29-2013 |
20130222040 | Signal Transmission Arrangement with a Transformer - A signal transmission arrangement includes a transformer with a first and a second winding. A damping circuit has an input terminal for receiving an input signal. The damping circuit is coupled to the first winding and is configured to have an electrical resistance that is dependent on the input signal. An oscillator circuit includes the second winding and is configured to provide an oscillating signal. An evaluation circuit is configured to receive the oscillating signal and to provide an output signal that is dependent on an amplitude of the oscillating signal. | 08-29-2013 |
20130229220 | SYSTEM FOR A CLOCK SHIFTER CIRCUIT - A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node. | 09-05-2013 |
20130234774 | LEVEL SWITCHING CIRCUIT AND METHOD FOR CONTROLLING RAIL-TO-RAIL ENABLING SIGNAL - This document discusses, among other things, methods for controlling a Rail-to-Rail enabling signal, including providing a first signal of an input signal of a control circuit to a level switching circuit, performing, by the level switching circuit, enabling control according to a high level and a low level of the first signal, and outputting, by the level switching circuit, a disabling signal in case of a failure of a power supply coupled to the level switching circuit. The document also discusses a circuit for controlling a Rail-to-Rail enabling signal and a level switching circuit configured to output a disabling signal properly to provide an accurate enabling control signal for equipment operated under control of an enabling control in case of the failure of the power supply. | 09-12-2013 |
20130241623 | LEVEL SHIFT CIRCUIT - A level shift circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a latch-type level shifter, a first current source and a second current source. The first input terminal receives an input signal; the second input terminal receives an inverse signal of the input signal; the first output terminal outputs an output signal; and the second output terminal outputs an inverse signal of the output signal. The latch-type level shifter is connected to the first input terminal, the second input terminal, the first output terminal and the second output terminal. The first current source is connected between a first high voltage input terminal of the latch-type level shifter and a voltage source. The second current source is connected between a second high voltage input terminal of the latch-type level shifter and the voltage source. | 09-19-2013 |
20130241624 | Dual Path Level Shifter - Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters. | 09-19-2013 |
20130257505 | LEVEL SHIFTER CIRCUITS CAPABLE OF DEALING WITH EXTREME INPUT SIGNAL LEVEL VOLTAGE DROPS AND COMPENSATING FOR DEVICE PVT VARIATION - A level shifter circuit includes a level shifter unit and a first controlling unit. The level shifter unit has an input node for receiving an input signal having a predetermined level, an output node for outputting an output signal having a desired level and a complementary output node for outputting a complementary output signal complementary to the output signal. The first controlling unit is coupled to the level shifter unit and has a first transistor coupled between the complementary output node and a first control node for receiving a first control signal and a second transistor coupled between the input node for receiving the input signal and a ground. | 10-03-2013 |
20130265094 | LEVEL SHIFTER CIRCUIT - A level shifter circuit for shifting voltage level of an input signal includes a supply voltage generation circuit, an inverter, and a cross-coupled latch. The supply voltage generation circuit generates a low-voltage supply using a high-voltage supply. The low-voltage supply is used by the inverter to generate an inverted input signal. The input signal and the inverted input signal are provided to the cross-coupled latch, which generates a level shifted output signal. | 10-10-2013 |
20130271199 | VOLTAGE LEVEL SHIFT WITH INTERIM-VOLTAGE-CONTROLLED CONTENTION INTERRUPT - Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption. | 10-17-2013 |
20130278319 | LEVEL SHIFT CIRCUIT UTILIZING RESISTANCE IN SEMICONDUCTOR SUBSTRATE - A level shift circuit does not affect delay time, regardless of the size of resistor resistance value. The level shift circuit includes first and second series circuits wherein first and second resistors and first and second switching elements are connected in series, rise detector circuits that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements connected in parallel to the first and second resistors respectively. The gate terminals of the third and fourth switching elements are connected to the rise detector circuits, and the third and fourth switching elements are turned on by the first and second output signals respectively. | 10-24-2013 |
20130285731 | SYSTEM AND METHOD OF CONTROLLING DEVICES OPERATING WITHIN DIFFERENT VOLTAGE RANGES - Semiconductor devices, systems, and methods are disclosed to facilitate power management. A method includes operating a first voltage range island of a semiconductor device within a first voltage range. The first voltage range includes a first midpoint. The first voltage range is provided in part by a voltage source that includes a tracking voltage regulator. The method also includes operating a second voltage range island of the semiconductor device within a second voltage range. The second voltage range includes a second midpoint. The first voltage range is different than the second voltage range. | 10-31-2013 |
20130293278 | LOW POWER DUAL VOLTAGE MODE RECEIVER - A dual-voltage receiver, comprising a voltage detector. A high voltage Schmitt trigger coupled to the voltage detector. A low voltage Schmitt trigger coupled to the voltage detector. A combined level shifter coupled to the high voltage Schmitt trigger and the low voltage Schmitt trigger, wherein the high voltage Schmitt trigger is on and the low voltage Schmitt trigger is off when the voltage detector outputs a high voltage detect signal. | 11-07-2013 |
20130293279 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source. | 11-07-2013 |
20130300485 | APPARATUS AND METHOD FOR HIGH VOLTAGE SWITCHES - Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor. | 11-14-2013 |
20130300486 | REDUCED DELAY LEVEL SHIFTER - A circuit comprising a first input transistor having a drain, a source and a gate. A first diode connected transistor having a drain, a source and a gate, wherein the gate of the first diode connected transistor is coupled to the drain of the first diode connected transistor, and the drain of the first input transistor is coupled to the drain of the first diode connected transistor. A first load transistor having a drain, a source and a gate, wherein the drain of the first load transistor is coupled to the drain of the first diode connected transistor and the source of the first load transistor is coupled to the source of the first diode connected transistor. | 11-14-2013 |
20130300487 | SEMICONDUCTOR SWITCH - A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anodeāand thereby turns off the switchāwhen off. When on, the MOS gate's channel resistance serves as a ballast resistor. | 11-14-2013 |
20130321059 | Sampling Switch Circuit that uses Correlated Level Shifting - A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node. | 12-05-2013 |
20130321060 | INPUT BUFFER CIRCUIT AND SEMICONDUCTOR DEVICE - A drain or a source of a transistor which receives an input signal at a gate is connected to a back gate of the transistor. A voltage changing circuit portion changes voltage applied to the drain or the source in accordance with a change in potential level of the input signal so that a potential difference between the gate and the drain or the source is lower than or equal to breakdown voltage of the transistor. | 12-05-2013 |
20130328611 | JITTER REDUCTION IN HIGH SPEED LOW CORE VOLTAGE LEVEL SHIFTER - An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The second supply has a higher voltage than the first supply. | 12-12-2013 |
20130342258 | LOW POWER RECEIVER FOR IMPLEMENTING A HIGH VOLTAGE INTERFACE IMPLEMENTED WITH LOW VOLTAGE DEVICES - An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications. | 12-26-2013 |
20130342259 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SWITCHING DEVICE - A semiconductor circuit for supplying a signal for controlling a switching circuit includes a control terminal for receiving a control signal. The control signal is sent to a first inverter, which inverts the control signal to generate a first signal. The first signal is provided to a second inverter, which inverts the first signal to generate a second signal. A level shift circuit is configured to receive a first intermediate voltage and a second intermediate voltage and shifts levels of first and second intermediate voltages to generate first and second output voltages, respectively. The output voltages are received by an augmenting circuit, which also receives the first and second signals. The augmenting circuit is configured to augment the output voltages to generate first and second augmented voltages that are output to first and second output terminals, respectively. | 12-26-2013 |
20130342260 | INPUT CIRCUIT ARRANGEMENT, OUTPUT CIRCUIT ARRANGEMENT, AND SYSTEM HAVING AN INPUT CIRCUIT ARRANGEMENT AND AN OUTPUT CIRCUIT ARRANGEMENT - The invention relates to an input circuit arrangement ( | 12-26-2013 |
20140002172 | VOLTAGE GENERATING CIRCUITS BASED ON A POWER-ON CONTROL SIGNAL | 01-02-2014 |
20140015586 | Integrated Semiconductor Device and a Bridge Circuit with the Integrated Semiconductor Device - A bridge circuit is provided. The bridge circuit includes a first integrated semiconductor device having a high-side switch, a second integrated semiconductor device having a low-side switch electrically connected with the high-side switch, a first level-shifter electrically connected with the high-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device, and a second level-shifter electrically connected with the low-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device. Further, an integrated semiconductor device is provided. | 01-16-2014 |
20140015587 | LEVEL SHIFTING CIRCUIT WITH DYNAMIC CONTROL - A level shifting circuit with dynamic control includes a dynamic controller and a level shifter. The dynamic controller outputs a dynamic voltage and an output data signal. The level shifter under control by the dynamic controller includes an input signal receiver, an output signal generator, and a bias current controller, which are coupled in series between a ground voltage and a high level voltage. The input signal receiver receives the output data signal of the dynamic controller and the output signal generator produces a level-shifted data signal according to the input data signal. The bias current controller controlled by the dynamic voltage is at a first current-output capability when the level-shifted data signal is at a stable stage and at a second current-output capability when the level-shifted data signal is at an unstable stage. The first current-output capability is greater than the second current-output capability. | 01-16-2014 |
20140015588 | LEVEL SHIFTER - A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal. | 01-16-2014 |
20140021999 | LEVEL SHIFTING CIRCUITRY - Level shifting circuitry is provided for generating an output signal in response to an input signal. The level shifting circuitry includes a pulldown path for pulling the output signal to a lower output voltage level in response to a first transition of the input signal and a pullup path for pulling the output signal to a higher output voltage level in response to a second transition of the input signal. Pullup control circuitry places the pullup path in a non-conductive state in response to the output signal being pulled to the higher output voltage level. A keeper path keeps the output signal at the higher output voltage level while the pullup path is non-conductive until the pulldown path pulls the output signal low. A maximum drive current of the pulldown path is greater than a maximum drive current of the keeper path. | 01-23-2014 |
20140028371 | Level Shifter Having Feedback Signal From High Voltage Circuit - According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal. | 01-30-2014 |
20140049308 | LEVEL SHIFT CIRCUIT - According to one embodiment, a first CMOS inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second CMOS inverter is connected to a rear stage of the first CMOS inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first CMOS inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second CMOS inverter. | 02-20-2014 |
20140062570 | Overdrive Circuits and Related Method - An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor. | 03-06-2014 |
20140062571 | INVERSE LEVEL SHIFT CIRCUIT - A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential. A mask logical circuit generating a fourth mask signal by performing a AND operation between the first mask signal and the second mask signal, and masking the first and second main signals with the third and fourth mask signals; and a SR flip flop circuit generating the output signal from the masked first and second main signals. | 03-06-2014 |
20140062572 | SINGLE INPUT LEVEL SHIFTER - Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage. | 03-06-2014 |
20140062573 | LEVEL SHIFT DEVICE - Disclosed is a level shift device. The level shift device to convert an input signal having a low-voltage level into an output signal having a high-voltage level includes a latch-type level shifter and a voltage generator. The latch-type level shifter includes two upper pull-up P channel transistors and two lower P channel transistors to prevent the gate-source voltage breakdown of the two upper pull-up P channel transistors. The two upper pull-up P channel transistors and the two lower P channel transistors form a latch structure. The voltage generator generates a voltage to prevent the gate-source voltage brake down of the two upper pull-up P channel transistors and provides the voltage to the gate electrodes of the two lower P channel transistors. | 03-06-2014 |
20140084984 | LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL FROM OUTPUT POWER DOMAIN AND A METHOD OF CONVERTING A DATA SIGNAL BETWEEN POWER DOMAINS - Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source. | 03-27-2014 |
20140084985 | LEVEL-UP SHIFTER CIRCUIT - A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity. | 03-27-2014 |
20140084986 | DRIVER CIRCUIT - A line driver circuit for a High Definition Multimedia Interface (HDMI) transmitter is disclosed. The line driver circuit includes a pre-driver circuit having a pair of pre-driver differential inputs and a pair of pre-driver differential outputs. A driver circuit having a pair of driver differential inputs and a pair of driver differential outputs is also included. Each of the pair of pre-driver differential outputs is coupled to a respective one of the pair of driver differential inputs. Each of the pair of driver differential outputs is coupled to a respective one of a pair of output terminals. The pre-driver further includes a pair of pre-driver cascode transistors. Each of the pre-driver cascode transistors is arranged between one of the pre-driver differential outputs and a respective one of the output terminals and wherein the driver circuit and the pre-driver circuit are operable to receive a current supplied by a HDMI receiver coupled to the pair of output terminals. | 03-27-2014 |
20140103988 | VOLTAGE SWITCH CIRCUIT - A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process. | 04-17-2014 |
20140111266 | METHOD AND DEVICE FOR HIGH-SPEED GENERAL PURPOSE LEVEL-SHIFTING - A level shifter and method are disclosed. In one embodiment, the level shifter includes a DC biasing component connected with both an AC coupling component and a high voltage output amplifier. The AC coupling component receives an input signal from a low voltage domain and output a first voltage signal. The DC biasing component is configured to bias the first voltage signal using a bias voltage based on a previous output signal in a high voltage domain. The high voltage output amplifier is configured to amplify the DC biased voltage signal in the high voltage domain and provide an output signal in the high voltage domain. | 04-24-2014 |
20140111267 | LEVEL SHIFTER AND OPERATIONAL AMPLIFIER - A level shifter includes a signal receiving module, including at least one signal receiving end for receiving at least one input signal and being conducted or non-conducted according to the input signal; a level adjusting module, configured to generate the adjusted output signal according to the input signal, wherein the level adjusting module includes a first connection end and a second connection end, the second connection end is coupled to the signal receiving module; and a switch module, including a first end coupling to the first connection end and a second end coupling to the second connection end. If the switch module is conducted, an current path is formed between the first connection end, the second connection end and the signal receiving module through the switch module. If the switch module is not conducted, current is blocked from flowing from the first connection end to the second connection end. | 04-24-2014 |
20140118049 | LEVEL SHIFT SWITCH AND ELECTRONIC DEVICE WITH THE SAME - According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit. | 05-01-2014 |
20140125396 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING LEVEL SHIFTING - A system, method, and computer program product are provided for performing level shifting. In use, level shifting is performed utilizing a native transistor, where the level shifting is performed utilizing a feedback based topology. | 05-08-2014 |
20140125397 | LEVEL CONVERTER FOR CONTROLLING SWITCH - Provided is a power amplifier using a differential structure. The power amplifier includes: first and second transistors whose first terminals are each connected to a first power supply source supplying a first voltage and into which signals having the same size and opposite polarities are input; third and fourth transistors whose first terminals are respectively connected to the first terminals of the first and second transistors; and a fifth transistor whose first terminal is connected to second terminals of the third and fourth transistors and controlling oscillation of the third or fourth transistor. | 05-08-2014 |
20140125398 | Driver Integrated Circuit - Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. | 05-08-2014 |
20140132329 | VOLTAGE LEVEL SHIFT CIRCUIT FOR MULTIPLE VOLTAGE INTEGRATED CIRCUITS - An over-driver, voltage level shift circuit for use with multiple voltage integrated circuits. The voltage level shift circuit includes a first pair of PMOS transistors, a second pair PMOS transistors and a third pair of PMOS transistors using a high supply voltage source VDDH and a low supply voltage source to voltage level shift input signals having a first voltage operating range to an output signal having a second voltage operating range higher then the first voltage operating range. Some embodiments include a fourth set of transistors and a fifth set of transistors to receive a medium supply voltage source VDDM between the high supply voltage source VDDH and a low supply voltage source and another set of input signals operating a voltage operating range different than the first operating range. The voltage level shift circuit selectably switches between a plurality of different voltage operating ranges for the second voltage operating range. | 05-15-2014 |
20140145777 | System and Method for a Level Shifter - In accordance with an embodiment, a level shifter circuit includes a reconfigurable level shifting core coupled to a first node and a second node. The reconfigurable level shifting core is configured as a current mirror in a first mode, and as a cross-coupled device in a second mode. In the first mode, the current mirror mirrors a current at the first node to the second node, and in the second mode, the cross-coupled device produces a current at the second node in response to a voltage at the first node, and a current at the first node in response to a voltage at the second node. | 05-29-2014 |
20140152369 | Level Translator Circuit, Driving Circuit for Driving High-Voltage Device and Method Thereof - The present invention provides a level translator circuit, a driving circuit for driving a high-voltage device and a corresponding method. The driving circuit for driving a high-voltage device comprises: a zener diode whose cathode is connected to a high-voltage power supply voltage and whose anode is connected to a ground potential of a low-voltage domain through a resistor; a high-voltage PMOS transistor whose gate is connected to an anode of the resistor, whose drain is connected to the ground potential of the low-voltage domain, and whose source is operable to supply a ground potential of a high-voltage domain; a level translator operable to convert a first signal in the low-voltage domain as received to a second signal in the high-voltage domain and output the second signal; and a low-voltage driving circuit operable to receive the second signal and adapt the second signal as a third signal which can drive the high-voltage device. The present invention allows for use of the low-voltage device to drive the high-voltage device to achieve the drive of the high-voltage device in a simple and efficient manner. | 06-05-2014 |
20140159795 | System and Method for AC Coupling - An AC coupling circuit is provided that has a level shifter circuit having a p input voltage and an n input voltage and producing a p output voltage and a p output voltage. There is a common mode voltage adjustment feedback circuit configured to cause a common mode voltage output to tend towards a specified reference voltage, the common mode voltage output being an average of the p output and n output voltages of the level shifter circuit. In combination, the level shifter circuit and the feedback circuit allow the interconnection of a first circuit that operates at a first, unspecified, common mode voltage to be connected to a second circuit having a required common mode voltage. The level shifter may be formed of adjustable components such that the frequency response of the level shifter circuit can be adjusted to compensate for a frequency response of an interconnect between the first circuit and the second circuit. | 06-12-2014 |
20140176221 | SENSE AMPLIFIER INCLUDING A LEVEL SHIFTER - An apparatus includes a sense amplifier that has a sense amplifier differential output. The sense amplifier may be in a first power domain. The apparatus may include level shifting circuitry that has a level shifter differential output. The level shifting circuitry may be coupled to the sense amplifier differential output. The level shifting circuitry may include a first transistor and a second transistor. A first sense amplifier output of the sense amplifier differential output may be coupled to the first transistor, and a second sense amplifier output of the sense amplifier differential output may be coupled to the second transistor. The apparatus may further include a latch to store data. The latch may be coupled to the level shifter differential output. The latch is in a second power domain that is different from the first power domain. | 06-26-2014 |
20140176222 | SIGNAL RECEIVER AND SIGNAL TRANSMISSION APPARATUS - A signal receiver includes first and second bias circuits that receive an input signal and convert the input signal to respective first and second bias signals. The signal receiver also includes a first inverter comprising a PMOS device and an NMOS device, each device has a source, a drain, and a gate. When the voltage magnitude of the first bias signal is smaller than that of the input signal, the gate of the PMOS device is coupled to the first bias signal and the gate of the NMOS device is coupled to the input signal. When the voltage magnitude of the first bias signal is greater than that of the input signal, the gate of the NMOS device is coupled to the first bias signal and the gate of the PMOS device is coupled to the input signal. | 06-26-2014 |
20140176223 | LOW POWER LEVEL SHIFTER WITH OUTPUT SWING CONTROL - A level shifter comprising a first driver transistor for receiving an input signal. A gate-controlled transistor coupled to the first driver transistor. A second driver transistor coupled to the gate controlled transistor. An output coupled to the second driver transistor, wherein the gate-controlled transistor is for receiving a predetermined gate voltage when the output voltage exceeds a predetermined value. | 06-26-2014 |
20140184299 | VOLTAGE LEVEL SHIFTER - A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch. | 07-03-2014 |
20140184300 | Multiple Power Domain Circuit and Related Method - A multiple power domain circuit includes a trigger circuit, a high threshold voltage circuit electrically connected to an output terminal of the trigger circuit, and a low threshold voltage circuit electrically connected to the output terminal of the trigger circuit and an output terminal of the high threshold voltage circuit. The low threshold voltage circuit comprises a pulse generator electrically connected to the output terminal of the trigger circuit, and an inverter electrically connected to an output terminal of the pulse generator, and the output terminal of the high threshold voltage circuit. | 07-03-2014 |
20140197872 | LEVEL SHIFTER DEVICE - A level shifter includes a first terminal configured to receive a first supply voltage, a second terminal configured to receive a second supply voltage, an input terminal configured to receive an input signal and an output terminal. The level shifter is configured to shift the input signal from the level of the first supply voltage to the level of the second supply voltage in outputting the output signal. The level shifter includes a storage circuit for storing the output signal value and configured, when the first supply voltage is no longer available, to force the output terminal to assume the last output voltage value stored by the storage circuit when the first supply voltage was available and before the first supply voltage was not available. | 07-17-2014 |
20140197873 | Semiconductor Device - An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied. | 07-17-2014 |
20140210541 | SYSTEMS AND METHODS OF LEVEL SHIFTING FOR VOLTAGE DRIVERS - System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component. The first converting circuit is configured to convert a first current and generate a first converted voltage signal based on at least information associated with the first current. The second converting circuit is configured to convert a second current and generate a second converted voltage signal based on at least information associated with the second current. The signal processing component is configured to receive the first converted voltage signal and the second converted voltage signal and generate an output signal based on at least information associated with the first converted voltage signal and the second converted voltage signal. | 07-31-2014 |
20140232445 | BALANCED LEVEL SHIFTER WITH WIDE OPERATION RANGE - Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals. | 08-21-2014 |
20140232446 | CONFIGURABLE SINGLE-ENDED DRIVER - Embodiments of the invention are generally directed to a configurable single-ended driver. An embodiment of an apparatus includes an interface with a channel; and a single-ended driver to drive a signal on the channel, wherein the driver includes a mechanism to configure a termination resistance of the driver, configure a voltage swing of the driver, and configure a signal response of the driver. | 08-21-2014 |
20140232447 | LEVEL SHIFT CIRCUIT - There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit. | 08-21-2014 |
20140232448 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line. | 08-21-2014 |
20140247081 | COMBINATORIAL CIRCUIT AND METHOD OF OPERATION OF SUCH A COMBINATORIAL CIRCUIT - An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. A contention mitigation circuitry reduces a voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry's performance of the combinatorial operation causes the combinatorial circuitry to switch the voltage on the output node, the contention mitigation circuitry thereby assists the combinatorial circuitry in the output node voltage switching. | 09-04-2014 |
20140247082 | Fast Voltage Level Shifter Circuit - A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate. | 09-04-2014 |
20140253209 | APPARATUSES AND METHOD FOR SHIFTING A VOLTAGE LEVEL - Apparatuses and methods, such as those for shifting a voltage level are disclosed. An example apparatus includes a level shifter configured to provide output signals based on a logical value of an input signal, where the level shifter is precharged to a precharge voltage prior to providing the output signals. An example method includes precharging an output node of a level shifter to a precharge voltage responsive to a precharge signal via a precharge circuit. A transition of the input signal from a first logical value to a second logical value is received at the level shifter and an output signal is provided at the output node based on the second logical value of the input signal. | 09-11-2014 |
20140253210 | VOLTAGE LEVEL SHIFTER WITH A LOW-LATENCY VOLTAGE BOOST CIRCUIT - Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters. | 09-11-2014 |
20140253211 | LOW VOLTAGE LEVEL SHIFTER FOR LOW POWER APPLICATIONS - A level shifter circuit for low power applications that can shift the level of a digital signal that is below the threshold voltage of output transistors. The level shifter uses core transistors in the input stage and includes an intermediate stage that limits the voltage applied to the drain of the core transistors. The intermediate stage may include two transistors whose gate is connected to a reference voltage and turns off when the voltage at their source is equal to a threshold voltage below the reference voltage, thus limiting the maximum voltage applied to the transistors present in the input stage. | 09-11-2014 |
20140253212 | Variable Voltage Level Translator - An integrated circuit including a processor configured to operate off a supply voltage being applied at one of a plurality of external pins; and internal input/output circuitry configured to select between the supply voltage and at least one other supply voltage being applied at another of the plurality of external pins. | 09-11-2014 |
20140253213 | LEVEL SHIFTING CIRCUIT WITH ADAPTIVE FEEDBACK - An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners. | 09-11-2014 |
20140266384 | SYSTEMS AND METHOD FOR LEVEL SHIFTERS - A level shifter system includes an inverting portion, a non-inverting portion and a cross latch output component. The inverting portion is configured to receive an inverting input, a supply voltage and to generate an intermediary inverting output. The non-inverting portion is configured to receive a non-inverting input, the supply voltage and to generate an intermediary non-inverting output. The cross latch output component is configured to drive the intermediary inverting and non-inverting outputs to inverting and non-inverting outputs, respectively. The inverting and non-inverting outputs are at selected upper and lower levels according to the inverting input and non-inverting inputs, respectively. | 09-18-2014 |
20140266385 | DUAL SUPPLY LEVEL SHIFTER CIRCUITS - A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage. The set of level shifter circuits includes a second set of coupled transistors, wherein the set of level shifter circuits is configured to receive a voltage input signal at an input node from a first circuit and to supply to an output node of the dual supply level shifter circuit an output signal having a value that is a highest voltage value between the first power supply voltage and the second power supply voltage. | 09-18-2014 |
20140266386 | LEVEL SHIFTER FOR HIGH DENSITY INTEGRATED CIRCUITS - A level shifter for converting between voltages of a core voltage range to voltages within a larger I/O voltage range. The level shifter has interconnected transistors implemented as core devices operable within the core voltage range. The level shifter is connected to first and second power connections at the I/O voltage range. A voltage clamping element implemented as a core device has a threshold voltage greater than or equal to the difference between the I/O voltage range and the core voltage range and configured to prevent overstressing the transistors with voltages beyond the core voltage range. The input to the level shifter is within the core voltage range. The level shifter output signal has a high level at the high voltage of the I/O voltage range and a low level at approximately one threshold voltage above the low voltage level of the core voltage range. | 09-18-2014 |
20140266387 | INPUT/OUTPUT INTERFACE - One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors. | 09-18-2014 |
20140266388 | VOLTAGE LEVEL SHIFTER - The voltage level shifter includes a first voltage shift circuit, a second voltage shift circuit, a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit. The first voltage shift circuit receives a first input voltage, and the second voltage shift circuit receives a second voltage shift circuit. When the first voltage is high level voltage, a second output voltage and a first voltage are transformed to a ground voltage so as to open the second switch circuit and the fourth switch circuit, and then the first output voltage is transited to a system voltage. When the second voltage is high level voltage, a first output voltage and a second voltage are transited to a ground voltage so as to open the first switch circuit and the third switch circuit, and then the second output voltage is transited to the system voltage. | 09-18-2014 |
20140266389 | Powerline Control Interface - A powerline control interface includes a powerline connection, a level shifter connected to the powerline connection, the level shifter having a zero crossing detector signal output, a capacitor connected to the powerline connection, an inductor connected to the powerline connection, and a receive signal inductively coupled to the inductor. | 09-18-2014 |
20140292392 | SEMICONDUCTOR DEVICE AND HIGH SIDE CIRCUIT DRIVE METHOD - Aspects of the invention can include a pulse generating means that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state. | 10-02-2014 |
20140300403 | SIGNAL PROCESSING DEVICE - A level shifter converting a binary signal having a first potential and a second potential into a signal having the first potential and a third potential, and a signal processing circuit using the level shifter are provided. The first potential is higher than the second potential. The second potential is higher than the third potential. The potential difference between the first potential and the third potential may be more than or equal to 3 V and less than 4 V. The level shifter includes a current control circuit which generates a second signal for operating an amplifier circuit for a certain period in accordance with the potential change of the first signal which is input to the amplifier circuit. The output of level shifter is input to a gate of an N-channel transistor whose threshold voltage is lower than 0 V. | 10-09-2014 |
20140312954 | HIGH-VOLTAGE MULTI-LEVEL SHIFTER FOR ULTRASOUND APPLICATIONS AND TRANSMIT/RECEIVE CHANNEL FOR ULTRASOUND APPLICATIONS USING SAID LEVEL SHIFTER - A multi-level shifter includes a first branch having first and second transistors coupled between a higher voltage terminal and a lower voltage terminal. The multi-level shifter comprises a second branch, in parallel with the first branch, having: a third transistor, coupled between said higher voltage reference terminal and an output node, a fourth switching transistor coupled between said output node and said lower voltage terminal. Said third and fourth transistors have respective control terminals controlled by drain terminals of said first and second transistors, respectively. The shifter includes a bidirectional battery coupled between said drain terminals of said first and second transistors to supply first and second voltages having the same magnitude and different polarities. Said fourth transistor is controlled according to the first voltage when said first transistor is turned on and said third transistor is controlled according to the second voltage when said second transistor is turned on. | 10-23-2014 |
20140333365 | SEMICONDUCTOR DEVICE - An object is to prevent malfunction of a power device. In a semiconductor device for driving a power device for power supply, a buffer circuit and a level-shift circuit are configured by transistors having the same conductivity type. Furthermore, a capacitor is provided in the level-shift circuit, and a signal to be boosted is supplied to the capacitor and is boosted using capacitive coupling of the capacitor. Furthermore, a structure can be employed in which the signal is boosted in such a manner that, in the level-shift circuit, a capacitor is provided between a wiring for supplying a low power source potential and a wiring for supplying a potential to boost the signal so that a power transistor can be driven. | 11-13-2014 |
20140340136 | Dynamic Level Shifter Circuit - A level shifter does not require any DC (standby) current consumption and has a fast operation with low propagation delay. The level shifting from input to output voltage ranges is performed by a pair of level shifting capacitors. The input-output power voltages domains are unrestricted and flexible. DC isolation is deployed between power domains. Symmetrical rise/fall times are without duty cycle distortion. Over voltage stress is reduced by using metal capacitors. Finally the level shifter does not use high-voltage devices for level shifting purpose. Embodiments of level shifters provide one-way level shifting and bi-directional level shifting. | 11-20-2014 |
20140347115 | VOLTAGE LEVEL TRANSLATOR - A voltage level translator includes an inverter circuit configured to switch an output of the inverter circuit between a first voltage level and a second voltage level. The voltage level translator also includes a capacitor connected to the output of the inverter circuit. The voltage level translator also includes a load connected to the capacitor. The capacitance of the capacitor is approximately 10 times larger than a capacitance of the load. An output signal of the voltage level translator has at least one of a different voltage swing and a different voltage domain than an input signal to the inverter circuit. | 11-27-2014 |
20140347116 | LEVEL SHIFT CIRCUIT - A level shift circuit of an embodiment includes first and second MOSFETs using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second MOSFETs; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second MOSFETs; and a current control circuit that controls an amount of first current flowing through the first MOSFET via the first resistance element and an amount of second current flowing through the second MOSFET via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal. | 11-27-2014 |
20140354342 | Compact Level Shifter - Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-FET coupled to a high reference voltage, and an n-FET coupled to a low reference voltage. The device also includes two latches. The first latch has a first latch output that drives a gate of the p-FET via an inverting circuit element. The second latch has a second latch output that drives a gate of the n-FET via a non-inverting circuit element. The device also includes a reset signal pulse generator that receives the input signal and generates a reset signal pulse in response to a transition in the input signal. Both of the latches are placed in a reset state by the reset signal pulse. | 12-04-2014 |
20140361824 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 12-11-2014 |
20140368253 | LEVEL CONVERSION CIRCUIT AND METHOD FOR CONVERTING VOLTAGE LEVEL THEREOF - A level conversion circuit including a first level shifter and a second level shifter is provided. The first level shifter converts a first control voltage into a second control voltage during a voltage conversion period. The second level shifter is coupled to the first level shifter. The second level shifter converts the second control voltage into a third control voltage during the voltage conversion period to control a next stage circuit. The first level shifter is configured to detect a voltage level of a power domain where the third control voltage operates and generate a plurality of middle voltages based on the detection result. The second level shifter is configured to generate the third control voltage based on the middle voltages. Furthermore, a voltage level conversion method is also provided. | 12-18-2014 |
20140375372 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment is provided with a normally-off transistor which includes a first source connected to a source terminal, a first drain, and a first gate connected to a gate terminal, and a normally-on transistor which includes a second source connected to the first drain, a second drain connected to a drain terminal, and a second gate connected to the gate terminal. | 12-25-2014 |
20140375373 | MULTI POWER SUPPLY TYPE LEVEL SHIFTER - There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters. | 12-25-2014 |
20150035578 | INTERNAL VOLTAGE COMPENSATION CIRCUIT - An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals. | 02-05-2015 |
20150042393 | LEVEL SHIFTER - A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal. The latch circuit is coupled to the input stage circuit through a first output terminal and a second output terminal, and determining steady-state levels of the first and the second output terminals according to the input signal. The transient speed-up circuit is coupled to the first and the second output terminals. When the transient speed-up circuit determines the first and the second output terminals are at the same logic level, the transient speed-up circuit accelerates the positive edge transition of the first or the second terminals. | 02-12-2015 |
20150042394 | BUFFER CIRCUIT - A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal. | 02-12-2015 |
20150042395 | SOURCE DRIVER AND METHOD TO REDUCE PEAK CURRENT THEREIN - A source driver and a method to reduce peak current of the source driver are provided. The source driver includes a latch circuit, a level shifter and a digital-to-analog converter (DAC) circuit. The latch circuit latches current bit-data. The latch circuit is coupled to an input terminal of the level shifter. The DAC circuit is coupled to an output terminal of the level shifter. When the current bit-data is not a complement of previous bit-data, the latch circuit selects and outputs the current bit-data to the input terminal of the level shifter, and the DAC circuit outputs a voltage corresponding to the output data of the level shifter. When the current bit-data is the complement of the previous bit-data, the latch circuit selects and outputs the previous bit-data to the input terminal of the level shifter, and the DAC circuit outputs a voltage corresponding to the current bit-data. | 02-12-2015 |
20150042396 | LEVEL SHIFTER - A level shifter includes high breakdown voltage first and second PMOS transistors, high breakdown voltage first and second depression NMOS transistors having gates respectively supplied with first and second control signals, low breakdown voltage first and second NMOS transistors having gates respectively supplied with third and fourth control signals, and a timing control unit that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal. | 02-12-2015 |
20150048875 | HIGH VOLTAGE POWER CONTROL SYSTEM - A high voltage power control system comprises a microcontroller unit, an embedded non-volatile memory, and a high voltage driver. The micro controller unit is configured to control high voltage outputs of the high voltage power control system. The embedded non-volatile memory is electrically connected to the micro controller. The high voltage driver is electrically connected to the micro controller and is configured to output the high voltage outputs of the high voltage power control system. The high voltage power control system is compatible with a logic process while the embedded non-volatile memory and the high voltage power control system can still support operations of high voltage. | 02-19-2015 |
20150054562 | LEVEL SHIFTER WITH STATIC PRECHARGE CIRCUIT - A level shifter includes a static precharge circuit. During a precharge phase, two nodes of the level shifter are precharged to a voltage at or near a reference voltage. During an evaluate phase, the level shifter maintains one of the nodes at the precharge voltage, while the other node is pulled to a different voltage level, such as at or near a ground voltage level, wherein the node that is maintained is selected based on the state of data input signals of the level shifter. The voltage at the nodes determines the state of the level shifter output signals, such that the output signals represent the input signals at a shifted voltage level. The level shifter can include a capacitor to feed forward a signal that causes the precharging to terminate more quickly. | 02-26-2015 |
20150054563 | COMMUNICATION BETWEEN VOLTAGE DOMAINS - An integrated circuit | 02-26-2015 |
20150054564 | Level Shifter Utilizing a Capacitive Isolation Barrier - According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal. | 02-26-2015 |
20150054565 | Systems and Methods for Operating High Voltage Switches - A system for communicating high voltages for a semiconductor device is provided. One system includes a controller having an input pad and an output pad, each of the input pad and the output pad being coupled to a respective high voltage switch of the controller. The system also includes a plurality of semiconductor chips, where each of the plurality of semiconductor chips has at least one input pad coupled to a high voltage switch of a respective semiconductor chip. A high voltage that is higher than normal operation voltages of the semiconductor device is coupled from the input pad of the controller to the output pad of the controller via the coupled high voltage switches of the controller. The high voltage is further coupled from the output pad of the controller to the at least one input pad of the respective semiconductor chip via the high voltage switch coupled to the at least one input pad of the respective semiconductor chip. Methods for operating and providing high voltage inputs to one or more semiconductor devices are also provided. | 02-26-2015 |
20150061745 | TRANSMITTER HAVING VOLTAGE DRIVER AND CURRENT DRIVER - A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result. | 03-05-2015 |
20150061746 | OUTPUT APPARATUS, OUTPUT DRIVER, AND LEVEL SHIFTING SYSTEM - An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors. The first and second first-type transistors are commonly controlled by a first logic signal. The third first-type transistor is connected in parallel to the second first-type transistor. The pull-down circuit includes first, second and third second-type transistors. The first and second second-type transistors are commonly controlled by a second logic signal. The third second-type transistor is connected in parallel to the second second-type transistor. The pull-up circuit is configured such that a response speed of the first first-type transistor to the first logic signal is lower than that of the second first-type transistor to the first logic signal. | 03-05-2015 |
20150070069 | LEVEL SHIFTER WITH BUILT-IN LOGIC FUNCTION FOR REDUCED DELAY - A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs. | 03-12-2015 |
20150070070 | Multiple Voltage Input Buffer and Related Method - A device includes a first level shifter, a switch, and a control circuit. The first level shifter is electrically connected to a pad. The switch has an input terminal electrically connected to an input terminal of the first level shifter, and an output terminal electrically connected to an output terminal of the first level shifter. The control circuit is electrically connected to a control terminal of the switch. | 03-12-2015 |
20150077168 | LEVEL SHIFTING CIRCUIT - A level shifter shifts the level of an input signal from a second voltage domain to a first voltage domain. To accommodate different input signal levels (e.g., including sub-threshold input signal levels) that may arise due to changes in the supply voltage for the second voltage domain, current for a latch circuit of the level shifter is limited based on the supply voltage for the second voltage domain. In this way, a drive circuit of the level shifter that controls the latch circuit based on the input signal is able to initiate a change of state of the latch circuit over a wide range of input signal levels. | 03-19-2015 |
20150084682 | Dual Path Level Shifter - Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters. | 03-26-2015 |
20150097612 | LEVEL SHIFTER OF DRIVING CIRCUIT AND OPERATING METHOD THEREOF - A level shifter applied in a driving circuit of a display is disclosed. The level shifter includes a first stage of level shifting unit and a second stage of level shifting unit and used to convert an input voltage signal with low voltage level into an output voltage signal with high voltage level. In one example, the total number of the transistors needed by the level shifter is much fewer than that of the prior art, and additional voltage sources are not needed to provide middle voltages. The manufacturing cost of the exemplary level shifter can be reduced and the signal level shifting efficiency of multi-power domain can be enhanced. | 04-09-2015 |
20150102849 | LEVEL-SHIFT CIRCUITS COMPATIBLE WITH MULTIPLE SUPPLY VOLTAGE - A level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage. The post-stage voltage conversion circuit includes a second voltage protection module generating a first inverse output signal, a first output signal, a second inverse output signal, and a second output signal. The transistors of the pre-stage voltage conversion circuit and the post-stage voltage conversion circuit have a punch-through voltage. The level-shift makes the stress of the transistors less than the punch-through voltage when the supply voltage is greater than the punch-through voltage, and remains the driving capability when being less than the punch-through voltage. | 04-16-2015 |
20150109045 | SCALABLE LAYOUT ARCHITECTURE FOR METAL-PROGRAMMABLE VOLTAGE LEVEL SHIFTER CELLS - A layout architecture for voltage level shifters is provided. The architecture includes features of voltage level shifter cells and arrangements of the voltage level shifter cells within integrated circuits. The architecture can be used, for example, in CMOS system-on-a-chip integrated circuits implemented using metal-programmable standard cells. The architecture is also scalable for interfaces having different numbers of signals. The architecture can provide reduced area and improved performance. | 04-23-2015 |
20150130528 | WIDE RANGE CORE SUPPLY COMPATIBLE LEVEL SHIFTER CIRCUIT - A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (FDSOI) technology. By enhancing the performance of the NMOS and devices within the level shifting circuit, the V | 05-14-2015 |
20150130529 | THREE-MODE HIGH-SPEED LEVEL UP SHIFTER CIRCUIT - Embodiments of the present invention disclose a level up shifter circuit. The level up shifter circuit further includes two field effect transistors connected in series and a control circuit. Sources of the two field effect transistors and a source of a sixth field effect transistor are respectively connected to a drain of a first field effect transistor and a drain of a second field effect transistor of the conversion circuit, and the control circuit is turned on when a first voltage signal and a third voltage signal are zero at the same time and is turned off in other situations. The level up shifter circuit according to the embodiments of the present invention can effectively solve the problem that an output state is unknown. | 05-14-2015 |
20150145584 | NEGATIVE LEVEL SHIFTER - A level shifter including a differential input stage including first and second transistors having respective first terminals, respective control terminals configured to receive a differential input signal, and respective second terminals connected in common to a first voltage; a breakdown voltage controller including third and fourth transistors having respective first terminals, respective second terminals connected to respective first terminals of the first and second transistors, and respective control terminals configured to receive a bias signal, and a load stage comprising fifth and sixth transistors having respective first terminals connected to respective first terminals of the third and fourth transistors, respective control terminals that are cross coupled, and respective second terminals connected to a second voltage is disclosed. A bias voltage applied to bulks or bodies of the first through the fourth transistors equals or substantially equals the first voltage. | 05-28-2015 |
20150295561 | VOLTAGE LEVEL SHIFTER MODULE - A voltage level shifter module comprising at least one input arranged to receive an input signal, and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal. The voltage level shifter module further comprises at least one reference voltage control component arranged to detect logical state transitions within the input signal from at least a first logical state to a second logical state, and cause the reference voltage signal applied to the gate of the at least one cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from at least a first logical state to a second logical state. | 10-15-2015 |
20150303921 | WIDE-RANGE LEVEL-SHIFTER - A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal. | 10-22-2015 |
20150303923 | RATIOLESS NEAR-THRESHOLD LEVEL TRANSLATOR - An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width. | 10-22-2015 |
20150304135 | SYSTEM AND METHOD FOR AC COUPLING - An AC coupling circuit is provided that has a level shifter circuit having a p input voltage and an n input voltage and producing a p output voltage and a p output voltage. There is a common mode voltage adjustment feedback circuit configured to cause a common mode voltage output to tend towards a specified reference voltage, the common mode voltage output being an average of the p output and n output voltages of the level shifter circuit. In combination, the level shifter circuit and the feedback circuit allow the interconnection of a first circuit that operates at a first, unspecified, common mode voltage to be connected to a second circuit having a required common mode voltage. The level shifter may be formed of adjustable components such that the frequency response of the level shifter circuit can be adjusted to compensate for a frequency response of an interconnect between the first circuit and the second circuit. | 10-22-2015 |
20150326226 | LOAD SWITCH FOR CONTROLLING ELECTRICAL COUPLING BETWEEN POWER SUPPLY AND LOAD - Circuits and methods for controlling electrical coupling by a load switch are disclosed. In an embodiment, the load switch includes a pass element, level-shift circuit and low-resistance active path. The pass element is configured to be coupled to a power supply and a load, and is configured to electrically couple the power supply with the load during ON-state and electrically decouple the power supply from the load during OFF-state. The level-shift circuit includes a first transistor and pull-up resistor and is configured to generate a level-shifted signal in response to an enable signal, and enable the ON-state and the OFF-state of the pass element based on first and second voltages of the level-shifted signal. The low-resistance active path is coupled in parallel with the pull-up resistor for shunting the pull-up resistor in the OFF-state by providing a path for a leakage current of the first transistor in the OFF-state. | 11-12-2015 |
20150333755 | SAMPLING CIRCUIT FOR SAMPLING SIGNAL INPUT AND RELATED CONTROL METHOD - A sampling circuit for sampling a signal input includes a signal generation circuit, a sampling switch and a control circuit. The signal generation circuit is arranged for generating a first control signal. The sampling switch has a control node, and is arranged for determining a sampling time of the signal input according to a signal level at the control node. The control circuit is arranged for controlling the signal level at the control node, wherein when the signal level at the control node corresponds to a first level, and before a signal level of the first control signal is changed in order to adjust the signal level at the control node to a second level, the control circuit couples the first control signal to the control node. | 11-19-2015 |
20150341022 | HIGH-VOLTAGE LEVEL CONVERSION CIRCUIT - The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area. | 11-26-2015 |
20150341034 | Methods, Circuits, Devices and Systems for Integrated Circuit Voltage Level Shifting - Disclosed is an integrated circuit voltage level shifter including: a first set of pull-up transistors to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on the input and a third set of transistors to limit current flow through the second set of pull-down transistors and to mitigate snapback of the second set of pull-down transistors using a bias gate voltage. | 11-26-2015 |
20150349759 | LEVEL SHIFT CIRCUIT - A level shift circuit includes a first pair of transistors of the first conductive type (M | 12-03-2015 |
20150349777 | SWITCHING CIRCUIT AND ELECTRONIC DEVICE - The present invention provides a switching circuit and an electronic device, which relate to the field of electronic technologies, so as to improve reliability of image processing. The switching circuit includes a comparator circuit, a first switch circuit, a second switch circuit, a first drive voltage source, and a second drive voltage source. Two input ends of the comparator circuit respectively receive an input voltage and a reference voltage, an output end is separately connected to an input end of the first switch circuit and an input end of the second switch circuit; The comparator circuit determines whether the input voltage is greater than the reference voltage, outputs a high level when determining that the input voltage is greater than the reference voltage, and outputs a low level when determining that the input voltage is not greater than the reference voltage. | 12-03-2015 |
20150349778 | LEVEL SHIFTER FOR A TIME-VARYING INPUT - A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit. | 12-03-2015 |
20150349779 | LEVEL SHIFTER FOR A TIME-VARYING INPUT - A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit. | 12-03-2015 |
20150358003 | LEVEL SHIFT CIRCUIT - Provided is a high-reliability level shift circuit not prone to faulty operation due to noise. A level shift circuit | 12-10-2015 |
20150365079 | PULL-UP CIRCUIT AND RELATED METHOD - A device includes a pull-up circuit, first and second switches, and a feedback circuit. The pull-up circuit has a first terminal electrically coupled to a pad, and a second terminal electrically coupled to a first power node. The first switch has a first terminal electrically coupled to a first control terminal of the pull-up circuit, and a second terminal electrically coupled to a second control terminal of the pull-up circuit. The feedback circuit has a first terminal electrically coupled to the pad, and a feedback terminal. The second switch has a first terminal electrically coupled to the first control terminal of the pull-up circuit, a second terminal electrically coupled to the feedback terminal of the feedback circuit, and a control terminal electrically coupled to a second power node. | 12-17-2015 |
20160036442 | LEVEL SHIFTING APPARATUS AND METHOD OF USING THE SAME - A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter. | 02-04-2016 |
20160036443 | FAST LOW POWER LEVEL SHIFTERS - In one embodiment, a method for increasing speed of a differential input pair, The method comprises applying a first boost current to a first input of the differential input pair during a transition of a first signal applied to the first input; storing the first boost current; ending the application of the first boost current in response to the stored first boost current exceeding a first threshold; applying a second boost current to a second input of the differential input pair during a transition of a second signal applied to the second input; storing the second boost current; and ending the application of the second boost current in response to the stored second boost current exceeding a second threshold. | 02-04-2016 |
20160036444 | FAST VOLTAGE DOMAIN CONVERTERS WITH SYMMETRIC AND SUPPLY INSENSITIVE PROPAGATION DELAY - In one embodiment, a circuit comprises a phase interpolator that converts a single-ended input to a pair of symmetric differential signals within a first voltage domain. The circuit further comprises a comparator that converts the symmetric differential signals into single-ended output in a second different voltage domain. In one embodiment, the single ended output of the comparator is configured to be coupled to drive a switching driver in a switching regulator. In one embodiment, the interpolator comprises a first inverter, a second inverter, and a third inverter connected in series. The interpolator further comprises a first resistor and a second resistor connected in series. The second inverter provides a first output signal. Outputs of the first inverter and the third inverter are connected by the series connected resistors. A node between the resistors provides a second output signal. The first and second output signals are inverted and symmetric. | 02-04-2016 |
20160054368 | LEVEL SHIFT CIRCUIT WITH SHORT-CIRCUIT DETECTION MECHANISM AND SHORT-CIRCUIT DETECTION METHOD THEREOF - A level shift circuit includes a level shift module and a voltage comparing module. The level shift module includes a plurality of stages of level shift units, each including a front-end circuit and an inverter circuit. The inverter circuit is electrically coupled to the front-end circuit and receives and inverts an output signal of the front-end circuit. The front-end circuit receives a clock signal, converts high/low voltage level of the clock signal into first/second voltage level, respectively, and outputs a respective signal with the first/second voltage level. The voltage comparing module is coupled to the level shift module and receives output signals of the inverter circuit of the first level shift unit and of the front-end circuit in the second level shift unit and compares the two output signals. The voltage comparing module outputs a short-circuit protection trigger signal when the two output signals have different voltages. | 02-25-2016 |
20160056802 | Level Shifter - A level shifter for high-speed level shifting includes a first P-channel transistor, comprising a gate coupled to a drain, and a source coupled to a system voltage; a second P-channel transistor, comprising a gate coupled to the gate of the first P-channel transistor, and a source coupled to the system voltage; a first N-channel transistor, comprising a drain coupled to the drain of the first P-channel transistor, and a source coupled to a ground level; and a second N-channel transistor, comprising a drain coupled to a drain of the second P-channel transistor, and a source coupled to the ground level; wherein the first N-channel transistor and the second N-channel transistor are low-threshold-voltage transistors or native transistors. | 02-25-2016 |
20160056822 | HIGH SPEED LEVEL TRANSLATOR - A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state. | 02-25-2016 |
20160079964 | INTEGRATED LEVEL SHIFTER - GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. | 03-17-2016 |
20160087613 | Fast Voltage Level Shifter Circuit - A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate. | 03-24-2016 |
20160094207 | VOLTAGE GENERATOR WITH CHARGE PUMP AND RELATED METHODS AND APPARATUS - Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In an embodiment, an apparatus includes a voltage generator, a level shifter, and a semiconductor-on-insulator radio frequency (RF) switch configured to receive a signal from the level shifter. The voltage generator can include a charge pump configured to provide an output voltage, a comparator configured to generate an enable signal based on comparing an indication of a voltage level of the output voltage with a reference value, and an oscillator configured to activate based on the enable signal and to provide a clock signal to the charge pump. The level shifter can receive the output voltage from the charge pump and perform level shifting. | 03-31-2016 |
20160094208 | Dynamic Level Shifter Circuit - A level shifter does not require any DC (standby) current consumption and has a fast operation with low propagation delay. The level shifting from input to output voltage ranges is performed by a pair of level shifting capacitors. The input-output power voltages domains are unrestricted and flexible. DC isolation is deployed between power domains. Symmetrical rise/fall times are without duty cycle distortion. Over voltage stress is reduced by using metal capacitors. Finally the level shifter does not use high-voltage devices for level shifting purpose. Embodiments of level shifters provide one-way level shifting and bi-directional level shifting. | 03-31-2016 |
20160099715 | LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR DEVICE - A level shift circuit includes: a latch circuit (Q | 04-07-2016 |
20160105163 | LOW-VOLTAGE TO HIGH-VOLTAGE LEVEL SHIFTER CIRCUIT - A low-voltage to high-voltage level shifter circuit includes an input circuit, a voltage shifting circuit, and an output circuit. The input circuit is configured to receive an input signal having a voltage range between a first voltage and a ground voltage, and to provide an inverted input signal and a delayed version of the inverted input signal. The voltage shifting circuit is coupled to the input circuit and is configured to receive the input signal, the inverted input signal, and the delayed version of the inverted input signal. The voltage shifting circuit is configured to provide an internal signal having a voltage range between a second voltage and the ground voltage, the second voltage being higher than the first voltage. The output circuit provides an output voltage in the high-voltage range for the corresponding input voltage in the low-voltage range. | 04-14-2016 |
20160105183 | RECEIVER CIRCUIT AND SIGNAL RECEIVING METHOD THEREOF - Provided is a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground. | 04-14-2016 |
20160112047 | LEVEL SHIFTER - A level shifter includes a first and a second transistor coupled to a first power supply voltage terminal supplied with a second power supply voltage in parallel, a third and a fourth transistor coupled to a reference voltage terminal in parallel, a first and a second depression transistor, the first depression transistor being coupled between the first and the third transistor, and a timing control unit placed between a second power supply voltage terminal supplied with a second power supply voltage lower than the first power supply voltage and the reference voltage terminal, that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal. | 04-21-2016 |
20160118986 | Apparatus for Reference Voltage Generation for I/O Interface Circuit - An apparatus includes a first input/output (I/O) interface circuit having a maximum voltage rating. The first I/O interface circuit includes a level shifter and an output stage. A reference voltage bias generator is coupled to the first I/O interface circuit, to a first supply voltage, and to a first ground potential. The reference voltage bias generator is configured to generate a plurality of reference bias signals, including a first reference voltage and a second reference voltage. When the first supply voltage is not greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage and the second reference voltage is equal to the first ground potential. When the first supply voltage is greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage times a first fraction, and the second reference voltage is equal to the first supply voltage times a second fraction. | 04-28-2016 |
20160126955 | Apparatus for Mixed Signal Interface Circuitry and Associated Methods - An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks. | 05-05-2016 |
20160126956 | NEGATIVE-LEVEL SHIFTING CIRCUIT AND A SOURCE DRIVER AND A DISPLAY DEVICE USING THE CIRCUIT - A negative-level shifting circuit includes a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit, and a second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level. The first level shifter further includes a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region. | 05-05-2016 |
20160134286 | HIGH-SPEED LEVEL-SHIFTING MULTIPLEXER - Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down. | 05-12-2016 |
20160142054 | VOLTAGE SCALING FOR HOLISTIC ENERGY MANAGEMENT - A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication. | 05-19-2016 |
20160163361 | DATA OUTPUT CIRCUIT - A data output circuit includes a first trigger unit and a signal generation unit. The first trigger unit is inputted with first data in a first mode and a second mode, and outputs the first data in response to a first trigger signal. The signal generation unit, in the first mode, outputs the first trigger signal in response to a first clock signal, and, in the second mode, retains the first trigger signal in a first state regardless of the first clock signal. | 06-09-2016 |
20160164523 | INTERFACE SUPPLY CIRCUIT - An interface supply circuit includes a power supply unit, a first control circuit coupled to the power supply unit, a second control coupled to the circuit power supply unit, and an output unit. The output unit is coupled to the first control circuit and the second control circuit. The first control circuit is configured to output a first voltage via the output unit when a system is in a normal state. The second control circuit is configured to output a second voltage via the output unit when the system is in a stand-by state. | 06-09-2016 |
20160164525 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2016 |
20160173070 | HIGH-SPEED LEVEL SHIFTER | 06-16-2016 |
20160173092 | CURRENT STEERING LEVEL SHIFTER | 06-16-2016 |
20160173093 | METHOD FOR PERFORMING SIGNAL DRIVING CONTROL IN AN ELECTRONIC DEVICE WITH AID OF DRIVING CONTROL SIGNALS, AND ASSOCIATED APPARATUS | 06-16-2016 |
20160173095 | LEVEL SHIFTING CIRCUIT, APPARATUS AND METHOD OF OPERATING THE SAME | 06-16-2016 |
20160173096 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE | 06-16-2016 |
20160173097 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE | 06-16-2016 |
20160182047 | METHOD FOR COMMUNICATION ACROSS VOLTAGE DOMAINS | 06-23-2016 |
20160182051 | Level-Shifter Circuit for Low-Input Voltages | 06-23-2016 |
20160191027 | VOLTAGE LEVEL SHIFTER FOR HIGH VOLTAGE APPLICATIONS - A voltage level shifter for high voltage applications has a low voltage domain current mirror having first and second branches. A high voltage switch and a resistor are connected in series with the second branch. An output stage provides an output signal that is a function of a voltage difference across the resistor, and the output stage and the resistor are in the high voltage domain. Assertion of an input signal in the low voltage domain develops a first current in the first branch, and causes the high voltage switch to pass in the resistor a second current from the second branch that is a function of the first current and develops the voltage difference across the resistor. Only the high voltage switch needs to have high breakdown voltage characteristics. | 06-30-2016 |
20160204770 | Level Shifter Circuit with Improved Time Response and Control Method Thereof | 07-14-2016 |
20160254213 | STACK PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A VARIABLE VOLTAGE | 09-01-2016 |
20160254807 | REFERENCE VOLTAGE CIRCUIT AND ELECTRONIC DEVICE | 09-01-2016 |
20160254814 | INTERFACE CIRCUIT INCLUDING BUFFER CIRCUIT FOR HIGH SPEED COMMUNICATION, SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME | 09-01-2016 |
20160254815 | TECHNIQUES AND DEVICES FOR LEVEL-SHIFTING A SIGNAL | 09-01-2016 |
20160380632 | VOLTAGE GENERATOR WITH CHARGE PUMP AND RELATED METHODS AND APPARATUS - Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In certain configurations, a negative voltage generator includes a charge pump controllable by a clock signal and configured to provide a negative voltage at an output node, an oscillator configured to activate based on an enable signal and to provide the clock signal to the charge pump, a comparator configured to generate the enable signal based on comparing a feedback voltage with a reference value, a voltage divider electrically connected between a positive voltage node and the output node and configured to generate the feedback voltage at a feedback node, and a start-up capacitor electrically connected between the positive voltage node and the feedback node and configured to control a settling time of the feedback voltage. | 12-29-2016 |
20170237435 | APPARATUSES AND METHODS FOR VOLTAGE LEVEL CONTROL | 08-17-2017 |
20170237437 | Small Area Native Level Shifter | 08-17-2017 |
20170237439 | WIDE OPERATING LEVEL SHIFTERS | 08-17-2017 |
20180026635 | VOLTAGE LEVEL TRANSLATION CIRCUIT AND MULTIPLE INTERFACE IN COMMUNICATION SYSTEM | 01-25-2018 |
20190149153 | HIGH SPEED LEVEL TRANSLATOR | 05-16-2019 |