Class / Patent application number | Description | Number of patent applications / Date published |
327382000 | Parasitic prevention or compensation (e.g., parasitic capacitance, etc.) | 67 |
20090267678 | Integrated Circuit with Improved Data Rate - An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed. | 10-29-2009 |
20110001542 | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals - Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack. | 01-06-2011 |
20110254612 | HIGH-FREQUENCY SWITCH CIRCUIT - A high-frequency switch circuit according to the present invention includes at least a first switch connected between a common terminal and a first terminal, and a second switch connected between the common terminal and a second terminal. Each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate. A compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the first switch. A compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the second switch. | 10-20-2011 |
20120032725 | POWER MODULE - A power module comprises: first and second terminals; first and second switching elements having a first electrode and a second electrode which is connected to the second terminal; first and second wirings respectively connecting the first electrodes of the first and second switching elements to the first terminal; and a third wiring directly connecting the first electrode of the first switching element to the first electrode of the second switching element, wherein parasitic inductances of the first and second wiring are different or switching characteristics of the first and second switching elements are different. | 02-09-2012 |
20120194257 | CONTINUOUS-TIME CIRCUIT AND METHOD FOR CAPACITANCE EQUALIZATION BASED ON ELECTRICALLY TUNABLE VOLTAGE PRE-DISTORTION OF A C-V CHARACTERISTIC - A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor. | 08-02-2012 |
20120262217 | RADIO FREQUENCY MULTI-PORT SWITCHES - A multiport radio frequency (RF) switch circuit is disclosed. The switch circuit includes a first transistor that is connected to a first port, a common antenna port, and a first enable line. The first transistor is selectively activatable in response to a first enable signal applied to the first enable line. There is also a second transistor connected to a second port, the common antenna port, and a second enable line. The second transistor is selectively activatable in response to a second enable signal applied to the second enable line. A first inductor connected to the first port and the second port compensates for parasitic capacitance between the first port and the second port from an inactive one of the transistors. | 10-18-2012 |
20130147540 | SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME - Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench. | 06-13-2013 |
20130271200 | SWITCHED CAPACITOR CIRCUIT UTILIZING DELAYED CONTROL SIGNAL AND INVERTING CONTROL SIGNAL FOR PERFORMING SWITCHING OPERATION AND RELATED CONTROL METHOD - A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal. | 10-17-2013 |
20130278322 | GATE DRIVING APPARATUS - A gate driving apparatus according to the embodiment includes a first switching device, a second switching device that outputs a signal to charge a capacitance of the first switching device, a third switching device connected in parallel to the second switching device to prevent a drop of a voltage output from the second switching device, and a fourth switching device that outputs a signal to discharge the capacitance of the first switching device. An NMOS transistor is used as a main switching device and a PMOS transistor connected in parallel to the NMOS transistor is used as a sub-switching device, so that the chip size is reduced without dropping the output voltage of the gate driving apparatus. The loss of the switching device is prevented by preventing the output voltage of the gate driving apparatus from being dropped. | 10-24-2013 |
20130278323 | High-Frequency Switching Circuit - A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit. | 10-24-2013 |
20130285733 | Voltage Generator With Adjustable Slope - A charging circuit includes a first current mirror for receiving an input voltage, a second current mirror including a first branch circuit and a second branch circuit for receiving the input voltage, a switch transistor coupled to the first current mirror and the first branch circuit for determining a conduction condition of the switch transistor according to a switch signal, a first resistor including a first resistance and one end coupled to the switch transistor, and a second resistor including a second resistance and one end coupled the second branch circuit of the second current mirror, wherein the first current mirror and the second current mirror perform a charging operation of a loading circuit according to the first resistance and the second resistance. | 10-31-2013 |
20130293280 | Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink - A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime. | 11-07-2013 |
20130321061 | CAPACITANCE COMPENSATION CIRCUIT OF A RADIO FREQUENCY SWITCH - An RF switch includes a transistor and a compensation capacitor circuit. The compensation capacitor circuit includes a first compensation capacitor and a second compensation capacitor of the same capacitance. The compensation capacitor circuit is used to improve voltage distribution between a control node and a first node of the transistor and between the control node and a second node of the transistor. | 12-05-2013 |
20130321062 | METHOD FOR CONTROLLING TWO ELECTRICALLY SERIES-CONNECTED REVERSE CONDUCTIVE IGBTS OF A HALF BRIDGE - A method for controlling two electrically series-connected reverse-conductive (RC) IGBTs (RC-IBGT) of a half bridge is disclosed, wherein an operating DC voltage is applied across the series connection and one of the two series-connected reverse-conductive IGBTs operates in IGBT mode and another of the two series-connected reverse-conductive IGBTs operates in diode mode, and wherein each of the two reverse-conductive IGBTs has three switching states “+15V”, “0V”, “−15V”. The RC-IGBT T1 operated in diode mode does not go into the switching state (−15V) of highly charged carrier concentration, but instead into a state of medium charge carrier concentration associated with the switching state “0V”, and not into the switching state “−15V”, as is known from conventional methods. This reduces the reverse-recovery without adversely affecting the forward voltage. | 12-05-2013 |
20140062576 | SEMICONDUCTOR DEVICE - The semiconductor device includes first and second output terminals each coupled to one end side and another end side of an inductive or capacitive load, a first MOS transistor coupled between a first voltage and the first output terminal, a second MOS transistor coupled between a second voltage and the first output terminal, a third MOS transistor coupled between the first voltage and the second output terminal, a fourth MOS transistor coupled between the second voltage and the second output terminal, and a drive circuit driving the first to fourth MOS transistors for controlling the inductive or capacitive load, and further includes first and second bypass transistors for bypassing a forward current of a parasitic diode of a PN-junction formed in the MOS transistor in the dead-off period. | 03-06-2014 |
20140091850 | GATE DRIVING DEVICE - The present invention copes with fluctuations in a power supply voltage when a capacitor for coping with fluctuations in the power supply voltage has been omitted and also cases in which the power supply voltage is constantly low, thereby ensuring driving of an active element. A gate driving device of an IGBT includes: a first switch portion which turns on the IGBT; a second switch portion which turns off the IGBT; a current control portion which controls the outflow of charge on the gate to a ground line such that current is constant; a first protection circuit which suppresses outflow of gate current to the power supply line; and a second protection circuit which detects a prescribed fluctuation in an internal power supply voltage Vdc, and interrupts the connection between the current control portion and the ground line. | 04-03-2014 |
20140103989 | SEMICONDUCTOR POWER MODULES AND DEVICES - An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion. | 04-17-2014 |
20140167834 | Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge - A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body. | 06-19-2014 |
20140184306 | Method for Operating Field-Effect Transistor, Field-Effect Transistor and Circuit Configuration - A method for operating a field-effect transistor having a source terminal, a drain terminal, a gate terminal, a drift region and a dielectric region adjoining the drift region, is provided. The method includes: connecting at least one of the drain terminal and the source terminal to a load; applying a sequence of voltage pulses between the gate terminal and the source terminal to repetitively switch the field-effect transistor such that the field-effect transistor is driven in an avalanche mode between the voltage pulses, during the avalanche mode avalanche multiplication occurring in the drift region close to the dielectric region; and applying at least one relaxation pulse to the field-effect transistor to reduce an accumulation of charges in the dielectric region due to hot charge carriers generated in the avalanche mode. Further, a field-effect transistor and a circuit configuration including the field-effect transistor are provided. | 07-03-2014 |
20140197877 | SYSTEM FOR A CONTACTLESS CONTROL OF A FIELD EFFECT TRANSISTOR - The invention stems from the realization that it is possible to control the electric field in the gate region of a field effect transistor (MOS, FET etc.) without changing the net charge of the gate electrode or without resorting to electrical conduction. According to an aspect of the invention, the electric field is changed by modifying the charge distribution within the gate electrode without materially adding or subtracting charge carriers to it or changing its net charge. This is achieved by displacing one or more sources of electric field, for example free charges, or conductive or non-conductive surface charges in the proximity of the gate electrode. By electric induction, the electric field produce a separation of charges in the gate electrode and an alteration in the conduction state of the FET transistor. | 07-17-2014 |
20140240026 | METHOD AND APPARATUS FOR CONTROLLING A GATE VOLTAGE IN HIGH ELECTRON MOBILITY TRANSISTOR - According to example embodiments, a method for controlling a gate voltage applied to a gate electrode of a high electron mobility transistor (HEMT) may include measuring a voltage between a drain electrode and a source electrode of the HEMT, and adjusting a level of the gate voltage applied to the gate electrode of the HEMT according to the measured voltage. The level of the gate electrode may be adjusted if the voltage between the drain electrode and the source electrode is different than a set value. | 08-28-2014 |
20140240027 | VERTICAL INSULATED-GATE TURN-OFF DEVICE HAVING A PLANAR GATE - An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation. | 08-28-2014 |
20140253217 | RF Switch Gate Control - In one implementation, a switching circuit includes a pass switch including group III-V, for example III-Nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch. | 09-11-2014 |
20140266394 | HIGH-SPEED SWITCH WITH SIGNAL-FOLLOWER CONTROL OFFSETTING EFFECTIVE VISIBLE-IMPEDANCE LOADING - A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal. | 09-18-2014 |
20140300404 | RF MEMS ISOLATION, SERIES AND SHUNT DVC, AND SMALL MEMS - The present invention generally relates to an architecture for isolating an RF MEMS device from a substrate and driving circuit, series and shunt DVC die architectures, and smaller MEMS arrays for high frequency communications. The semiconductor device has one or more cells with a plurality of MEMS devices therein. The MEMS device operates by applying an electrical bias to either a pull-up electrode or a pull-down electrode to move a switching element of the MEMS device between a first position spaced a first distance from an RF electrode and a second position spaced a second distance different than the first distance from the RF electrode. The pull-up and/or pull-off electrode may be coupled to a resistor to isolate the MEMS device from the substrate. | 10-09-2014 |
20140312957 | Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals - Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack. | 10-23-2014 |
20140320194 | SOLID STATE POWER CONTROLLER GATE CONTROL - A system for controlling gate power includes a metal oxide semiconductor field effect transistor (MOSFET) configured to supply power to a load according to a gate control voltage applied to a gate of the MOSFET. The system includes a gate control circuit configured to turn on and off the gate control voltage supplied to the gate of the MOSFET. The system also includes a ramping circuit configured to perform at least one of ramping up a voltage applied to the gate of the MOSFET based on the gate control circuit turning on power to the gate of the MOSFET and ramping down the voltage applied to the gate of the MOSFET based on the gate control circuit turning off power to the gate of the MOSFET. | 10-30-2014 |
20140320195 | UNIVERSAL CONTACT INPUT APPARATUS AND METHOD FOR OPERATING THE SAME - At a contact input circuit, a voltage at a switching device is sensed and the voltage is associated with a status of a switching device. The contact input circuit is operated according to the sensed voltage regardless of the value of the sensed voltage. The power usage of the contact input circuit is maintained to be within a predetermined range of power consumption values regardless of the value of the sensed voltage. Wetting voltages can be continuously monitored and the approaches described herein can monitor open contact, closed contact, and open field wire conditions. | 10-30-2014 |
20140320196 | Control Device and Method for Actuating a Semiconductor Switch - A control device for influencing a flow of energy in a load circuit between an electrical voltage source and an electrical load, having a semiconductor switch including a conductive section which is formed between an input connection and an output connection, can be looped into the load circuit, and has an electrical resistance adjustable by means of an electrical potential which can be applied to a control connection associated with the semiconductor switch, and having a control circuit which is coupled to the control connection and includes a freewheeling means connected in parallel to the load. The control circuit is designed to supply a control current at the control connection which is proportional to a voltage via the freewheeling means. | 10-30-2014 |
20140375376 | ADAPTIVE MOS TRANSISTOR GATE DRIVER AND METHOD THEREFOR - In an embodiment, a gate driver circuit and/or method therefor may include configuring the gate driver circuit form a drive current to supply to a gate of an MOS transistor wherein the value of the drive current is a minimum value that can be supplied to the gate without increasing a charge stored on a gate-to-source capacitance of the MOS transistor; configuring the gate driver circuit to change the value of the drive current responsively to changes of a Vgs of the MOS transistor. | 12-25-2014 |
20150015319 | DEVICES FOR SHIELDING A SIGNAL LINE OVER AN ACTIVE REGION - A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line. | 01-15-2015 |
20150022257 | SWITCHING DEVICE AND MODULE - A switching device includes: a switch that selects and connects one of at least three terminals including a first terminal, a second terminal, and a third terminal to a common terminal; and a compensating circuit that shifts a phase of at least one of a first signal transmitted through the second terminal and a second signal transmitted through the third terminal so that the first signal and the second signal compensate each other and unifies and outputs the first signal and the second signal to a fourth terminal as a third signal, or that branches a third signal input to the fourth terminal into the first signal and the second signal. | 01-22-2015 |
20150028933 | GATE DRIVING CIRCUIT FOR DISPLAY - A gate driving circuit for a display is disclosed. The gate driving circuit utilizes at least one transistor connected in series between an input end of a reference voltage signal and a transistor connected to a node providing a high voltage level for making the at least one transistor share the voltage difference between the source electrode and the drain electrode of the transistor connected to the node. In such a manner, the gate driving circuit can reduce the occurrence of current leakage in the transistor, thereby improving the stability of driving voltage of the gate driving circuit and the reliability of the gate driving circuit. | 01-29-2015 |
20150035581 | SWITCH CIRCUIT ARRANGEMENTS AND METHOD FOR POWERING A DRIVER CIRCUIT - In various embodiment, a switch circuit arrangement is provided. The switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state. | 02-05-2015 |
20150035582 | BODY BIAS SWITCHING FOR AN RF SWITCH - Embodiments of radio frequency (RF) switching circuitry are disclosed that include (at least) a first switch and a body switching network operably associated with the first switch. The first switch has a first control contact, a first switch contact and a first body contact. The body switching network includes a first switchable path and a second switchable path. The first switchable path is connected between the first body contact and the first control contact of the first switch. Additionally, the second switchable path is connected between the first body contact and the first switch contact. Accordingly, the first body contact is can be appropriately biased by the switchable paths without requiring a resistor network and thus there is less loading. This maintains the Q factor of the RF switching circuitry. | 02-05-2015 |
20150035583 | FIELD DEVICE AND METHOD OF OPERATING HIGH VOLTAGE SEMICONDUCTOR DEVICE APPLIED WITH THE SAME - A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region. | 02-05-2015 |
20150054567 | LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION - A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level. | 02-26-2015 |
20150054568 | LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION - A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together. | 02-26-2015 |
20150054569 | SWITCH CIRCUIT - According to one embodiment, a switch circuit includes a transmission unit configured to transmit a signal through a transistor, in which a back gate and a source are connected by way of a resistor; and a back gate control unit configured to connect the back gate of the transistor to a fixed potential when the transistor is turned OFF, and to separate the back gate of the transistor from the fixed potential when the transistor is turned ON. | 02-26-2015 |
20150061748 | SWITCH CIRCUIT - A switching circuit includes a plurality of switching elements connected between an input node and an output node and each comprising a first and second electrode connected to the input node and output node, respectively. The switching elements include a control electrode for controlling electrical conductance between the first and second electrodes such the switching element can be switched between an ON conductance state and an OFF conductance state. A detection circuit in the switching circuit outputs a detection value corresponding to an output current at the output node. A control circuit changes the conductance state of at least one switching element such that the summed total of the parasitic capacitances of all switching elements in the ON state decreases as the output current decreases as indicated by the detection value. | 03-05-2015 |
20150070074 | CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY - Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node. | 03-12-2015 |
20150084685 | CASCODE TRANSISTOR AND METHOD OF CONTROLLING CASCODE TRANSISTOR - A cascode transistor includes: a first switch; a second switch that has a withstand voltage higher than that of the first switch and is cascade coupled to a drain of the first switch; and a circuit in which a third switch and a capacitor are coupled in series with each other and that is provided between a connection node and a source of the first switch, the connection node being a node at which the first switch and the second switch are coupled to each other. | 03-26-2015 |
20150091634 | GATE CONTROL CIRCUIT FOR MOS SWITCH - A gate drive circuit is disclosed that charges the gate of a switching transistor to a voltage that is high enough to turn the switching transistor fully on and then prevent the charge from flowing back into the gate drive circuit. The gate drive circuit works with a ground rectifier switch by providing a fully differential connection of the switching transistor and its capacitor and resistor in parallel with the antenna. | 04-02-2015 |
20150097613 | GATE CLAMPING - A circuit is described that includes a switch, a switchable clamping element coupled to the switch, and a driver configured to control the switch based at least in part on a driver control signal. The driver is further configured to enable or disable the switchable clamping element. The switchable clamping element is configured to clamp a voltage across the switch when the switchable clamping element is enabled by the driver and when the voltage across the switch or a current at the switch satisfies a threshold for activating the switchable clamping element. | 04-09-2015 |
20150102850 | DECOUPLING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes. | 04-16-2015 |
20150130530 | CURRENT LEAKAGE MITIGATION - One or more circuits are provided wherein leakage current is mitigated. A circuit comprises a pad, a first transistor, a second transistor, a power leakage component and a data leakage component. The first transistor and the second transistor are respectively configured to control a voltage level at the pad. The first transistor is connected to the pad and to a first voltage source. The second transistor is connected to the pad and to a third voltage source. The power leakage component is connected between the first transistor and the pad. The data leakage component is connected between the second transistor and the pad. The power leakage component is configured to mitigate leakage current from the first transistor to the pad. The data leakage component is configured to mitigate leakage current from the pad to the second transistor. | 05-14-2015 |
20150145587 | HIGH FREQUENCY SEMICONDUCTOR SWITCH CIRCUIT AND HIGH FREQUENCY RADIO SYSTEM INCLUDING SAME - A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an inverter circuit having a first internal power supply voltage (e.g., 2.5 V) as a power supply. The sources and drains of the path switching FET and the shunt FET are controlled using an inverter circuit having a second internal power supply voltage (e.g., 1.25 V) which is smaller than the first internal power supply voltage, as a power supply. | 05-28-2015 |
20150295572 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 10-15-2015 |
20150333748 | SEMICONDUCTOR DEVICE - A horizontal MOSFET is arranged in parallel to a horizontal MOSFET and a portion of a return current IL which flows to a linear solenoid flows as a current to the horizontal MOSFET. Therefore, a current which flows to a parasitic transistor is reduced and it is possible to suppress the current which flows to the parasitic transistor provided in the horizontal MOSFET. Since the current which flows to the parasitic transistor is reduced, it is possible to prevent the erroneous operation and breakdown of a semiconductor device forming a synchronous rectification circuit. | 11-19-2015 |
20150341025 | DIFFERENTIAL MODE BANDWIDTH EXTENSION TECHNIQUE WITH COMMON MODE COMPENSATION - A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors. | 11-26-2015 |
20150341026 | TRANSISTOR BASED SWITCH STACK HAVING FILTERS FOR PRESERVING AC EQUIPOTENTIAL NODES - A device for switching a radio frequency (RF) signal includes two or more field-effect transistor (FET) unit cells in a stacked or chain topology, and gate or body node filtration circuitry that preserves RF equipotential nodes. The filtration circuitry may be capacitive or resistive-capacitive. The filtration circuitry may be included in each unit cell of the device or in a gate or body bias network that is common to all unit cells in the device. | 11-26-2015 |
20150349771 | SEMICONDUCTOR DEVICE AND CASCODE CIRCUIT - A semiconductor device and a cascode circuit are disclosed herein. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first electrode, a second electrode, a control electrode, and a control pad. The second transistor includes a first electrode, a second electrode, a control electrode, and a control pad. The second electrode of the first transistor is configured to receive a first predetermined voltage. The control electrode of the first transistor is configured to receive an input signal. The first electrode of the second transistor configured to receive a second predetermined voltage. The second electrode of the second transistor is electrically coupled to the first electrode of the first transistor. The control pad is disposed between the first electrode of the second transistor and the control electrode of the second transistor, and is configured to receive a first adjust signal. | 12-03-2015 |
20150365084 | CIRCUITS AND METHODS FOR OPERATING A CIRCUIT - According to various examples, circuits, detection circuits, methods for operating circuits and methods for operating power supplies are described herein. As one example, a circuit includes a transistor and a detection circuit. A voltage is coupled across two controlled terminals of the transistor and the transistor is configured to be in a non-conducting state. The detection circuit is coupled to a control terminal of the transistor. The detection circuit is configured to detect at least one of: a signal due to a voltage coupled across the two controlled terminals; a signal due to a change in the voltage coupled across the two controlled terminals; and a change in a signal at the control terminal due to a change in the voltage coupled across the two controlled terminals. | 12-17-2015 |
20150381160 | ROBUST MULTIPLEXER, AND METHOD FOR OPERATING A ROBUST MULTIPLEXER - Multi-channel multiplexers and a method for operating a multi-channel multiplexer are presented, wherein each of a plurality of input channels includes at least one doped bulk well of a conductivity type. The method further includes blocking each input channel of a selection of the plurality of input channels by at least one corresponding control voltage, and bringing each of the at least one doped bulk well of each of the input channels of the selection of the plurality of input channels to an at least one corresponding predetermined voltage. At least one corresponding predetermined voltage is, depending on the conductivity type, either smaller than the corresponding control voltage, or larger than the corresponding control voltage. | 12-31-2015 |
20150381162 | LOW LEAKAGE ANALOG SWITCH - A semiconductor isolating switch has two series connected primary field effect transistors (FET), a first one the primary FETs is coupled between a first node and an intermediate node, and a second one of the primary FETs is coupled between the intermediate node and a second node. A controllable pull-up FET is coupled in series to a controllable pull-down FET. The controllable pull-up FET is coupled between a power rail node and a common node and the controllable pull-down FET is coupled between the common node and a ground rail node. A leakage control transistor is coupled between the common node and the intermediate node. The gates of all of the transistors are coupled to a switch control node. | 12-31-2015 |
20160020760 | SWITCHING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a switching circuit capable of transmitting a signal with large amplitude and large current while suppressing deterioration when a small-amplitude signal is transmitted. The switching circuit | 01-21-2016 |
20160020761 | TRANSMISSION CIRCUIT WITH LEAKAGE PREVENTION CIRCUIT - A transmission circuit includes: a first transistor, having a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit; a second transistor, having a source terminal coupled to a gate of the first transistor, and a drain terminal coupled to the first output terminal of the transmission circuit; and a third transistor, having a drain terminal coupled to the first output terminal of the transmission, a source terminal coupled to a second reference voltage terminal of the transmission, and a gate terminal for receiving a first input signal; wherein the first and second transistors are of a first conducting type, and the third transistor is of a second conducting type different from the first conducting type. | 01-21-2016 |
20160043712 | SEMICONDUCTOR DEVICE FOR WIRELESS COMMUNICATION - Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors. | 02-11-2016 |
20160049929 | SWITCHABLE FREQUENCY FILTER - The invention relates to a filter, for example, a switchable harmonic filter for the gigahertz range. A first line segment, which can comprise a radial stub leads away from a main line of the filter. A second line segment can be electrically connected to the first line segment. At least two electronically controllable switching elements are provided, by means of which the first and the second line segment can be connected. | 02-18-2016 |
20160056809 | LEAKAGE CURRENT REDUCTION IN STACKED FIELD-EFFECT TRANSISTORS - A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer. | 02-25-2016 |
20160065201 | REFERENCE CURRENT SETTING CIRCUIT - A reference current setting circuit according to one embodiment includes a first terminal, a first current mirror circuit, a second current mirror circuit, and a third current mirror circuit. The first terminal is connected to a ground potential via a first resistor. The first current mirror circuit includes a first transistor with a source connected to a reference voltage and a drain serving as a first input terminal, and a second transistor with a source connected to the first terminal and a drain serving as a first output terminal, the drain of the first transistor being connected to a gate of the first transistor and a gate of the second transistor. | 03-03-2016 |
20160087624 | HIGH FREQUENCY SWITCH CIRCUIT - A high frequency switch circuit including a first terminal, a second terminal, a bias terminal, n (n is an integer more than one) number of transistors connected in series in an order from a first transistor to an nth transistor from said first terminal to said second terminal, first to nth nodes respectively connected to back gates of said first to nth transistors, and n number of resistance elements connected in series in an order from a first resistance element to an nth resistance element from said bias terminal to said nth node, wherein said first resistance element is connected between said bias terminal and said first node, and a kth resistance element (k=2 to n) is connected between said (k−1)th node and said kth node. | 03-24-2016 |
20160126943 | High Frequency Absorptive Switch Architecture - An absorptive switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common terminal and one or more ports, any of which may be selectively coupled to the common terminal by closing an associated path switch; non-selected, unused ports are isolated from the common terminal by opening an associated path switch. Between each path switch and a port are associated shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated absorptive switch module. Each absorptive switch module includes a resistor coupled in parallel with a switch. The combination of the resistor and the switch of the absorptive switch module is placed in series with a corresponding signal path from each port to the common terminal, rather than in a shunt configuration. | 05-05-2016 |
20160191039 | Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements when Connected Between Terminals - Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack. | 06-30-2016 |
20160191040 | Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink - A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime. | 06-30-2016 |
20160191050 | Tuning Capacitance to Enhance FET Stack Voltage Withstand - An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero. | 06-30-2016 |
20170237423 | High Frequency Absorptive Switch Architecture | 08-17-2017 |