Entries |
Document | Title | Date |
20080205179 | INTEGRATED CIRCUIT HAVING A MEMORY ARRAY - An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed. | 08-28-2008 |
20080225618 | Non-Volatile Semiconductor Memory - A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells. | 09-18-2008 |
20080232184 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a memory comprising memory cells including floating bodies, logic data being stored in the memory cells; word lines connected to gates of the memory cells; bit lines connected to the memory cells; and sense amplifiers connected to the bit lines, and applying a first voltage to the bit lines when first logic data is written to the memory cells connected to the bit lines, wherein the sense amplifiers apply a second voltage to the memory cells having stored therein the first logic data during a refresh operation in which at least second logic data stored in the memory cells is recovered, the second logic data is opposite in logic to the first logic data, and the second voltage is lower in absolute value than the first voltage and equal to or higher in absolute value than a potential of sources of the memory cells. | 09-25-2008 |
20080266992 | DRAM WITH HYBRID SENSE AMPLIFIER - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein the memory cells are constructed using I/O transistors. | 10-30-2008 |
20080279025 | Electronic Circuit with Memory for Which a Threshold Level is Selected | 11-13-2008 |
20080279026 | Signal sensing circuit and semiconductor memory device using the same - A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level. | 11-13-2008 |
20080298150 | Semiconductor device - A semiconductor device includes a DRAM cell configured to store a data; and a sense amplifier activated in response to supply of power supply voltages and configured to sense the data stored in the DRAM cell. A power supply circuit supplies the power supply voltages to the sense amplifier. A sense amplifier dummy circuit provides a replica of a state of the sense amplifier immediately after the activation of the sense amplifier; and a power supply control circuit controls the power supply circuit based on the replica such that the power supply voltages are varied with time. | 12-04-2008 |
20080298151 | Sense Amplifier Overdriving Circuit and Semiconductor Device Using the Same - A sense amplifier overdriving circuit includes a first voltage driver which supplies an internal voltage from an internal voltage terminal to a sense amplifier in response to a first enabling signal, a logic unit which logically operates a block select signal for selection of a cell block and a second enabling signal enabled for a predetermined time after enabling of the first enabling signal, and outputs the resultant signal, and a second voltage driver which supplies an external voltage to the internal voltage terminal in response to the signal output from the logic unit. A semiconductor device using the sense amplifier overdriving circuit is also disclosed. | 12-04-2008 |
20080310244 | Digital filters with memory - A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter. | 12-18-2008 |
20080310245 | Digital filters for semiconductor devices - A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor. | 12-18-2008 |
20090010086 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential output voltages to a sense amplifier output line pair. The voltage sense amplifier is coupled to the sense amplifier output line pair to amplify the differential output voltages on the sense amplifier output line pair. The voltage sense amplifier is activated at the time later than a time of activation of the current sense amplifier. The output stabilizing circuit is coupled to the sense amplifier output line pair to stabilize the differential output voltages on the sense amplifier output line pair. The output stabilizing circuit has a positive input resistance. Accordingly, the sense amplifier circuit reduces power consumption and an occupied area on a semiconductor chip. | 01-08-2009 |
20090022001 | SEMICONDUCTOR MEMORY DEVICE - By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON. | 01-22-2009 |
20090059703 | RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals. | 03-05-2009 |
20090067274 | MEMORY DEVICE HAVING AN EVALUATION CIRCUIT - A memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of the bit line and the reference line. Inputs of the evaluation circuit are directly connected to the bit line. Outputs of the evaluation circuit are coupled to the bit line via a switch. | 03-12-2009 |
20090073792 | Wide databus architecture - A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs. | 03-19-2009 |
20090109780 | HYBRID STATIC AND DYNAMIC SENSING FOR MEMORY ARRAYS - A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit. | 04-30-2009 |
20090122630 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - An exemplary aspect of the present invention is a sense amplifier having a power supply voltage of 1.2 V or lower and amplifying a potential difference between a bit line pair, a first transistor supplying the power supply voltage to the sense amplifier, a second transistor supplying a low potential side voltage to the sense amplifier, and a control circuit controlling the first transistor to be a conduction state before the second transistor is set to the conduction state or at the same time when the second transistor is set to the conduction state. | 05-14-2009 |
20090129188 | Devices and methods for a threshold voltage difference compensated sense amplifier - Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes. | 05-21-2009 |
20090168576 | SEMICONDUCTOR MEMORY DEVICE - A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays. | 07-02-2009 |
20090168577 | SEMICONDUCTOR STORAGE DEVICE, AND DATA READING METHOD - A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge. | 07-02-2009 |
20090245002 | SEMICONDUCTOR MEMORY DEVICE HAVING HIGH STABILITY AND QUALITY OF READOUT OPERATION - A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second column line connected to the other terminal of the memory cells adjacent to the one terminal of the memory cell storing the data to be readout, a second multiplexer selecting the sub-block including the second column line, a source selector selecting a third column line connected to the other terminal of the memory cell storing the data to be read out. The second multiplexer and precharge selector, when selecting, apply a first voltage to the second column line, and the source selector, when selecting, applies a second voltage to the third column line. | 10-01-2009 |
20090257298 | Semiconductor device having single-ended sensing amplifier - A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit line, and a global bit line voltage determination circuit; and at least the ON/OFF timing of the second MOS transistor or the read timing of a global sense amplifier that includes the global bit line voltage determination circuit is controlled by the output signal of a delay circuit that includes a replica of the first MOS transistor and a replica of the global bit line voltage determination circuit. | 10-15-2009 |
20090268537 | Semiconductor memory device - A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory. | 10-29-2009 |
20090279371 | HYBRID SENSE AMPLIFIER AND METHOD, AND MEMORY DEVICE USING SAME - Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The sensing circuit has first and second complementary output nodes and is coupled to the data lines. In a first mode, the sensing circuit can sense a difference between a voltage on the first digit line and a voltage on the second digit line to generate a first voltage differential between the first and second output nodes. In a second mode, the sensing circuit can sense a difference between a current flow in the first digit line and a current flow in the second digit line to generate a second voltage differential between the first and second output nodes. Other sense circuits, devices and methods are also provided. | 11-12-2009 |
20090290443 | MEMORY CIRCUIT WITH SENSE AMPLIFIER - A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal and the reference signal. The comparator further includes a first output stage for generating a first comparator output signal by comparing the output signal and the bias signal. The comparator further includes a second output stage for generating a second comparator output signal by comparing the reference signal and the bias signal. | 11-26-2009 |
20090310431 | SEMICONDUCTOR DEVICE INCLUDING CAPACITORLESS RAM - There is provided a semiconductor device including a capacitorless RAM. The semiconductor device includes a field effect transistor (FET) having a floating body structure. FET includes a channel body region arranged in a first region comprising a first semiconductor (e.g., p-SiGe) having a given band gap and a second region comprising a second semiconductor (e.g., n-Si) having a larger band gap than the first semiconductor. | 12-17-2009 |
20090310432 | BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized. | 12-17-2009 |
20100020627 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a cell array; bit lines; word lines; sense amplifiers; first determination transistors receiving information data and making a connection between a first voltage source and a first determination node be in a conductive or a non-conductive state based on a logic value of the information data; second determination transistors receiving the information data detected by the sense amplifiers and making a connection between the first voltage source and a second determination node be in a conductive or a non-conductive state based on the logic value of the information data; a second voltage source charging the first and the second determination nodes; and a determination unit detecting potentials of the first determination node and the second determination node when a logic of the information data is inverted logically to determine maximum and minimum values of potential of the information data. | 01-28-2010 |
20100054066 | Memory device, semiconductor memory device and control method thereof - A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation. | 03-04-2010 |
20100061170 | Sense amplifier circuit and semiconductor memory device - A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor supplies a predetermined voltage to the bit line and switches connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor having a gate connected to the sense node amplifies a signal transmitted from the bit line via the first MOS transistor. The first voltage setting circuit sets the bit line to a first voltage, and the second voltage setting circuit sets the sense node to a second voltage. In the sense amplifier circuit, after setting the bit line and the sense node to respective voltages, the bit line is driven in a charge distributing mode via the first MOS transistor so that a signal voltage at the sense node is amplified by the second MOS transistor. | 03-11-2010 |
20100067317 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair. The controller is configured to set an operating mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal. The sense amplifier driver is configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal. | 03-18-2010 |
20100074041 | SEMICONDUCTOR DEVICE INCLUDING ASYMMETRIC SENSE AMPLIFIER - A semiconductor device includes an alternating arrangement of memory cell blocks and sense amplifier blocks, such that the sense amplifier blocks include an interior sense amplifier block and a periphery amplifier block. The peripheral amplifier block includes a first sense amplification unit having a first sense amplifier and a second sense amplifier cross-coupled between a bit line and a complementary bit line. The first sense amplifier supplies/receives current to/from the bit line, the second sense amplifier provides/receives current to/from the complementary bit line, and a current driving capability for the first sense amplifier is greater than a current driving capability of the second sense amplifier. | 03-25-2010 |
20100103758 | Semiconductor memory device having sense amplifier - To provide a first power supply wiring that supplies a lower-side write potential to a sense amplifier, a second power supply wiring that supplies a higher-side write potential to the sense amplifier, a third power supply wiring that supplies an overdrive potential to the sense amplifier, and a stabilizing capacitance arranged between the first power supply wiring and the third power supply wiring. With this configuration, a capacitance value applied to the lower-side write potential and a capacitance value applied to the overdrive potential inevitably match, and thus fluctuation of the lower-side write potential and fluctuation of the overdrive potential at an initial stage of a sense operation are offset. | 04-29-2010 |
20100149895 | High speed carbon nanotube memory - In order to realize high speed carbon nanotube memory, bit line is multi-divided into short lines for reducing parasitic capacitance. For reading, a small local sense amp is composed of a local pre amplifier and a local main amplifier with high gain, and a simple global sense amp is composed of an inverter as amplifying circuit for receiving an output of the local sense amp through a global bit line. By the sense amps, time domain sensing scheme is realized such that a voltage difference in the bit line is converted to a time difference as an output of the global sense amp, for differentiating high data and low data. In this manner, fast read operation is realized with fast sensing circuit. And alternative circuits are described. Particularly, field-effect alignment process is realized for aligning the carbon nanotubes on exact location of the memory cell, when forming the memory cell. | 06-17-2010 |
20100149896 | SENSE AMPLIFIER - A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder. | 06-17-2010 |
20100149897 | LOW CURRENT WIDE VREF RANGE INPUT BUFFER - A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages. | 06-17-2010 |
20100165770 | SEMICONDUCTOR MEMORY DEVICE - A memory includes memory cells, wherein during a first write operation in which first logical data is written in all memory cells connected to a first word line, a source line driver and a word line driver, the source line driver shifts a voltage of a selected source line corresponding to the first word line in a direction away from the voltage of the first word line and the word line driver shifts a voltage of a second word line in a same direction as a transition direction of voltage of a selected source line, and during a second write operation in which second logical data is written in a selected cell connected to the first word line, the source line driver and the word line driver shift voltages of the selected source line and the second word line in a direction approaching the voltage of the first word line. | 07-01-2010 |
20100165771 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, a memory cell array having a plurality of memory cell each provided at an intersection of the word line and the bit line, a plurality of sense amplifier each of which detects and amplifies a signal level of the bit line, a replica word line, a replica bit line intersecting the replica word line, a replica memory cell provided at each intersection of the replica word line and the replica bit line, a replica circuit which simulates reading out of the memory cell, and a timing generating circuit which quantizes a replica delay time that is a time until the replica bit line changes from a reference timing, and which generates an activation timing for the sense amplifier based on a quantization result. | 07-01-2010 |
20100172199 | BALANCED SENSE AMPLIFIER FOR SINGLE ENDED BITLINE MEMORY ARCHITECTURE - A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell. | 07-08-2010 |
20100177581 | Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme - The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects. | 07-15-2010 |
20100177582 | Semiconductor Memory Device - A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels. | 07-15-2010 |
20100188913 | SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair. | 07-29-2010 |
20100232243 | DIFFERENTIAL SENSE AMPLIFIER - The differential sense amplifier according to one aspect of the present invention includes a first differential amplification unit that detects a difference between the pair of complementary signals inputted from a first bit line and a second bit line, a second differential amplification unit that detects a difference between one of the complementary signals inputted from the first bit line and a first reference signal, and a third differential amplification unit that detects a difference between the other complementary signal inputted from the second bit line and a second reference signal. | 09-16-2010 |
20100246303 | SENSE AMPLIFIERS AND EXEMPLARY APPLICATIONS - Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed. | 09-30-2010 |
20100260002 | Circuit and Method for Small Swing Memory Signals - Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time. | 10-14-2010 |
20100265782 | HYBRID SENSE AMPLIFIER AND METHOD, AND MEMORY DEVICE USING SAME - Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The sensing circuit has first and second complementary output nodes and is coupled to the data lines. In a first mode, the sensing circuit can sense a difference between a voltage on the first digit line and a voltage on the second digit line to generate a first voltage differential between the first and second output nodes. In a second mode, the sensing circuit can sense a difference between a current flow in the first digit line and a current flow in the second digit line to generate a second voltage differential between the first and second output nodes. Other sense circuits, devices and methods are also provided. | 10-21-2010 |
20100271893 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE AND READ METHODS THEREOF - A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating body, the reference memory cell coupled to a reference word line, a second bit line, and a second source line, a first isolation gate portion configured to selectively transmit a signal between the first bit line and at least one of a sense bit line and an inverted sense bit line, a second isolation gate portion configured to selectively transmit a signal between the second bit line and at least one of the sense bit lines, and a sense amplifier configured to amplify voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels. | 10-28-2010 |
20100277996 | SEMICONDUCTOR DEVICE - A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers. | 11-04-2010 |
20100277997 | Semiconductor memory device - The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the memory device may include a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation, a first sense amplifier having a first transistor connected between to the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied. The semiconductor memory device may have a second transistor connected between the inverted bit line and a second node, the second transistor including a gate to which a signal of the bit line is applied, and the first sense amplifier configured to amplify a voltage of the bit line or the inverted bit line to a second voltage based on to the second voltage applied to one of the first node and the second nodes during the read operation. The semiconductor memory device may also have a bias unit configured to generate a voltage difference between the first node and the second node, and a sense amplifier driver configured to apply the second voltage to one of the first and second nodes based on one of the first and second selected word lines during the read operation. | 11-04-2010 |
20100277998 | MAINTENANCE OF AMPLIFIED SIGNALS USING HIGH-VOLATAGE-THRESHOLD TRANSISTORS - Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated. | 11-04-2010 |
20100329059 | APPARATUS AND METHODS FOR SENSE AMPLIFIERS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell; and a second circuit including a second circuit path coupled between the supply node and the line to charge the line during the memory operation. Additional embodiments are disclosed. | 12-30-2010 |
20110002184 | METHOD OF DETECTING A LIGHT ATTACK AGAINST A MEMORY DEVICE AND MEMORY DEVICE EMPLOYING A METHOD OF DETECTING A LIGHT ATTACK - A memory device having a plurality of memory cells employs a method to detect a light attack on the memory device. The method utilizes at least one memory cell to detect a light attack when the memory cell is in an inactive state, and outputs a signal indicating whether a light attack is detected. In one case, the method includes turning off all of the memory cells of memory blocks of the memory device that are not currently being accessed for a read/write operation; sensing a leakage current of at least one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation; and detecting a light attack on the memory device when a leakage current of the one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation is greater than a threshold. | 01-06-2011 |
20110026346 | SELF-TIMED LOW POWER SENSE AMPLIFIER - A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and having a gate terminal linked to the first sense input, and a second p-channel control transistor arranged to electrically power a second section of the latch and having a gate terminal linked to the second sense input. Application may be in particular to low power embedded memories. | 02-03-2011 |
20110026347 | Differential Sense Amplifier - A differential sense amplifier can perform data sensing using a very low supply voltage. | 02-03-2011 |
20110038220 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A sense amplifier includes a first inverter having an input terminal connected to a first line and an output terminal connected to a second line, and a second inverter having an input terminal connected to the second line and an output terminal connected to the first line, wherein an NMOS transistor of the first inverter and an NMOS transistor of the second inverter have well biases different from each other. | 02-17-2011 |
20110044121 | SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER - A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal. | 02-24-2011 |
20110058435 | SEMICONDUCTOR MEMORY DEVICE COMPRISING SENSE AMPLIFIERS CONFIGURED TO STABLY AMPLIFY DATA - A semiconductor memory device adjusts a timing interval between the activation of first and second amplifiers in a sense amplifier circuit based on the distance between the sense amplifier circuit and corresponding power supply. | 03-10-2011 |
20110058436 | TECHNIQUES FOR SENSING A SEMICONDUCTOR MEMORY DEVICE - Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor. | 03-10-2011 |
20110063934 | MEMORY CIRCUIT WITH MULTI-SIZED SENSE AMPLIFIER REDUNDANCY - A memory circuit with multi-sized sense amplifier redundancy is disclosed. In one aspect, the circuit includes sense amplifiers connected to differential bit-lines and configured to amplify a voltage difference sensed on the differential bit-lines. The sense amplifiers include a first set of smaller sense amplifiers and a second set of larger sense amplifiers redundantly arranged to the first set to form redundant groups which each contain one smaller sense amplifiers and one larger sense amplifiers. The larger sense amplifiers have a failure rate lower than the smaller sense amplifiers. The circuit also includes calibration circuitry connected to enable and disable nodes of each of the sense amplifiers and configured to select for each redundant group either the smaller sense amplifier of the first set or, if the smaller sense amplifier fails, the larger sense amplifier of the second set. | 03-17-2011 |
20110063935 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 03-17-2011 |
20110063936 | SEMICONDUCTOR DEVICE INCLUDING PLURAL ELECTRODE PADS - A semiconductor device includes a pad for sense amplifier ground potential as an electrode pad supplying ground potential voltage to a sense amplifier, a first conductive line connected to the pad for sense amplifier ground potential, and a second conductive line connected to an electrode pad closest to the pad for sense amplifier ground potential among plural electrode pads included in a pad row. The second conductive line extends to the opposite side of the first conductive line with the pad row as a reference. | 03-17-2011 |
20110069570 | MEMORY CIRCUITS AND METHOD FOR ACCESSING DATA OF THE MEMORY CIRCUITS - A memory circuit includes at least one first memory cell of a first memory array for storing a first datum. The at least one first memory cell is coupled with a first word line and a first bit line. A first bit line bar is disposed substantially parallel with the first bit line. A first switch is coupled between a sense amplifier and the first bit line bar. The first switch can electrically isolate the sense amplifier from the first bit line bar if the sense amplifier is capable of sensing a first voltage difference between the first bit line. The first bit line bar and the first voltage difference is substantially equal to or larger than a predetermined value. | 03-24-2011 |
20110096616 | SENSE AMPLIFIER CIRCUIT TO ENABLE SPEEDING-UP OF READOUT OF INFORMATION FROM MEMORY CELLS - A sense amplifier circuit, which is connected to a bit line and to an inverted bit line to which a voltage, inverted alternatively from a high level or a low level of a voltage applied to the bit line, is applied, includes a first resistance section reducing a voltage output from a memory cell through the inverted bit line, a second resistance section reducing a voltage output from a memory cell through the bit line, and an amplification section amplifying the first voltage reduced by the first resistance section and amplifying the second voltage reduced by the second resistance section. | 04-28-2011 |
20110103167 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation. | 05-05-2011 |
20110103168 | BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized. | 05-05-2011 |
20110128808 | CURRENT SENSE AMPLIFIER WITH FEEDBACK LOOP - A sensing circuit ( | 06-02-2011 |
20110158023 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time. | 06-30-2011 |
20110182129 | SENSE AMPLIFIER HAVING LOOP GAIN CONTROL - Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage. | 07-28-2011 |
20110182130 | LOW CURRENT WIDE VREF RANGE INPUT BUFFER - A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages. | 07-28-2011 |
20110199849 | SENSE AMPLIFIER FOR CONTROLLING FLIP ERROR AND DRIVING METHOD THEREOF - A sense amplifier and a driving method is described for resolving a flip failure occurrence where the voltage applied across the bit line is within an acceptable threshold range when the data is delivered to the data bus. The driving method includes disconnecting a bit line from a sense amplifying circuit according to a bit line select control signal after performing a read operation according to a read request. Then, connecting the sense amplifying circuit to a data bus according to a column select control signal after the bit line is disconnected from the sense amplifying circuit and deactivating an output terminal of the sense amplifier circuit that is disconnected from the bit line and connected to the data bus during a restore section synchronized to a command following the read command. Finally, delivering the data on the bit line to the output terminal of the sense amplifying circuit to update the output terminal of the sense amplifying circuit by connecting the sense amplifying circuit to the bit line according to the bit line select control signal. | 08-18-2011 |
20110205821 | Semiconductor device having sense amplifiers - A semiconductor device includes a plurality of memory cells connected to a word line, sense amplifiers arranged correspondingly to the memory cells, and a sense-amplifier control circuit that activates the sense amplifiers in response to selection of the word line and temporarily reduces driving performance of the sense amplifiers in response to a request for writing of data to any one of the memory cells. With this configuration, inverted data can be quickly overwritten to the sense amplifier. Furthermore, because a collective control is executed on the sense amplifiers to be activated, instead of individually controlling the sense amplifiers to be activated, the circuit scale of the sense-amplifier control circuit can be reduced. | 08-25-2011 |
20110205822 | BITLINE SENSE AMPLIFIER, MEMORY CORE INCLUDING THE SAME AND METHOD OF SENSING CHARGE FROM A MEMORY CELL - A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation. | 08-25-2011 |
20110211409 | Embedded Memory Databus Architecture - A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs | 09-01-2011 |
20110216616 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first and second memory cell array region, a first and second sense amplifier region interposed between the first and second memory cell array regions, a first column selection region interposed between the first sense amplifier region and the first memory cell array region and including a first column selection transistor connected between a first bit line and a first local data input/output (I/O) line, and a second column selection region interposed between the second sense amplifier region and the second memory cell array region and including a second column selection transistor connected between a second bit line and a second local data I/O line. A load of the second bit line is larger than a load of the first bit line and a threshold voltage of the first column selection transistor is higher than a threshold voltage of the second column selection transistor. | 09-08-2011 |
20110216617 | TECHNIQUES FOR SENSING A SEMICONDUCTOR MEMORY DEVICE - Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the plurality of memory cells. The data sense amplifier circuitry may comprise first amplifier circuitry and resistive circuitry, wherein the first amplifier circuitry and the resistive circuitry may form a feedback loop. | 09-08-2011 |
20110235449 | Dual Sensing Current Latched Sense Amplifier - A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state. | 09-29-2011 |
20110235450 | CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD - Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance. | 09-29-2011 |
20110235451 | DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF DRIVING DYNAMIC RANDOM ACCESS MEMORY - A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source. | 09-29-2011 |
20110242920 | VOLTAGE SENSING CIRCUIT CAPABLE OF CONTROLLING A PUMP VOLTAGE STABLY GENERATED IN A LOW VOLTAGE ENVIRONMENT - Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage. | 10-06-2011 |
20110255359 | Sense-Amplification With Offset Cancellation For Static Random Access Memories - An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers. | 10-20-2011 |
20110261637 | INCREASED DRAM-ARRAY THROUGHPUT USING INACTIVE BITLINES - A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost. | 10-27-2011 |
20110292750 | BIT LINE SENSE AMPLIFIER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal. | 12-01-2011 |
20110310687 | CURRENT SENSE AMPLIFIERS, MEMORY DEVICES AND METHODS - A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals. | 12-22-2011 |
20110310688 | CURRENT MODE DATA SENSING AND PROPAGATION USING VOLTAGE AMPLIFIER - A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method may include providing a current output signal from a voltage-to-current converter in response to the voltage-to-current converter receiving the output signal. The output signal may be used to drive a current sense amplifier. | 12-22-2011 |
20120020176 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain. | 01-26-2012 |
20120026818 | Split Bit Line Architecture Circuits and Methods for Memory Devices - Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved. | 02-02-2012 |
20120039143 | SENSE AMPLIFIER WITH ADJUSTABLE BACK BIAS - A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type transistors. Each transistor of the pair of the first type transistors is coupled in series with a transistor of the pair of the second type transistors. The first node has a first voltage and is coupled to each bulk of each transistor of the pair of the first type transistors. The second node has a second voltage and is coupled to each bulk of each transistor of the pair of the second type transistors. | 02-16-2012 |
20120039144 | Semiconductor device with shortened data read time - A semiconductor device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on selected bit lines, that amplify potentials in opposite phase to the potentials, and that output data signals and inverted data signals; a data output circuit that outputs the data to an external circuit based on the data signals and the inverted data signals; and a plurality of local signal lines extending parallel to the predetermined direction, to transmit the data signal and the inverted data signals to the data output circuit, wherein the local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to the predetermined direction alternately at predetermined intervals. | 02-16-2012 |
20120057422 | LOW POWER SENSE AMPLIFIER FOR READING MEMORY - A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current. | 03-08-2012 |
20120063251 | SEMICONDUCTOR DEVICE, METHOD OF ADJUSTING LOAD CAPACITANCE FOR THE SAME, AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals. | 03-15-2012 |
20120063252 | VARIABILITY RESILIENT SENSE AMPLIFIER WITH REDUCED ENERGY CONSUMPTION - An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors. | 03-15-2012 |
20120069692 | SEMICONDUCTOR DEVICE - A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing. | 03-22-2012 |
20120081985 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: odd and even sub word line driving units configured to selectively drive odd sub word lines and even sub word lines among a plurality of sub word lines; a bit line sense amplifier including a plurality of sense amplifier driving lines which are electrically connected with bit lines; a first sense amplifier driving unit formed on one side of the bit line sense amplifier which extends in the same direction as the bit lines, and configured to drive odd sense amplifier driving lines among the plurality of sense amplifier driving lines; and a second sense amplifier driving unit formed on another side of the bit line sense amplifier which extends in the same direction as the bit lines, and configured to drive even sense amplifier driving lines among the plurality of sense amplifier driving lines according to driving of the even sub word lines. | 04-05-2012 |
20120081986 | Semiconductor Devices, Operating Methods Thereof, And Memory Systems Including The Same - At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit configured to provide a power supply voltage to the first sense amplifier in response to a first control signal, a second power supply circuit configured to provide a ground voltage to the second sense amplifier in response to a second control signal, and a switching circuit configured to selectively connect the first power supply circuit with the second power supply circuit in response to a third control signal. | 04-05-2012 |
20120120751 | SEMICONDUCTOR DEVICE HAVING EQUALIZING CIRCUIT EQUALIZING PAIR OF BIT LINES - A semiconductor device includes: a sense amplifier including an equalizing circuit that equalizes a pair of bit lines; an equalizing control circuit that converts the amplitude of an equalizing signal into a VDD level, and a word driver that controls a sub word line based on a timing signal. The word driver includes a level shift circuit for changing the operation timing of the sub word line in accordance with the VDD level, allowing a timing to complete the equalizing operation and a timing to reset the sub word line to synchronize even when the level of the VDD level is changed. | 05-17-2012 |
20120134226 | SENSE AMPLIFIER AND SENSE AMPLIFIER LATCH HAVING COMMON CONTROL - A sense amplifier of a memory array may be provided to amplify data presented from storage cells of the memory array. Additionally, a sense amplifier latch may be provided to store data received from the sense amplifier. The sense amplifier may be enabled for operation by a sense amplifier enable signal that is distinct from a clock signal. Moreover, the latch enable signal of the sense amplifier latch may be controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier. | 05-31-2012 |
20120213026 | MEMORY DEVICE AND METHOD FOR SENSING A CONTENT OF A MEMORY CELL - A memory device and a method for sensing a content of a memory cell. The memory device includes: a pair of bit-lines; a memory cell coupled between the pair of bit-lines; a sensing circuit having at least two inputs for receiving respective currents from a current conveyor, said sensing circuit being arranged to sense, when operating in a sensing mode, a difference between said output currents, said difference between the output currents representing a content of the memory cell; and said sensing circuit comprising an output for outputting an output signal that represents the content of the memory cell; and a current conveyor, coupled to the pair of bit-lines and to the sensing circuit, for: isolating the sensing circuit from the bit-lines, when the current conveyor operated in an isolation mode; said current conveyor having at least two outputs for providing, to the sensing circuit when the sensing circuit operated in the sensing mode, output currents representing bit-lines currents; and equalizing the output currents before the current conveyor starts to operate in a current conveying mode. The sensing circuit enters the sensing mode after the current conveyor exits the current conveying mode. | 08-23-2012 |
20120218847 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 08-30-2012 |
20120224443 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first and the second transistor. The shielding circuit is located between the second transistor and the output circuit. | 09-06-2012 |
20120230141 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines. | 09-13-2012 |
20120236669 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITANCE - Disclosed herein is a device that includes: first and second memory mats each including a plurality of bit lines; a sense area arranged between the first and second memory mats; a column selection line provided on the first memory mat; and a compensation capacitance provided on the second memory mat. The sense area includes a plurality of sense amplifiers. Each of the sense amplifiers is connected to an associated one or ones of the bit lines. At least one of the sense amplifiers is selected based on a column selection signal supplied via the column selection line. At least a part of the compensation capacitance is formed in a same wiring layer as the column selection line. | 09-20-2012 |
20120243359 | SENSE AMPLIFIER - A circuit comprises a first node, a second node, a sense amplifier, at least one first transistor, at least one second transistor, and one or a combination of a first control circuit and a second control circuit. The first control circuit is configured to generate a first control signal for at least one first gate of the at least one first transistor. The first control signal is capable of having a first voltage level lower than a first operational voltage. The second control circuit is configured to generate a second control signal for at least one second gate of the at least one second transistor. The second control signal is capable of having a second voltage level higher than a second operational voltage. | 09-27-2012 |
20120243360 | SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED WITH A LOCAL COLUMN DECODER - A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines. | 09-27-2012 |
20120275256 | SEMICONDUCTOR DEVICE - A device may include, but is not limited to, a bit line; a power line supplied with a power voltage; a sense amplifier circuit amplifying a voltage of the bit line by using the power voltage of the power line; and a control circuit configured to respond to an active command and supply, as the power voltage, the power line with a first voltage during a first period and a second voltage lower than the first voltage during a second period. The control circuit is further configured to respond to a refresh command and supply, as the power voltage, the power line with the second voltage during both the first and second periods. | 11-01-2012 |
20120300567 | Sense Amplifier Apparatus and Methods - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed. | 11-29-2012 |
20130003478 | Embedded Memory Databus Architecture - A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors. | 01-03-2013 |
20130010560 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node. | 01-10-2013 |
20130010561 | SENSE AMPLIFIERS AND EXEMPLARY APPLICATIONS - Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed. | 01-10-2013 |
20130107651 | SEMICONDUCTOR DEVICE WITH REDUCED LEAKAGE CURRENT AND METHOD FOR MANUFACTURE THE SAME | 05-02-2013 |
20130107652 | SEMICONDUCTOR MEMORY DEVICE | 05-02-2013 |
20130114362 | DATA TRANSMISSION CIRCUIT - A data transmission circuit includes an enable signal generation unit configured to receive a first enable signal and generate a second enable signal having a pulse width controlled according to a swing width of data inputted through a first data line, and a sense amplification unit configured to sense and amplify the data inputted through the first data line in response to the second enable signal, and transmit the amplified data to a second data line. | 05-09-2013 |
20130114363 | MULTI-MODAL MEMORY INTERFACE - A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques. | 05-09-2013 |
20130121099 | AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - An amplifier circuit includes an amplification unit and a back-bias voltage providing unit. The amplification unit amplifies input data. The back-bias voltage providing unit provides selectively back-bias voltages of different levels to the amplification unit in an initial operation period of the amplification unit and a period after the initial operation period. | 05-16-2013 |
20130128681 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first switch, a second switch and a control unit. The first switch couples/separates a first bit line and a sense amplifier to/from each other in response to a first bit line separation signal. The second switch couples a second bit line and the sense amplifier to each other in response to a second bit line separation signal. The control unit generates a bit line separation signal for a refresh operation, of which enable period is shorter than that of the second bit line separation signal, and provides the generated bit line separation signal for the refresh operation to the second switch in the refresh operation. | 05-23-2013 |
20130170309 | SENSE-AMPLIFIER CIRCUIT OF MEMORY AND CALIBRATING METHOD THEREOF - A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided. | 07-04-2013 |
20130188435 | MEMORY HAVING ISOLATION UNITS FOR ISOLATING STORAGE ARRAYS FROM A SHARED I/O DURING RETENTION MODE OPERATION - A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths. | 07-25-2013 |
20130258795 | SINGLE-ENDED READ RANDOM ACCESS MEMORY - A single-ended read random access memory including a plurality of memory units, a clock generator, a bit line load circuit, a control processing unit, and a sensing unit is revealed. The memory units are coupled to a bit line and the clock generator is for generating a clock signal. The bit line load circuit charges the memory units to an operating voltage according to the clock signal. The control processing unit controls at least one of the memory units according to the clock signal to make the memory unit store a stored voltage according to the operating voltage. The sensing unit generates a sensing threshold according to the clock signal and a data dependency, and outputs a data signal according to the sensing threshold and the stored voltage. The operating voltage includes a noise whose ratio to the operating voltage is inversely proportional to the operating voltage. | 10-03-2013 |
20130279282 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line, a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor, a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line, and a second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor. | 10-24-2013 |
20130308404 | CIRCUIT FOR SENSING MULTI-LEVEL CELL - A circuit for sensing a multi-level cell (MLC) comprises a first switch associated with a first read bit, a second switch associated with a second read bit, a first switch control unit to control the first switch in response to a first data bit from a counter, and a second switch control unit to control the second switch in response to a second data bit from the counter. | 11-21-2013 |
20130322196 | MEMORY DEVICE AND SIGNAL DRIVING DEVICE THEREOF - A signal driving device includes a constant current circuit configured to provide a constant current, a first mirror circuit configured to generate a mirror current from the constant current and provide a voltage according to the mirror current of the constant current, a circuit comprising a switch device and configured to provide a driver current, a second mirror circuit configured to generate a mirror current of the driver current and output a voltage that includes a voltage drop caused when the mirror current of the driver current flows through a replica switch device, and a differential amplifier configured to receive the voltage from the first mirror circuit and the voltage from the second mirror circuit to provide a biased voltage for the bias circuit and thereby induce the driver current. | 12-05-2013 |
20130343140 | Bitline for Memory - Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline. | 12-26-2013 |
20140003177 | Memory Device, System Having the Same, and Method for Manufacturing the Same | 01-02-2014 |
20140016420 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier circuit region including first wells disposed in a first direction, a driving circuit region including second wells disposed in a second direction, and a conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region. | 01-16-2014 |
20140056090 | TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment. | 02-27-2014 |
20140064005 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify the voltages of the bit line pair based on the sensed potential difference, a bit line main sense amplifier configured to sense a potential difference between the bit line pair and amplify the voltages of the bit line pair to first and second driving voltages based on the sensed potential difference, and a power supplying controller configured to supply the second driving voltage to the bit line pre-sense amplifier and the bit line main sense amplifier. | 03-06-2014 |
20140064006 | JUNCTIONLESS SEMICONDUCTOR DEVICE HAVING BURIED GATE, APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current. | 03-06-2014 |
20140126315 | CIRCUIT AND METHOD FOR IMPROVING SENSE AMPLIFIER REACTION TIME IN MEMORY READ OPERATIONS - A sense amplifier circuit, a method of modifying a differential voltage in a sense amplifier circuit and a memory system incorporating the sense amplifier circuit or the method. In one embodiment, the sense amplifier circuit includes: (1) a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read and (2) a sense speed alteration circuit having first and second outputs respectively coupled to the first and second inputs via respective first and second capacitors and configured to cause one of the first and second capacitors to discharge to increase the differential voltage when a previously read logic value is opposite the current logic value to be read. | 05-08-2014 |
20140126316 | CIRCUIT AND METHOD FOR DYNAMICALLY CHANGING A TRIP POINT IN A SENSING INVERTER - A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage. | 05-08-2014 |
20140126317 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage, a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage, a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated, a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated, an e-fuse device supplied with voltage of the program/read line, a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line, and a column circuit configured to supply the negative voltage to the column line when the column line is activated. | 05-08-2014 |
20140177368 | NONVOLATILE MEMORY APPARATUS - A nonvolatile memory apparatus includes a memory cell configured to receive a first current and a second current through a bit line which is connected to a sensing node; a sensing node level control unit configured to be driven in response to a control signal, compare a reference voltage and a voltage of the sensing node, and output a driving signal to a driving node; a first current driving unit configured to output the first current to the driving node by using a first driving voltage in response to the driving signal; and a current control unit configured to perform a discharge operation of the bit line or electrically connect the driving node and the sensing node, in response to the control signal. | 06-26-2014 |
20140185400 | APPARATUS AND METHOD FOR SENSE AMPLIFYING - A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted V | 07-03-2014 |
20140185401 | SENSING CIRCUIT, MEMORY DEVICE AND DATA DETECTING METHOD - A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage. | 07-03-2014 |
20140185402 | DRAM SECURITY ERASE - A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range. | 07-03-2014 |
20140241090 | SMART READ SCHEME FOR MEMORY ARRAY SENSING - Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation. | 08-28-2014 |
20140241091 | SENSE AMPLIFIER VOLTAGE REGULATOR - A memory is disclosed that includes a plurality of memory cells, a plurality of sense amplifiers for reading data of the memory cells, and a voltage regulator coupled to the plurality of sense amplifiers. The voltage regulator includes a reference sense amplifier, a current injector, and a current injector control circuit. The current injector control circuit controls an amount of current provided by the current injector to an output node of the voltage regulator based on a voltage of the reference sense amplifier. | 08-28-2014 |
20140269130 | MEMORY RECEIVER CIRCUIT FOR USE WITH MEMORY OF DIFFERENT CHARACTERISTICS - Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed. | 09-18-2014 |
20140301151 | DISTRIBUTED SUB-PAGE SELECTION - Described are dynamic, random-access memories (DRAM) architectures and methods for subdividing memory activation into fractions of a page. Circuitry in support of sub-page activation is placed in the intersections of local wordline drivers and sense-amplifier stripes to allow independent control of adjacent arrays of memory cells without significant area overhead. | 10-09-2014 |
20140307516 | BIAS SENSING IN DRAM SENSE AMPLIFIERS THROUGH VOLTAGE-COUPLING/DECOUPLING DEVICE - Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased. | 10-16-2014 |
20150049565 | APPARATUSES AND METHODS FOR REDUCING CURRENT LEAKAGE IN A MEMORY - Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell. | 02-19-2015 |
20150055426 | NOVEL SENSE AMPLIFIER SCHEME - A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter. The first inverter has a first pull-up transistor with a first pull-up terminal. The second inverter has a second pull-up transistor with a second pull-up terminal. The output of the first inverter is coupled to the input of the second inverter at a first sense amp node. The output of the second inverter is coupled to the input of the first inverter at a second sense amp node. The data line charging circuit has a first node connected to a data line and the first pull-up terminal. The data line charging circuit also has a second node connected to a complementary data line and the second pull-up terminal. The first and second pull-up transistors are coupled to different voltage levels when a sense amplifier enable signal is activated. | 02-26-2015 |
20160055887 | MEMORY CIRCUITS AND METHOD FOR ACCESSING DATA OF THE MEMORY CIRCUITS - A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion. | 02-25-2016 |
20160071572 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively. | 03-10-2016 |
20160078919 | SEMICONDUCTOR MEMORY DEVICE COMPENSATING DIFFERENCE OF BITLINE INTERCONNECTION RESISTANCE - A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance. | 03-17-2016 |
20220139429 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SENSE AMPLIFIER - A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor. The local sense amplifier includes an active region, a plurality of gate patterns at least partially extending in the first direction and disposed on the active region, a first contact disposed between the plurality of gate patterns and including a long side extending in the first direction and a short side extending in a second direction crossing the first direction and a first conductive line electrically connected to the first contact while overlapping the first contact in a plan view and including a first conductive region extending in the first direction. | 05-05-2022 |