Class / Patent application number | Description | Number of patent applications / Date published |
365230020 | Multiplexing | 28 |
20080239860 | Apparatus and Method for Providing Multiple Reads/Writes Using a 2Read/2Write Register File Array - An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays. | 10-02-2008 |
20080304351 | Pin Multiplexing - A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core. | 12-11-2008 |
20080304352 | MEMORY CONTROLLERS AND PAD SEQUENCE CONTROL METHODS THEREOF - Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported. | 12-11-2008 |
20090027992 | PSRAM AND METHOD FOR OPERATING THEREOF - Disclosed is a pseudo static random access memory (PSRAM) and a method for operating the same. The PSRAM includes a multi-bit control register and a multiplexer circuit operatively coupled to the multi-bit control register. The multi-bit control register has a first set of bits reserved for a page control mode of the PSRAM and a second set of bits reserved for a bus control mode of the PSRAM. The multiplexer circuit activates one of the page control mode and the bus control mode of the PSRAM based on a logic level of an address bit inputted to the multiplexer circuit. | 01-29-2009 |
20090034356 | Dual-Port Memory - A dual-port memory circuit includes a plurality of memory sub-blocks. Each of the memory sub-blocks includes a plurality of single-port memory cells, at least one row line, and at least one local bit line, the row line and the bit line being coupled to the memory cells for selectively accessing the memory cells. The memory circuit further includes at least one global bit line connected to the plurality of memory sub-blocks. The global bit line is time-multiplexed during a given memory cycle such that the global bit line propagates data associated with a first port in the memory circuit during a first portion of the memory cycle, and the global bit line propagates data associated with a second port in the memory circuit during a second portion of the memory cycle. | 02-05-2009 |
20090052268 | SYSTEM AND METHOD FOR PROVIDING TEMPERATURE DATA FROM A MEMORY DEVICE HAVING A TEMPERATURE SENSOR - A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path. | 02-26-2009 |
20090059707 | POWER SAVING SENSING SCHEME FOR SOLID STATE MEMORY - Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device. | 03-05-2009 |
20090103387 | HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS - The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications. | 04-23-2009 |
20090175114 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 07-09-2009 |
20090268543 | MEMORY CONTROL CIRCUIT AND MEMORY ACCESSING METHOD - A control circuit applied in a memory that comprises a first memory block and a second memory block, and each of the first and the second memory blocks includes a boundary cell. The control circuit comprises an address decoder, a first Y-multiplexer, and a second Y-multiplexer. The address decoder provides a plurality of column selection signals capable of being a boundary value. The first Y-multiplexer corresponds to the first memory block and provides a first boundary data channel for a boundary cell of the first memory block. The second Y-multiplexer corresponds to the second memory block and provides a second boundary data channel for a boundary cell of the second memory block. The first and the second boundary data channels are enabled simultaneously in response to the boundary value for outputting boundary data stored in the boundary cell of the first memory block and that of the second memory block. | 10-29-2009 |
20100091598 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data. | 04-15-2010 |
20100103761 | MEMORY DEVICES HAVING REDUNDANT ARRAYS FOR REPAIR - Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data transmission. The memory device also includes one or more multiplexers/demultiplexers, wherein each of the multiplexers/demultiplexers is electrically coupled to one or more, but not all, of the global I/O lines. The memory device further includes a plurality of local I/O lines, each configured to provide a data path between one of the multiplexers/demultiplexers and one or more, but less than the first number, of the columns in the sub-array. This configuration allows local I/O line repairability with fewer redundant elements, and shorter physical local I/O lines, which translate to improved speed and die size reduction. | 04-29-2010 |
20110085401 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode. | 04-14-2011 |
20120113739 | MEMORY DEVICES HAVING REDUNDANT ARRAYS FOR REPAIR - Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data transmission. The memory device also includes one or more multiplexers/demultiplexers, wherein each of the multiplexers/demultiplexers is electrically coupled to one or more, but not all, of the global I/O lines. The memory device further includes a plurality of local I/O lines, each configured to provide a data path between one of the multiplexers/demultiplexers and one or more, but less than the first number, of the columns in the sub-array. This configuration allows local I/O line repairability with fewer redundant elements, and shorter physical local I/O lines, which translate to improved speed and die size reduction. | 05-10-2012 |
20120134229 | CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE - An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit ceils and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines. | 05-31-2012 |
20130003483 | WIDE FREQUENCY RANGE DELAY LOCKED LOOP - A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power. | 01-03-2013 |
20130083617 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a plurality of address input blocks configured to respectively receive a plurality of addresses that are related to burst ordering and a control circuit configured to selectively disable all or a part of the address input blocks in response to a burst length information during a write operation mode. | 04-04-2013 |
20130100757 | Dual-Port Memory and a Method Thereof - A dual-port memory is provided. The dual-port memory includes a first single-port memory and a second single-port memory. The first single-port memory is configured to store data in an even address of the dual-port memory. The second single-port memory is configured to store data in an odd address of the dual-port memory. The dual-port memory simultaneously performs a read operation to read data from the odd address and a write operation to write data into the even address. The dual-port memory simultaneously performs a read operation to read data from the even address and a write operation to write data into the odd address. | 04-25-2013 |
20130107655 | Lookahead Scheme for Prioritized Reads | 05-02-2013 |
20130163364 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a first semiconductor chip including a first pad group configured to input/output first data and a second pad group configured to input/output second data; and a second semiconductor chip in a stack with the first semiconductor chip and configured to be electrically connected to the first semiconductor chip by at least one chip through via, wherein the second semiconductor chip includes a first unit bank group including at least one first upper bank group and at least one first lower bank group, a second unit bank group including at least one second upper bank group and at least one second lower bank group, and a data path selector configured to electrically connect one among the first and second upper bank groups and the first and second lower bank groups with the chip through via. | 06-27-2013 |
20130242684 | SEMICONDUCTOR STORAGE DEVICE AND DRIVING METHOD THEREOF - A semiconductor storage device according to the present embodiment includes local word lines and bit lines intersecting the local word lines. Each memory segment includes nonvolatile memory cells. Each memory segment corresponds to a plurality of the local word lines. A sense amplifier corresponds to a plurality of the bit lines. A global word line corresponds to a plurality of the local word lines, and is commonly driven in the memory segments. A decoder is connected between the global word line and the local word lines corresponding to the global word line, and selectively drives a certain local word line from the local word lines. A segment controller is provided in each memory segment, and selects one of the memory segments to be driven. An input/output part outputs read data from the memory segments or receives write data to the memory segments. | 09-19-2013 |
20140003182 | APPARATUS AND METHOD FOR SELECTIVELY USING A MEMORY COMMAND CLOCK AS A REFERENCE CLOCK | 01-02-2014 |
20140119148 | MULTI-PORT MEMORY CIRCUIT, ACCESSING METHOD AND COMPILER - A memory circuit includes first and second word lines, a plurality of memory cells and a timing controller. Each memory cell includes a first access port and a second access port. The first access port is coupled to the first word line and configured to be enabled by a first word line signal on the first word line. The second access port is coupled to the second word line and configured to be enabled by a second word line signal on the second word line. The timing controller is configured to receive a timing select signal and to control a time delay between the first word line signal and the second word line signal to be different in response to different first and second states of the timing select signal. | 05-01-2014 |
20140313845 | SEMICONDUCTOR CHIP, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SEMICONDUCTOR CHIP, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DRIVING THE SEMICONDUCTOR SYSTEM - A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails. | 10-23-2014 |
20150036448 | OUTPUT CIRCUIT FOR IMPLEMENTING HIGH SPEED DATA TRANSMITION - An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal. | 02-05-2015 |
20150348605 | NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE HAVING THE SAME - A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time. | 12-03-2015 |
20150371693 | CODEC TO REDUCE SIMULTANEOUSLY SWITCHING OUTPUTS - Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions. | 12-24-2015 |
20160064055 | EVENT CONTROLLED DECODING CIRCUIT - A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits. | 03-03-2016 |