Class / Patent application number | Description | Number of patent applications / Date published |
375342000 | Locating predetermined portion of pulse | 19 |
20080298514 | Method And Apparatus For Real-Time Pulse Parameter Estimator - A real-time pulse parameter estimator is disclosed herein. In one embodiment, an apparatus has pulse detection logic, an abnormal pulse filter, and a pulse parameter estimator. The pulse detection logic is operable to detect pulses and to record an arrival time of each detected pulse. The abnormal pulse filter is operable to analyze the arrival time of the detected pulses and to determine whether there are any abnormal pulses based on the analysis. In one embodiment, the abnormal pulse filter generates an adjusted time difference of arrival (TDOA) signal for a pulse, based on a determination that the pulse is abnormal. The pulse parameter estimator is operable to estimate a pulse parameter for the signal based on an analysis of the arrival times of the detected pulses and information pertaining to there being any abnormal pulses in the signal. | 12-04-2008 |
20100027722 | WIRED SIGNAL RECEIVING APPARATUS - A wired signal receiving apparatus including a signal receiver, a signal peak detector, and a signal comparator is disclosed. The signal receiver includes an operation current detecting circuit for detecting an operation current. The signal receiver further receives a transmission signal. The signal peak detector receives the operation current, detects a peak thereof, and generates a peak current. The signal comparator compares a reference signal and the peak current to generate an output current for regulating the operation current. | 02-04-2010 |
20100239053 | Apparatus and Method for Tracking Symbol Timing of OFDM Modulation in a Multi-Path Channel - Methods and Systems for tracking symbol timing of an OFDM signal are disclosed. In one embodiment, a wireless receiver includes signal tracking and timing logic to facilitate the timing of a demodulation operation such that the demodulation operation occurs on the proper symbol boundary, particularly when the OFDM signal has multipath components and the second component has greater power than the first. | 09-23-2010 |
20110274220 | Reduced Complexity Timing Estimation for Locating the Position of a Mobile Terminal - A method and corresponding apparatus are provided to reduce the complexity of calculations needed to determine the time of arrival of position reference signals transmitted from multiple cells. A scheduler determines at a given instance what portions of a search grid or search window to search. A timing estimation circuit operating under the control of the scheduler computes timing estimates and reports the timing estimates back to the scheduler. The scheduler uses the timing estimates reported by the detection circuit to scheduler subsequent searches of the search grid or search window. | 11-10-2011 |
20120140857 | METHOD FOR SYNCHRONIZING A RECEIVER WITH A RECEIVED AMBIGUOUS SIGNAL HAVING A KNOWN NUMBER OF AT LEAST TWO PEAKS - Method and receiver synchronizing receiver with received ambiguous signal having at least two peaks. Method includes providing information about known transmitted signal having a number of at least two peaks, the information including number of peaks and distances between at least two peaks, determining ratios between peaks of known transmitted signal and assigning determined ratio value to each peak, and deducing theoretical auto-correlation function from known transmitted signal. Auto-correlation function has number of correlations corresponding to number of peaks in known transmitted signal and correlators of the auto-correlation function are provided in same distance and have the same relative ratio as peaks in known transmitted signal. Further includes tracking received signal with auto-correlation function so that correlator pattern of auto-correlation function is aligned with peak pattern of received signal by assigning each peak of the received signal to a correlator of the auto-correlation function, and identifying each peak. | 06-07-2012 |
20120170693 | COMMUNICATION RECEIVER AND A RECEIVING METHOD - A communication receiver and a receiving method are disclosed. An analog front-end device samples a receiving signal and generates a sampled signal. A signal detector detects presence of the receiving signal according to the sampled signal. A symbol timing recovery (STR) unit determines an optimal symbol sampling point according to a zero-crossing point of the sampled signal when the receiving signal is present, and then generates a recovered symbol based on an optimally chosen sampled value according to the optimal symbol sampling point. | 07-05-2012 |
20120207252 | FREQUENCY CORRECTION OF A PROGRAMMABLE FREQUENCY OSCILLATOR BY PROPAGATION DELAY COMPENSATION - A first programmable frequency oscillator, which includes a first ramp comparator and programmable signal generation circuitry is disclosed. The programmable signal generation circuitry provides a ramping signal, which has a first frequency, based on a desired first frequency. The first ramp comparator receives the ramping signal and provides a first ramp comparator output signal based on the ramping signal. The first ramp comparator output signal is fed back to the programmable signal generation circuitry, such that the ramping signal is based on the desired first frequency and the first ramp comparator output signal. However, the first ramp comparator has a first propagation delay, which introduces a frequency error into the programmable frequency oscillator. Therefore, the first frequency is not proportional to one or more slopes of the ramping signal. As a result, the programmable signal generation circuitry compensates for the frequency error based on the desired first frequency. | 08-16-2012 |
20120236973 | SYSTEM AND METHOD FOR SYNCHRONIZING DIGITAL BITS IN A DATA STREAM - A system for synchronizing a receiver of a bit stream to the bit stream include a correlator to remove the PN code modulation and to generate a stream of time sequence values (samples) from the received bits. Multiple accumulators are included, each accumulator corresponding to a different offset from a first time period. The accumulators add a number of values equal to a number of samples in a bit period. Multiple magnitude calculators receive sums from the corresponding accumulators and calculates respective magnitudes. Multiple non-coherent summers are then used to add the magnitudes for each offset in each bit period for all of the received bits. The outputs of the non-coherent summers are analyzed to find the highest value, to identify the location of the bit transition in the bit period. | 09-20-2012 |
20120269304 | Symbol Clock Recovery Circuit - A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit. | 10-25-2012 |
20120275549 | Systems and Methods for Wirelessly Receiving Data - In accordance with some embodiments, receivers for receiving a wireless data transmission are provided, the receivers comprising at least one amplifier that receives an RF input signal and produces at least one amplified signal; a mixer that mixes the at least one signal to produce a mixed signal; a filter that filters the mixed signal to produce a filtered signal, a comparator that compares the filtered signal to a threshold voltage and produces a digital signal, a first pulse generate i that generates a first pulse in response to a transition in the digital signal, a second pulse generator that generates a second pulse that is longer than the first pulse in response to a transition in the digital signal; and digital logic that generates a clock output and that generates a data output based on a state of the first pulse when the second pulse expires. | 11-01-2012 |
20130039449 | UNIVERSAL SYSTEMS AND METHODS FOR DETERMINING AN INCOMING CARRIER FREQUENCY AND DECODING AN INCOMING SIGNAL - Consumer infrared (CIR) systems typically are used in remote control systems. Most CIR systems expect a known carrier frequency and encoding scheme. However, there are many applications of a universal CIR receiver which can receive and decode CIR signals regardless of the carrier frequency or encoding scheme. A CIR receiver circuit is disclosed which can both decompose a received CIR signal into run length representation and detect the carrier frequency. The result can then be supplied to a host device for further processing, interpretation and/or actions. | 02-14-2013 |
20130259171 | METHOD FOR SPECTRUM SENSING OF MULTI-CARRIER SIGNALS WITH EQUIDISTANT SUB-CARRIERS - A multi carrier signal is typically comprised of many equidistant sub-carriers. This results in periodicity of spectrum within the bandwidth of such a multi-carrier signal. An unknown multi-carrier signal with equidistant sub-carriers can thus be sensed together with its sub-carrier spacing by finding a discernable local maximum in the cepstrum (Fourier transform of the log spectrum) of the multi-carrier signal. | 10-03-2013 |
20140119479 | RECEIVER SYSTEM - The present invention concerns a receiver circuit including an input terminal through which an input signal is received, said receiver circuit further including:
| 05-01-2014 |
20140169507 | MANCHESTER CODE RECEIVING CIRCUIT - A Manchester code receiving circuit includes an analog circuit configured to convert an analog signal received through a communication transmission path, to a digital signal based on a Manchester code, and a characteristic compensating unit configured to compensate at least one of rise delay characteristics in which a rising time of the digital signal is longer than a falling time, and fall delay characteristics in which the falling time of the digital signal is longer than the rising time. | 06-19-2014 |
20140198883 | Systems and Methods for Highly Accurate and Efficient Pulse Prediction - A method is disclosed for predicting a pulse periodicity in a signal. The method includes the steps of receiving a signal that includes a component that is periodic having an unknown periodicity and a noise component; comparing the signal to an adjustable reference signal, and varying at least one of the phase and the periodicity of the reference signal until a best fit match is obtained between the signal and the reference signal. | 07-17-2014 |
20140254729 | Detecting Digital Radio Signals - In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence. | 09-11-2014 |
20140355724 | RECEIVING APPARATUS AND METHOD FOR DETECTING THE NUMBER OF BITS OF THE SAME VALUE IN A RECEIVED BIT STREAM - An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval. | 12-04-2014 |
20150016574 | Word Boundary Lock - In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND operation on a current state of the bit position of the register and a result of the XOR operation, and storing a result of the AND operation to update the state of the bit position of the register. The word boundary is defined based on the content of the register following the processing of the number of consecutive N bit words. | 01-15-2015 |
20150023454 | MULTI-PHASE CLOCK GENERATION METHOD - Systems and methods for multi-phase signaling are described herein. In one embodiment, a method for receiving data comprises receiving a sequence of symbols from a plurality of conductors, and generating a clock signal by detecting transitions in the received sequence of symbols. The method also comprises delaying the received sequence of symbols, and capturing one or more symbols in the delayed sequence of symbols using the clock signal, wherein a previous symbol in the delayed sequence of symbols is captured using a clock pulse in the clock signal generated based on a detected transition to a current symbol in the received sequence of symbols. | 01-22-2015 |