Entries |
Document | Title | Date |
20080205565 | Receiver With Adaptive Strobe Offset Adjustment - Receiver for receiving a data stream via a data bus, which receiver samples the bits of the data stream in an over-sampling process, in which n bit strobe offsets are used and n data sets with i bits are sampled,—applies a decision criterion for identifying those data sets with correct bit values. This decision uses checksum CRC,—selects one of the identified data sets with correct bit values and—uses the bit strobe offset, which was used for receiving the selected data streams, for receiving the data stream. In this way the multiphase clock with optimal phase shifts is selected. | 08-28-2008 |
20080205566 | CLOSED LOOP SUB-CARRIER SYNCHRONIZATION SYSTEM - A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received subcarrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference. | 08-28-2008 |
20080219390 | Receiver Circuit - A thermometer code to sign and magnitude converter that is particularly useful in a flash ADC is provided. This comprises two conversion units. The first is a thermometer code to Gray code converter and the second a Gray code to sign and magnitude converter. Preferably, the Gray code is of a kind that has a sign bit and has the other bits symmetrically disposed about zero. This form is easily converted to a sign and magnitude code, which is advantageous as it reduces the latency of the converter, which is particularly useful at high data rates. | 09-11-2008 |
20080232522 | Method and System for Integration of Bluetooth and FM Local Oscillator Generation into a Single Unit Using a DDFS - Certain aspects of a method and system for integration of Bluetooth and FM local oscillator generation in a single unit using a direct digital frequency synthesizer (DDFS) may be disclosed. Aspects of the method may include generating a clock signal at a particular frequency in a chip that handles communication of Bluetooth signals and FM signals. The generated clock signal may be divided to produce a frequency divided clock signal, which may be mixed with the generated clock signal to enable transmission and/or reception of Bluetooth signals. The generated clock signal or the frequency divided clock signal may be selected for clocking one or more direct digital frequency synthesizers (DDFSs) to enable transmission and/or reception of the FM signals. | 09-25-2008 |
20080232523 | Method And System For Mixing A Plurality Of Audio Sources In An FM Transmitter - A plurality of digital audio signals from a plurality of sources utilizing different clocks may be processed and transmitted via an FM transmitter. The plurality of signals may have different sample rates which are converted to one same sample rate by a plurality of rate adapters. The plurality of rate adapters may be clocked at one same sample rate. The energy levels of the signals may be adjusted relative to one another and as a group. Energy level adjustments may improve FM modulation signal characteristics and audible energy levels for an end listener. The plurality of digital audio signals may be combined into one composite signal and FM modulated in the digital domain. The FM modulated signal may be converted to analog signal prior to being filtered, amplified and coupled to an antenna for transmission. | 09-25-2008 |
20080232524 | JITTER-TOLERANCE-ENHANCED CDR USING A GDCO-BASED PHASE DETECTOR - An embodiment of a clock and data recovery circuit comprising a first clock and data recovery circuit with high bandwidth and a second clock and data recovery circuit with low bandwidth is disclosed. The first clock and data recovery circuit with high bandwidth receives a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein a second data rate X bps of the first signal and the second signal is half of a first data rate of the data signal. The second clock and data recovery circuit with low bandwidth receives and reduces jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal. | 09-25-2008 |
20080240318 | Recovering precoded data using a Mueller-Muller recovery mechanism - In one embodiment, the present invention includes an apparatus having a digital signal processor (DSP) coupled to receive a digitized signal. The DSP may be controlled to perform a timing recovery mechanism that implements a Mueller and Müller (MM)-based algorithm to generate a sensor output responsive to the digitized signal, where the incoming signal is non-linearly precoded in a transmitter from which the signal is received. Other embodiments are described and claimed. | 10-02-2008 |
20080240319 | Measuring a horizontal eye opening during system operation - In one embodiment, the present invention includes a method for receiving an incoming signal from a communication channel at a receiver, sampling the incoming signal in first and second samplers that are independently clocked, comparing outputs of the samplers, and outputting a measure of a horizontal eye opening of the incoming signal based on the comparison. Other embodiments are described and claimed. | 10-02-2008 |
20080240320 | TRANSMIT CLOCK GENERATOR - A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a clock training period to enforce a phase relationship between the first and second divided clock signals. The synchronization signal includes at least one synchronization pulse that is applied to the first local clock generator and second local clock generator during the clock training period. | 10-02-2008 |
20080260083 | SIGNAL PROCESSING CIRCUIT - A signal processing circuit detects a pulsative change point of an input signal and sets a phase point which is shifted by a predetermined phase difference from the detected pulsative change point of the input signal as the timing for sampling the input signal. | 10-23-2008 |
20080267329 | Synchronous Digital Data Transmission Interface - The field of the invention is that of transmission interfaces for synchronous digital input signals composed of bits transmitted in series at a frequency of transmission equal to a first integer multiple M of a first clock frequency. The interface according to the invention comprises at least one deserializer operating in over-sampling mode and supplying digital output samples of each bit in parallel. The output samples are transmitted at a second clock frequency, integer multiple N of a third frequency. The third frequency is substantially equal to the first frequency. Each sampled bit is substantially composed of N samples. The interface has an electronic device for frequency-locking the third frequency onto the first clock frequency. The device has means for counting the number of samples composing each sampled bit. The device also has incrementation-decrementation means for the third clock frequency configured in such a manner that the third clock frequency is increased when the number of samples is less than the integer multiple N and decreases when the number of samples is greater than N. | 10-30-2008 |
20080279319 | SAMPLE RATE CONVERTER SYSTEM AND METHOD - A sample rate conversion is accomplished by presenting to a numerically controlled oscillator (NCO) register a clock input at the desired output rate; first-modifying the NCO register contents responsive to a first factor; determining when the first modified NCO register contents are in a predetermined range and in response to the first modified NCO register contents not being in the predetermined range, presenting the first modified NCO register contents to the input of the NCO register; second-modifying, responsive to a second factor, the first modified NCO register contents when the first modified NCO register contents are within the predetermined range and presenting it to the input of the NCO register; and fetching samples, in response to the first-modified NCO register contents being in the predetermined range and interpolating them to produce a resultant sample value at the output rate, and in response to the contents not being in the predetermined range to interpolate the previous sample to produce a resultant sample value at the output rate. | 11-13-2008 |
20080279320 | BI-DIRECTIONAL SINGLE WIRE INTERFACE - A single-wire, bi-directional communication protocol is provided in which the sending device transmits its clock frequency and its bit transmission period and data through a predefined waveform pattern or “learning sequence” that is recognizable by the receiving device and in a period of time, as measured in number of sending clock cycles, that is known to the receiving device. By clocking the full length of the predefined waveform pattern using its own internal clock, the receiving device becomes aware of the bit transmission period of the sending device. | 11-13-2008 |
20080285693 | RECEIVER APPARATUS FOR PROCESSING AMPLITUDE-MODULATED SIGNAL - An amplitude-modulation signal reception apparatus is provided. The amplitude-modulation signal receiver apparatus includes a timing recovery module, a symbol phase shift unit, and an equalizer. The carrier recovery module removes a frequency offset and a phase jitter from an amplitude-modulation signal to generate a carrier recovered signal. The timing recovery module estimates a proper re-sampling position to re-sample the carrier-recovered signal. The phase shifter further shifts the signal that is timing recovered and carrier recovered. The equalizer applies equalization to the shifted signal to remove inter-symbol interference from the shifted signal. | 11-20-2008 |
20080285694 | Clock-data recovery circuit, multi-port receiver including the same and associated methods - A clock-data recovery circuit includes a plurality of input ports and a code generation circuit. The plurality of input ports generates sampling clock signals based on digital control codes and samples input data signals based on the sampling clock signals to generate output data signals and phase detection signals, respectively. The code generation circuit generates the digital control codes based on the phase detection signals received from the input ports during a training mode. | 11-20-2008 |
20080292038 | SIGNAL PROCESSING DEVICE AND METHOD, AND PROGRAM - A signal processing device for detecting, from an input signal expressing data series, the data, including: a sampling clock generating unit for generating, from a driving clock with a predetermined cycle, multiple sampling clocks with mutually different phases and the same cycle as the cycle; a sampling data generating unit for sampling the input signal using the multiple sampling clocks, and generating a plurality of sampling data; a phase comparison data generating unit for generating phase comparison data indicating phase shifting as to the input signal of the sampling clock using the sampling data for each sampling clock; and a data generating unit for generating the data for each sampling clock using the sampling data, and selecting the data of the sampling clock having the phase closest to the phase of the input signal as the original data expressed with the input signal, based on the phase comparison data. | 11-27-2008 |
20080310568 | Digital Sampling Apparatuses and Methods - Methods and apparatus for sampling and determining the frequency of periodic digital signals. An exemplary digital sampling apparatus includes a polyphase sampling apparatus configured to sample a periodic digital signal according to a polyphase clock system having multiple phases. The multiple phases provided by the polyphase clock system are successively distributed in time so that consecutive phases have a periodic phase difference. By using a polyphase clock system, a sampling rate that is equivalent to a sampling clock having a period equal to the phase difference in time between phases of the polyphase clocks is realized. Accordingly, the effective sampling rate of a given periodic digital signal can be increased, or the sampling of higher frequency periodic digitals signals can be achieved, while the underlying logic circuitry used to capture the samples is clocked at a much lower rate. | 12-18-2008 |
20080317181 | Single-Line Bidirectional Communication Apparatus and System - A communication apparatus ( | 12-25-2008 |
20080317182 | Method and Apparatus for Multiresolution / Multipath Searcher - A multipath searcher and method includes a programmable decimation filter configured to adjust a sample rate of a received pilot signal. A plurality of correlators is configured to compare the received pilot signal to a reference code in a first mode and in a second mode. The first mode includes a low resolution search of a search window performed such that the plurality of correlators encompass an entire search window concurrently and the plurality of correlators receives a delayed reference code delayed to correspond with a portion of the search window in which a corresponding correlator performs correlation to identify peaks in the received pilot signal. The second mode includes a high resolution search of a refined search window only at or near identified peaks discovered in the first mode. The high resolution search is focused at the peak location by adjusting delays in the plurality of correlators. | 12-25-2008 |
20090034671 | Synchronous circuit and method for receiving data - The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N−(N is an integer of 2 or larger) phase sampling clock; a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information; a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data. | 02-05-2009 |
20090041170 | Dynamic phase alignment methods and apparatus - Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates. | 02-12-2009 |
20090046820 | Serial Data Sampling Point Control - Serial data transmission is performed using a serial data signal ( | 02-19-2009 |
20090060107 | Data sampling circuit and method for clock and data recovery - A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data. | 03-05-2009 |
20090092211 | Method and apparatus for adjusting serial data signal - A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation. | 04-09-2009 |
20090097603 | COMMON STATE-SPACE MULTI-CHANNEL DIGITAL SAMPLE TIMING PHASE CONTROL OF MULTIPLE READ CHANNELS FOR CORRELATED SIGNALS - Common sample timing control for sample timing of multiple read channels, wherein the signal clocking of the signals received by the multiple read channels are correlated, for example from parallel tracks of magnetic tape that have been written simultaneously. In one embodiment, a common sample timing control comprises multiple phase error inputs, each indicating phase error of one of the read channels. Logic responsive to the multiple phase error inputs is configured to weight and crosscouple the phase error indication of each phase error input with the phase error indication of each other phase error input, and to apply gain related to the variance of noise of the phase error indications. Feedback logic is responsive to the crosscoupling and is configured to provide a sample timing phase estimate for each read channel. | 04-16-2009 |
20090147897 | Receiver and communication system having the same - A receiver may include a clock and data recovery circuit, a detection circuit and a sampling clock generator. The clock and data recovery circuit may receive first data and sample the first data to generate recovered data in response to a reception sampling clock signal. The detection circuit may detect a frequency difference between a transmission sampling clock signal and the reception sampling clock signal by comparing the first data and the reception sampling clock signal to generate a frequency difference detection signal. The sampling clock generator may generate the reception sampling clock signal based on the frequency difference detection signal and a first reference clock signal. Therefore, a communication system including the receiver may effectively reduce a jitter noise. | 06-11-2009 |
20090147898 | METHOD AND SYSTEM FOR RECEIVING DISTANCE MEASUREMENT EQUIPMENT CHANNELS IN AN UNDERSAMPLED BROADBAND RECEIVER - A method to receive channels in an undersampled broadband receiver is provided. The method includes converting received radio frequency signals to downshifted-sampled-digital signals at an analog-to-digital converter in a sampling system, outputting the downshifted-sampled-digital signals to a digital system for digital processing, and determining if the unique identifying code associated with a desired channel is detectable. Each channel in the radio frequency signal has an assigned unique identifying code. When the unique identifying code is detectable, the method includes detecting the unique identifying code associated with the desired channel. When the unique identifying code is undetectable, the method includes outputting control signals from the digital system to tune an adjustable sample clock in the sampling system and tuning the adjustable sample clock based on the output control signals. | 06-11-2009 |
20090190701 | System and method for sampling rate adjustment of digital radio receiver - Methods and systems for adjusting a sampling rate of a digital radio receiver are disclosed that comprise the steps of receiving from a decoder a first frame of data having a first number of samples; determining at the digital radio receiver a phase difference between a receiver clock and a transmitter clock; generating at the digital radio receiver a second frame of data having a second number of samples, wherein the second number of samples depends on the phase difference between the receiver clock and the transmitter clock such that the second number of samples is less than the first number of samples if the transmitter clock is ahead of the receiver clock, and the second number of samples is greater than the first number of samples if the receiver clock is ahead of the transmitter clock; outputting the second frame of data having the second number of samples; and requesting a next frame of data from the decoder at a time that is earlier than a processing time for the first number of samples if the transmitter clock is ahead of the receiver clock and at a time that is later than the processing time for the first number of samples if the receiver clock is ahead of the transmitter clock such that the next frame of data from the decoder and a next transmitter frame are synchronized, and wherein whether the second number of samples is greater than or less than the first number of samples is determined by whether the sampling rate is increased or decreased. | 07-30-2009 |
20090190702 | DIGITAL TIMING CORRECTION SYSTEM, METHOD AND APPARATUS - The method and system of digital timing correction in a digital baseband communication system is disclosed. In one embodiment, a method includes receiving samples at a predetermined time interval based on a current clock signal of a receiver clock, reading in a prompt sample of the received samples and a successor sample of the received samples based on a control signal, interpolating a projected sample based on the prompt sample, the successor sample and a predetermined time offset, determining the time offset for interpolation, by accumulating sampling frequency offset between the receiver clock and a reference clock, relative to a sample timing of the prompt sample, resulting in an interpolated data sample rate reduced by an integer multiple factor compared to a received sample rate and receiving a next sample of the received samples based on the current clock signal of the receiver clock. | 07-30-2009 |
20090190703 | SAMPLING METHOD AND DATA RECOVERY CIRCUIT USING THE SAME - A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first predetermined phase, the third and the fourth strobe respectively lag the first and the second strobe a second predetermined phase, and the second predetermined phase is half of the first predetermined phase. Then, a digital signal is respectively sampled with the first and the second strobe. Thereafter, the positions of data transition points of the digital signal are determined according to the sampling results of the first and the second strobe. Next, the third or the fourth strobe is selected as a preferable sampling strobe according to the determination result. Finally, the digital signal is sampled with the preferable sampling strobe. | 07-30-2009 |
20090196387 | INSTANT-ACQUISITION CLOCK AND DATA RECOVERY SYSTEMS AND METHODS FOR SERIAL COMMUNICATIONS LINKS - Methods and systems for recovering clock and data in data streams communicated over serial communications links. An exemplary serial communications receiver system includes a line receiver configured to receive a data stream from a serial communications link and an instant-acquisition clock and data recovery circuit coupled to the line receiver. The instant-acquisition clock and data recovery circuit includes a time interval detector and a sampling clock selector. The time interval detector is operable to sample the data stream received by the line receiver according to a multi-phase set of sampling clocks. The sampling clock selector is operable to designate one of the sampling clocks of the multi-phase set of sampling clocks as a recovered clock, based on a data transition in the received data stream detected by the time interval detector. The clock selector is configured to designate the sampling clock as the recovered clock independent of data transitions in the data stream that may have occurred prior to the data transition detected by the time interval detector. | 08-06-2009 |
20090202026 | METHOD, NETWORK, APPARATUS AND COMPUTER PROGRAM FOR USING QUALIFYING CIRCUITS IN CLOCK AND DATA RECOVERY CIRCUITS - A method for performing CDR on a digital transmission, and an apparatus, system, and computer program that operate in accordance with the method. The method includes oversampling the digital transmission into oversampled data, detecting a frequency component of the oversampled data, qualifying a decision logic to select a sample of the oversampled data, and selecting at least one sample of the oversampled data using the decision logic. | 08-13-2009 |
20090202027 | Unidirectional sweep training for an interconnect - In one embodiment, the present invention includes a receiver having a delay lock loop (DLL) to receive a clock signal and to generate a plurality of clock phases therefrom, and an offset controller including a first register set for a first phase interpolator and a second register set for a second phase interpolator. At initiation of a track pre-tune process, both phase interpolators are controlled to generate sampling signals at a common clock phase. Other embodiments are described and claimed. | 08-13-2009 |
20090202028 | METHOD, ARTICLE, AND APPARATUS FOR DYNAMIC PHASE DELAY COMPENSATOR - An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a digital circuit. A delayed return data signal is then sampled from the digital circuit. The sampled delayed return data signal is then compared to an expected return data signal. The delayed return data signal is then adjusted as a function of the comparison to increase the communication speed between the emulator and the evaluation board. | 08-13-2009 |
20090207958 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN EVEN SAMPLING SPREAD OVER DIFFERING CLOCK DOMAIN BOUNDARIES - The present invention relates to a method, computer program product and system for generating a sample signal from differing clock domain boundaries. The system comprises a cycle base component, a sample offset component being configured to receive a time-based sample pulse signal, and logic to generate a sample pulse. The sample pulse generation logic is configured to receive a time-based sample pulse signal, a free running counter value, a sample offset counter value, and deliver a sample pulse signal. | 08-20-2009 |
20090207959 | METHOD AND DEVICE FOR DOWNCONVERTING THE SAMPLING FREQUENCY OF A DIGITAL SIGNAL, FOR EXAMPLE IN A NON-INTEGER FREQUENCY RATIO - A method for converting a sampling frequency of a digital signal sampled at a first sampling frequency includes receiving digital signal input samples, and forming output samples corresponding to a second sampling frequency based on the digital signal input samples and an interpolation filter. The first sampling frequency may be larger than the second sampling frequency. The method may further include delivering the output samples. Forming output samples includes, for each of the digital signal input samples, updating current values of N successive output samples with N contributions. The N contributions may be respectively calculated based on a value of a current input sample of the digital input samples weighted by values of N filter coefficients associated with the current input sample, N being fixed and identical for all the digital signal input samples regardless of a value of the conversion ratio between the first and second sampling frequencies. | 08-20-2009 |
20090232262 | Circuit for recovering an output clock from a source clock - An output clock recovery circuit ( | 09-17-2009 |
20090232263 | Timing Errors - A method of analysing a sampled signal that is supplied for decimation, wherein the decimation process produces a decimated version of the signal and wherein the method comprises determining an adjustment, if any is required, to the sampling instant of the signal prior to decimation that will cause the frequency responses of the decimated signal and of a main alias to combine constructively at a given frequency. | 09-17-2009 |
20090238318 | MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIGNALS RECEIVED BY A RECEIVER - A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver. | 09-24-2009 |
20090252265 | CLOCK AND/OR DATA RECOVERY - Embodiments for clock and/or data recovery may comprise two samplers to sample a relatively small number of distinct data sample phase locations of a data pulse relative to an estimate of the location of a center of the data pulse. | 10-08-2009 |
20090262874 | DEVICE AND PROCESS FOR DATA RATE ACQUISITION - A baud rate acquisition circuit ( | 10-22-2009 |
20090279650 | METHOD AND APPARATUS FOR GENERATING CLOCK SIGNALS FOR QUADRATURE SAMPLING - The present invention provides a quadrature-sampling clock signals generation method and apparatus for use in a receiver The apparatus firstly obtains an initial clock signal whose frequency is lower than twice of the carrier frequency of an input signal, then divides the frequency of the initial clock signal by two to obtain two quadrature intermediate clock signals, and finally divides the frequency of the two intermediate clock signals respectively to output two quadrature sampling clock signals. With the clock signal generation method and apparatus of the present invention, it is possible to operate a VCO at a relative low frequency, which will not only reduce the cost of the VCO, but also decrease the power consumption thereof. | 11-12-2009 |
20100002819 | TRACKER CIRCUIT AND METHOD FOR AUTOMATED TEST EQUIPMENT SYSTEMS - A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines whether the transition occurs between the first time and the second time and whether it occurs between the first time and third time and generates an increment/decrement signal indicating a position for the transition. A strobe adjust circuit generates a strobe signal based on the increment/decrement signal. A capture circuit captures the received digital data signal using the strobe signal. | 01-07-2010 |
20100008457 | METHOD AND COMPUTER PROGRAM FOR IDENTIFYING A TRANSITION IN A PHASE-SHIFT KEYING OR FREQUENCY-SHIFT KEYING SIGNAL - A system for identifying phase transitions in phase-shift keying signals and frequency transitions in frequency-shift keying signals broadly comprises a memory and a computing element capable of: selecting a portion of the signal to analyze, wherein the signal comprises a plurality of data samples; applying a transform to the signal to obtain a frequency spectrum; determining a maximum frequency spectrum corresponding to a carrier frequency; determining a starting approximation value of a slope of the phase transition; calculating a bounded limit of slopes within which to search for the phase transition; selecting a plurality of lines; calculating a sum for the data samples associated with each of the lines; and based on the sum for the data samples, identifying a line that corresponds to a location of the phase transition. | 01-14-2010 |
20100040182 | BUST-MODE CLOCK AND DATA RECOVERY CIRCUIT USING PHASE SELECTING TECHNOLOGY - A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase. | 02-18-2010 |
20100046683 | ADAPTIVE CLOCK AND EQUALIZATION CONTROL SYSTEMS AND METHODS FOR DATA RECEIVERS IN COMMUNICATIONS SYSTEMS - Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods adapted to achieve optimum sampling of data and amplitude sampling clock signals to accurately detect data bits and optimize system equalization settings, including, decision-feedback equalizer and/or an optional linear equalizer preceding a decision-feedback equalizer. | 02-25-2010 |
20100054382 | Recovering Data From An Oversampled Bit Stream With A Plesiochronous Receiver - Data is recovered in a plesiochronous receiver from an oversampled bit stream. In one example, a bit stream is received and oversampled in blocks to produce successive sets of samples, each set of samples representing a same number of bits. Transitions are found in the samples. Positions of the found transitions are determined and a single mask of a plurality of masks is selected. The selected mask is applied to the set of samples to determine values for the block of bits. | 03-04-2010 |
20100091922 | SAMPLE RATE CONVERTER - A sample rate converter circuit receives a first signal at a first sampling frequency and for outputs a second signal, representative of the first signal, having a second sampling frequency. The sample rate converter comprises: a buffer, for storing data samples received from said first signal; a first loop circuit, for receiving a first clock signal corresponding to the first sampling frequency and a second clock signal corresponding to the second sampling frequency, and for generating an estimate of a ratio of the first sampling frequency to the second sampling frequency; and a second loop circuit, for receiving the first clock signal, the second clock signal and the estimate of the ratio of the first sampling frequency to the second sampling frequency, and for outputting a write pointer so that the data samples can be stored in the buffer, and for outputting a read pointer so that the data samples can be read from the buffer, with a first offset between the read pointer and the write pointer, such that the first offset is substantially independent of the ratio of the first sampling frequency to the second sampling frequency. | 04-15-2010 |
20100091923 | CIRCUIT FOR A RADIO SYSTEM, USE AND METHOD FOR OPERATION - A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values. | 04-15-2010 |
20100091924 | SYSTEM AND METHOD FOR MULTILATERATING A POSITION OF A TARGET USING MOBILE REMOTE RECEIVING UNITS - A method of multilaterating the position of a target, including the steps of deploying a plurality of time synchronized receiving units in a network that allows the receiving units to communicate with a central processor; receiving a target signal from the target at each receiving unit; determining a time of arrival for the target signal at each receiving unit; determining position data for each receiving unit at the time when the target signal is received at each respective receiving unit; and using the time of arrival and position data for each receiving unit to determine the position of the target by multilateration. A system for carrying out the method is also disclosed. | 04-15-2010 |
20100104055 | APPARATUS AND METHOD FOR DIGITAL UP CONVERTING IN A MOBILE COMMUNICATION SYSTEM - An apparatus and method for digital up converting in a mobile communication system are provided. The apparatus includes a Selectable Input Logic (SIL), a Scalable Clock Distribution Logic (SCDL), a filter logic, and a mixer logic. The SIL performs decimation at a decimation rate. The SCDL controls a clock frequency. The filter logic performs channel filtering for the decimated signal, and performs interpolation at an interpolation rate variable. The mixer logic up-converts the signal provided from the filter logic. | 04-29-2010 |
20100119023 | RECEPTION APPARATUS - In a reception apparatus | 05-13-2010 |
20100142665 | Methods of Processing A Wireless Communication Signal, Wireless Communication Synchronization Methods, and A Radio Frequency Ideentification Device Communication Method - Wireless communications devices, methods of processing a wireless communication signal, wireless communication synchronization methods and a radio frequency identification device communication method are described. In one aspect, a wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, communication circuitry coupled with the antenna and configured to sample the electrical energy to process the wireless communication signal, synchronization circuitry coupled with the antenna and the communication circuitry and configured to generate a clock signal to control sampling of the electrical energy using the communication circuitry, wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal responsive to a plurality of transitions of the electrical energy during a first data period and wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal during a second data period including generating at least one of the transitions independent of transitions of the electrical energy. | 06-10-2010 |
20100158178 | MULTIRATE RESAMPLING AND FILTERING SYSTEM AND METHOD - A discrete time signal resampling circuit ( | 06-24-2010 |
20100158179 | SYMBOL TIMING ACQUISITION USING EARLY-LATE INTERPOLATION - Symbol timing acquisition is described for a wireless broadband signal received at a user terminal from a gateway via a satellite. In-phase and quadrature channels of the wireless signal may each be sampled at a rate of one sample per symbol. The samples may be interpolated to generate an early interpolation and a late interpolation for each of the samples. A difference measurement is obtained between the early interpolation and the late interpolation for a set of the samples. A number of the difference measurements may be averaged, and symbol timing may be modified based on the average. This process may be continued on an iterative basis to acquire symbol timing. | 06-24-2010 |
20100172453 | High availability clock synchronization and distribution for mobile backhaul networks - Fully redundant clock systems are provided on network nodes coupled by redundant multisegment psuedowires (MSPWs) within an internet-protocol (IP)-based mobile backhaul network. The primary clock system includes a primary master clock on a first node and a primary slave clock on a second node coupled via a primary MSPW, while the secondary clock system includes a secondary master clock on the first node and a secondary slave clock on the second node coupled via a secondary MSPW. The primary and secondary slave clocks synchronize with their respective primary and secondary master clocks via their respective MSPWs. A clock controller maintains the secondary clock system in a hot-stand-by mode, and upon determining that a switch-over is needed, automatically switches from the primary clock system to the secondary clock system. | 07-08-2010 |
20100220828 | EDGE-BASED SAMPLER OFFSET CORRECTION - Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler ( | 09-02-2010 |
20100266079 | METHOD AND SYSTEM FOR BIT DETECTION AND SYNCHRONIZATION - A bit synchronization method is proposed. The method includes buffering a plurality of samples from a signal stream, scanning the buffered samples for transitions and updating a zero-crossing histogram buffer upon detection of the transitions. The method further includes detecting at least two peaks simultaneously from the updated zero-crossing histogram buffer, fixing at least two boundaries from the detected peaks, and integrating the buffered samples within the boundaries. Finally the method includes generating an output signal comprising a synchronized bit stream from the integrated samples. | 10-21-2010 |
20100296614 | Method for carrying out bidirectional communications - In a method for carrying out bidirectional communications between a first electronic unit and a second electronic unit, a clock signal and an input signal synchronized with the clock signal are transmitted from the first electronic unit to the second electronic unit, and the second electronic unit transmits a response sequence in an output signal to the first electronic unit. In addition, an unambiguous test sequence is generated in the second electronic unit and transmitted to the first electronic unit prior to the response sequence in the output signal, a time sequence between the test sequence and the response sequence in the output signal making it possible to take into account a time delay between the first electronic unit and the second electronic unit. | 11-25-2010 |
20110064176 | CLOCK RECOVERY CIRCUIT AND DATA RECOVERY CIRCUIT - A serial input signal is sampled in synchronization with a plurality of first clock signals to obtain a plurality of sampling data pieces. A phase comparison circuit outputs a serial phase information signal based on the sampling data pieces. A serial-parallel conversion circuit performs a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a lower frequency, to output a parallel phase information signal. A digital filtering circuit calculates phase deviation and phase advance-delay signals based on the parallel phase information signal in synchronization with the second clock signal. By these signals, a phase control amount processing circuit generates a phase control signal. The phase control signal is in synchronization with third clock signals having a higher frequency. A phase interpolation circuit adjusts the phases of the third clock signals based on the phase control signal to output the first clock signals. | 03-17-2011 |
20110075780 | Method and Apparatus for Bandpass Digital to Analog Converter - Systems and methods for providing a mechanism by which digital signals can be converted to analog signals with an efficient structure that reduces the number of filters required by providing a mechanism for cancelling images that would otherwise be generated. By adjusting three parameters in the system, a selection can be made as to whether to generate upper sidebands, lower sidebands and in which direction the envelope of the output from the system will be skewed. | 03-31-2011 |
20110096882 | Method and apparatus for deskewing data transmissions - The present invention discloses a method and apparatus for addressing the issue of clock skew in a data signal while making efficient use of space on an integrated chip (IC) by utilising a physical delay line controlled by a state machine in conjunction with pre-requisite chip architecture. The pre-requisite chip architecture samples the incoming data signal in response to a clocking signal input from the physical delay line; the physical delay line responds to commands from the state machine to increment the delay of the physical delay line to produce samples which describe the incoming data signal and delineate its data valid window. | 04-28-2011 |
20110122979 | Apparatus and methods for estimating and compensating sampling clock offset - An apparatus for sampling clock recovery (SCO) and methods for estimating and compensating SCO are provided. The apparatus comprises a symbol timing adjustment module for shifting forward or backward symbol timing of the transmitted OFDM symbols; a discrete Fourier transform (DFT) processor for performing DFT to an output from the symbol timing adjustment module; a channel estimator for undertaking a channel frequency response estimation based on a channel estimation sequence; a SCO phase rotator for receiving and performing phase shift on the transmitted OFDM symbols of a frame header and a frame payload; an SCO estimation stage for undertaking an SCO estimation based on a pilot-subcarrier-related output of the SCO phase rotator and the CFR estimation; and an SCO compensation distributor for dividing the SCO estimation into integer and fractional portions and then distributing them into the symbol timing adjustment module and the SCO phase rotator, respectively. | 05-26-2011 |
20110150157 | METHOD AND APPARATUS FOR ESTIMATING SYMBOL TIMING - Provided is a symbol timing estimating apparatus and method that may generate at least one sampled preamble signal by sampling a preamble signal with changing a phase of the preamble signal based on a symbol speed, calculate a power value of each of the at least one sampled preamble signal, and estimate a symbol timing of a sampled preamble signal having a maximum power value by comparing each power value among the at least one sampled preamble signal. | 06-23-2011 |
20110150158 | Radio communication apparatus and method - A radio communication apparatus includes a clock reproducer unit which repetitively detects a symbol timing from a Nyquist point in detection-result data. A symbol generator unit controllably generates or non-generates a to-be-transmitted symbol or symbols at every symbol timing detected by the clock reproducer unit, converts the to-be-transmitted symbol or symbols into modulating data pieces, and outputs the modulating data pieces to a FIFO buffer. A D/A converter reads out modulating data pieces from the FIFO buffer at a predetermined rate and converts the read-out modulating data pieces into an analog modulating signal for use in modulation of a carrier. A controller unit controls a number of the to-be-transmitted symbol or symbols generated by the symbol generator unit at every symbol timing to hold a number of modulating data pieces in the FIFO buffer in a predetermined range. | 06-23-2011 |
20110170644 | METHOD FOR CLOCK AND DATA RECOVERY - An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one or more sets of non-transitioning phases are identified and then a final center phase that accurately represents the bits belonging to the input bit stream is selected. The data samples corresponding to the final center phase are extracted, thereby recovering the clock signal and data bits from the input bit stream. | 07-14-2011 |
20110194659 | APPARATUS AND METHOD FOR CLOCK AND DATA RECOVERY - Apparatus and methods for clock and data recovery are disclosed. In one embodiment, a clock and data recovery system includes a sampler, a deserializer, a phase detector and a frequency detector. The sampler may be configured to sample a serial data stream to produce data samples and transition samples. The deserializer may be configured to deserialize the data samples and the transition samples to produce deserialized data samples and deserialized transition samples. The deserialized data samples and the deserialized transition samples can be aligned and provided to the phase detector and the frequency detector, thereby improving phase alignment and cycle slip detection. | 08-11-2011 |
20110194660 | APPARATUS AND METHOD FOR ROTATIONAL FREQUENCY DETECTION - Apparatus and methods for rotational frequency detection are disclosed. In one embodiment, a rotational frequency detector is configured to receive samples taken from a serial data stream and to generate a frequency up error signal or a frequency down error signal. The rotational frequency detector processes a first set of samples to generate first transition data, which may be stored in a memory. The rotational frequency detector processes a second and third set of samples to generate second and third transition data. The frequency up or frequency down error signal is generated based at least partly on the first, second or third transition data. This configuration can reduce the maximum operating frequency of the rotational frequency detector, thereby simplifying the rotational frequency detector design to a point that a conventional static digital CMOS circuit design flow can be used to design the rotational frequency detector. | 08-11-2011 |
20110194661 | DIGITAL AUDIO PROCESSING SYSTEM AND METHOD - A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the adjusted sample to a nearest predetermined phase value of a plurality of predetermined phase values. The symbol recognition logic determines a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The prior nearest predetermined phase value corresponds to a prior sample of the phase component of the signal. The offset value is based on a detected error of the prior sample of the phase component of the signal. The digital audio processing system also includes an output to provide a second signal that indicates the symbol. | 08-11-2011 |
20120008723 | PHASE DETECTION METHOD AND CIRCUIT - Phase detection methods are provided. According to a first embodiment, a signal is sampled in order to obtain an amplitude sample. Then an absolute value of the difference of the amplitude sample minus an average of amplitude samples is calculated. According to a second embodiment, the signal is sampled at a first and second phase. This results in first and second amplitude samples which are compared to a first and second plurality of thresholds, respectively, in order to assign first and second weighting values to each first and second amplitude sample, respectively, depending on to which range between two adjacent thresholds the first and second amplitude sample belong. Then the sum or difference of said first and second weighting values is calculated. | 01-12-2012 |
20120020444 | Slicing level and sampling phase adaptation circuitry for data recovery systems - The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers. | 01-26-2012 |
20120020445 | Wireless sensor synchronization methods - A method of sampling data includes providing a plurality of wireless nodes, wherein each of the wireless nodes includes a receiver, a real time clock and a counter. Ticks of the real time clock are counted by the counter. The method also includes broadcasting a common beacon for receipt by receivers of each of the wireless nodes, and upon receipt of the common beacon setting each of the counters to a first preset value. | 01-26-2012 |
20120033771 | Multi-Channel Sample Rate Converter - A method of sample rate conversion and clock synchronization for multiple asynchronous input signals using a single processing core. A sample processing clock with a frequency equal to or higher than the input signal clock frequencies is provided. The clock period is divided into a number of time slots corresponding to the input signals. For each valid sample of an input signal, the core performs a first stage processing operation on the sample. Subsequently, for each required sample of an output signal, the core performs a second stage processing operation to generate the output sample. | 02-09-2012 |
20120039426 | CLOCK DATA RECOVERY CIRCUIT AND CLOCK DATA RECOVERY METHOD - A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data. | 02-16-2012 |
20120093273 | GLITCH-FREE OVERSAMPLING CLOCK AND DATA RECOVERY - A clock and data recovery (CDR) circuit includes an edge detector, an edge selector, and a phase selector. The edge detector is arranged to detect edges of serial input data and to provide an edge detection result. The serial input data is oversampled utilizing multiple clock phases. The edge selector for selecting one of the multiple clock phases for a recovered clock is arranged to provide an edge selection result, to receive the last edge selection result as a first input, and to receive the edge detection result as a second input. The phase selector is arranged to provide the recovered clock and recovered data. | 04-19-2012 |
20120099688 | OVERSAMPLING CIRCUIT, SERIAL COMMUNICATION APPARATUS AND OVERSAMPLING METHOD - An oversampling circuit includes: a generation unit configured to generate multiphase serial data by delaying serial data by a predetermined time; and an oversampling unit configured to oversample the multiphase serial data by using multiphase clocks, wherein a phase difference of the multiphase serial data is set to be a sum of an oversampling interval used in the oversampling circuit and an integral multiple of a phase difference of the multiphase clocks. | 04-26-2012 |
20120155586 | Adaptive Frequency Synthesis for a Serial Data Interface - Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate. | 06-21-2012 |
20120155587 | Systems and Methods for Improved Timing Recovery - Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a data input and to provide a first interpolated output corresponding to a first phase, and the second digital interpolation circuit is operable to receive the data input and to provide a second interpolated output corresponding to a second phase. The phase selection circuit operable to select the first phase for processing, and the sampling clock rotation circuit is operable to move a sampling clock away from the first phase. | 06-21-2012 |
20120170697 | DATA RECOVERY APPARATUS AND METHOD BY USING OVER-SAMPLING - A data recovery apparatus and method by using over-sampling are provided. The data recovery apparatus by using over-sampling includes an over-sampling module, a data regeneration unit, a phase alignment unit, a phase decision module, and an output data correction unit. The over-sampling module samples serial data according to a clock signal, so as to output M-bit data, in which each bit in the serial data is sampled N times. The phase alignment unit selects specific M-bit data from a P-bit signal output by the data regeneration unit, and distinguishes the specific M-bit data to X groups of N-bit signals. The phase decision module determines a direction of phase adjustment according to the specific M-bit data. The output data correction unit selects and outputs first or second recovery data constituted by first or second specific bits of each group of N-bit signal according to the direction of phase adjustment. | 07-05-2012 |
20120257698 | System for Adaptive Sampled Medical Signal Interpolative Reconstruction for Use in Patient Monitoring - A patient medical signal processing system adaptively reconstructs a medical signal sampled using a varying sampling rate. The system includes an input processor and a signal processor. The input processor receives first data and second data. The first data represents a first portion of a medical signal derived by sampling at a first sampling rate and the second data represents a second portion of the medical signal derived by sampling at a second sampling rate. The first and the second sampling rates are different and comprise a master clock rate or an integer division of the master clock rate. A signal processor provides a reconstructed sampled medical signal by, interpolating the second data to provide third data at the first sampling rate and combining the first data and the third data to provide the reconstructed sampled medical signal. | 10-11-2012 |
20120263264 | SYSTEM AND METHOD TO OVERCOME WANDER ACCUMULATION TO ACHIEVE PRECISION CLOCK DISTRIBUTION OVER LARGE NETWORKS - A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the previous stage, updates this error message with its own stage clock error, and then transmits the updated grand clock error to the next stage. This enables the synchronization algorithm to compensate for the error of the previous stage, effectively locking each clock regenerator stage to the grand master clock directly. | 10-18-2012 |
20120269308 | SAMPLING CLOCK SELECTION MODULE OF SERIAL DATA STREAM - A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases. | 10-25-2012 |
20130010908 | IMPLIED CLOCK - Systems and methods providing clocking between various components or sub-components are shown. Embodiments implement an implied clock technique which reduces the number of signal lines, signaling overhead required for an encoded clock signal, and/or and power consumption for a high speed communication link. In accordance with embodiments efficient communication is provided between a core device and a remote device by the core device providing both clock and data signals to the remote device and the remote device providing a data signal at a predetermined clock rate without communicating its clock signal. The core device of this embodiment determines an “implied clock” suitable for accurately receiving data from the remote device. | 01-10-2013 |
20130058445 | SAMPLING PHASE SELECTION METHOD FOR A STREAM OF DATA BITS - The current disclosure discloses a sampling phase selection method for a data stream, wherein the data stream has a variable data rate in a fixed time period. The method comprises the following steps: generating M section signals with the same time interval during the fixed time period of the data stream, generating N continuous clock phases according to a rising edge of each of the section signals, selecting one of the continuous clock phases corresponding to the different section signals in turn to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, repeating the selecting and the sampling steps to generate N flag signals corresponding to the different section signals, and selecting a final sampling phase according to the N flag signals corresponding to the different section signals. | 03-07-2013 |
20130101075 | METHOD AND APPARATUS FOR REGULATING THE SAMPLING PHASE - Embodiments of the invention relate to methods and circuits for controlling the sampling phase of a signal that is to be regenerated by sampling, particularly a serial communication signal, having method steps or means for oversampling the signal in order to ascertain samples of the signal during predetermined sampling phases, for determining differential errors between the samples during different instances of the predetermined sampling phases, for determining a differential error rate between the samples to at least one first and at least one second sampling phase on the basis of the ascertained differential errors, and for comparing at least two differential error rates based on at least two different sampling phase pairs in order to ascertain a decision concerning which of the predetermined sampling phases can be selected as a reference sampling phase for correctly regenerating the signal. | 04-25-2013 |
20130195234 | Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets - A circuit for performing clock recovery according to a received digital signal | 08-01-2013 |
20130216013 | SYSTEM AND METHOD FOR DETERMINING A TIME FOR SAFELY SAMPLING A SIGNAL OF A CLOCK DOMAIN - A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate. | 08-22-2013 |
20130243138 | APPARATUS, SYSTEM, AND METHOD FOR TIMING RECOVERY - Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal. | 09-19-2013 |
20130259177 | DATA RECOVERY CIRCUIT AND OPERATION METHOD THEREOF - In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data. | 10-03-2013 |
20130336434 | METHOD AND DEVICE FOR ESTABLISHING ROUTER NEIGHBOR - Embodiments of the present invention relate to a method and a device for establishing a router neighbor. The method includes: obtaining a first discovery protocol Hello message sent by a neighbor router, where the first Hello message carries identification information and priority information of the neighbor router; and determining whether to add the relevant information of the neighbor router into the neighbor list of a local end router, according to the priority information of the neighbor router, and/or priority information of the local end router, and/or whether the identification information of the neighbor router is identification information of an opposite end device of a virtual link configured for the local end router. The embodiments of the present invention ensure that a small device can establish neighbor relationships with a DR and a BDR on a network and that the small device's OSPF function is normal. | 12-19-2013 |
20140037033 | Techniques for Varying a Periodic Signal Based on Changes in a Data Rate - A circuit includes phase detection, frequency adjustment, sampler, and control circuits. The phase detection circuit compares phases of first and second periodic signals to generate a control signal. The frequency adjustment circuit adjusts a frequency of the second periodic signal and a frequency of a third periodic signal based on the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The control circuit adjusts the frequency of the third periodic signal based on the data signal changing from a first data rate to a second data rate while maintaining the frequency of the second periodic signal constant. The control circuit adjusts the frequency of the second periodic signal and the frequency of the third periodic signal based on the data signal changing from the second data rate to a third data rate. | 02-06-2014 |
20140050288 | APPARATUS & METHODS FOR SYMBOL TIMING ERROR DETECTION, TRACKING AND CORRECTION - Systems and methods for adjusting timing in a communication system, such as an OFDM system are described. In one implementation an error signal is generated to adjust the timing of a variable rate interpolator so as to adjust FFT timing. The error signal may be based on detection of significant peaks in an estimate of the impulse response of the channel, with the peak locations being tracked over subsequent symbols and the system timing adjusted in response to changes in the peaks. | 02-20-2014 |
20140064421 | METHOD AND APPARATUS FOR SAMPLING A SERIAL DATA STREAM USING A CLOCK SIGNAL, BASED ON A COUNTER PATTERN - In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit. | 03-06-2014 |
20140126676 | Estimation of Sample Clock Frequency Offset Based on Error Vector Magnitude - A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/T | 05-08-2014 |
20140133614 | Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability - The use of eye pattern circuitry associated with a serial receiver embedded in an integrated circuit (e.g. in an FPGA) relies on the signal quality and signal frequency being sufficient for the serial receiver to lock onto the signal: if this is not possible then it is not possible to obtain an eye pattern. | 05-15-2014 |
20140169513 | COMMUNICATION SYSTEM INCLUDING MULTIPLE RECEIVING ANTENNAS AND TIME TRACKING METHOD THEREOF - A tracking method and apparatus of a communication system to prevent a timing difference and bit error rate performance degradation caused by unstable characteristics of a plurality of circuit devices are provided. The tracking method and apparatus include sampling signals received at receiving antennas, tracking sample values resulting from the sampling of the signals, and combining the tracked sample values. | 06-19-2014 |
20140192938 | SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD - A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals. | 07-10-2014 |
20140192939 | Alignment of Non-Synchronous Data Streams - An apparatus for aligning non-synchronous input data streams received in the apparatus, the apparatus comprising an analogue to digital converter arrangement for digitising the data streams into a plurality of sequences of samples; and a synchronisation processing arrangement for generating alignment pulses for each sequence of the plurality of sequences of samples, for arranging each sequence of samples with respect to the alignment pulses for the sequence and for synchronisation the delivery of said plurality of sequences of samples to a common processor with respect to the respective alignment pulses. The synchronisation processing arrangement may comprise a processing chain for each antenna feed of said plurality of antenna feeds and each processing chain may comprise an alignment pulse generator for generating an alignment pulse for the sequence of samples corresponding to the processing chain. The input data streams may be received by a plurality of antenna feeds. | 07-10-2014 |
20140192940 | COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS - A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component. | 07-10-2014 |
20140211896 | Receiver and Methods for Calibration Thereof - There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards. | 07-31-2014 |
20140254731 | Dithering Circuit for Serial Data Transmission - A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system clock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock. | 09-11-2014 |
20140270024 | APPARATUS AND METHOD FOR DETECTION OF TIME TRACKING FAILURE - According to an example embodiment of this application, a method may include calculating a timing offset estimate based on a received reference signal; accumulating consecutive timing offset estimates to generate a cumulative timing offset estimate; comparing the cumulative timing offset estimate against a threshold; and determining whether a time tracking has failed based on the comparison between the cumulative timing offset estimate and the threshold. | 09-18-2014 |
20140270025 | COMMUNICATION SYSTEM WITH CHARGE PUMP MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a wireless communication system includes: synthesizing an incoming clock reference by differentiating an even cycle signal and an odd cycle signal; commutating a pair of resistors (R | 09-18-2014 |
20140270026 | MULTI-WIRE SINGLE-ENDED PUSH-PULL LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols. | 09-18-2014 |
20140270027 | PROTECTION CONTROL APPARATUS - A protection control apparatus includes a control-signal output circuit configured to generate a sampling signal in synchronization with a 1PPS signal and output, as a control signal, data numbers cyclically counted up every time the sampling signal is generated and the sampling signal and a data output unit configured to convert a system electrical quantity into digital data based on the control signal and output the digital data. The control-signal output circuit includes a number-of-clocks calculating circuit configured to calculate a second number of clocks and a third number of clocks and a synchronization control unit configured to calculate a difference between a first number of clocks and a second number of clocks, control a cycle of the sampling signal based on the difference and the third number of clocks, and synchronize generation timing of the sampling signal with the 1PPS signal. | 09-18-2014 |
20140314190 | Methods and Systems for Clocking a Physical Layer Interface - A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals. | 10-23-2014 |
20140348278 | USING MULTIPLE OSCILLATORS ACROSS A SUB-NETWORK FOR IMPROVED HOLDOVER - A method and system are provided for improving maintenance of timing information when a node enters holdover due to a lost connection between a sub-network and a reference clock. Each node within the sub-network sends information concerning the drift of its local oscillator to a single node, and the single node uses this information to determine timing information for the entire sub-network. The single node may also use knowledge of the characteristics of the local oscillators. In this way, drift from the reference clock can be minimized without incurring significant added hardware costs. | 11-27-2014 |
20140348279 | DIGITAL SIGNAL UP-CONVERTING APPARATUS AND RELATED DIGITAL SIGNAL UP-CONVERTING METHOD - A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal. | 11-27-2014 |
20140369453 | RECEIVERS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data. | 12-18-2014 |
20140369454 | DIGITAL RECEIVERS - A method for processing a received digital signal includes generating a clock signal used for sampling the received signal by comparator which compares the received signal to a reference. A phase shifter adjusts the phase of the first clock signal to maximize the vertical eye opening of the signal at the sampling time. The phase of the clock signal may be adjusted in a first direction and a measure of vertical eye opening of the signal compared to a previous measure. If the measure of vertical eye opening has increased the signal another phase adjustment may be made in the same direction whereas if the vertical eye opening of the signal has decreased a further phase adjustment in the opposite direction may be made. | 12-18-2014 |
20140376675 | RECEIVER CIRCUIT AND RECEIVING METHOD - A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase. | 12-25-2014 |
20150010121 | CALIBRATION OF CLOCK PATH MISMATCHES BETWEEN DATA AND ERROR SLICER - Embodiments include systems and methods for calibrating effective clock path mismatches in a receiver circuit. For example, a serializer/deserializer (SERDES) circuit includes a data slicer that generates data sampler decisions by sampling an input signal according to a clocking signal, and an error slicer that generates error slicer samples by sampling the input signal according to the clocking signal. Each of the data slicer and error slicer has an associated clock path delay, and the delays are typically different (e.g., due to manufacturing differences). A calibrator performs iteratively shifted sampling and comparing of the data sampler decisions and the error slicer samples over a plurality of clocking locations to determine an effective clock path mismatch. The calibrator can then determine and apply a clocking offset to the data slicer and/or the error slicer to effectively shift data and error sampling, thereby compensating for the effective clock path mismatch. | 01-08-2015 |
20150016579 | CLOCK AND DATA RECOVERY DEVICE, SAMPLER AND SAMPLING METHOD THEREOF - A clock and data recovery device, a sampler and a sampling method thereof are provided. The sampler includes a phase generation circuit and a first edge sampling circuit electrically connected with the phase generation circuit. The phase generation circuit is configured to generate a plurality of first phases which have different phase values. The first edge sampling circuit is configured to sample a plurality of first edge values of a plurality of bits of a data signal according to the first phases so that the clock and data recovery device determines a clock of the data signal according to the first edge values. | 01-15-2015 |
20150063512 | METHOD FOR SYMBOL SAMPLING IN A HIGH TIME DELAY SPREAD INTERFERENCE ENVIRONMENT - Symbol sampling in a high time delay spread interference environment includes acquiring ( | 03-05-2015 |
20150063513 | OPERATING METHOD OF HUMAN INTERFACE DEVICE - An operating method of a human interface device includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and calibrating detected information obtained operating with the oversampling signal according to the correction parameter. | 03-05-2015 |
20150063514 | DATA RECEPTION APPARATUS AND DATA COMMUNICATION SYSTEM - A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples). | 03-05-2015 |
20150092899 | SIGNAL RECEIVER WITH MULTI-LEVEL SAMPLING - A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal. | 04-02-2015 |
20150098536 | N FACTORIAL DUAL DATA RATE CLOCK AND DATA RECOVERY - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively. | 04-09-2015 |
20150098537 | METHOD TO ENHANCE MIPI D-PHY LINK RATE WITH MINIMAL PHY CHANGES AND NO PROTOCOL CHANGES - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods. | 04-09-2015 |
20150098538 | SPECIFYING A 3-PHASE OR N-PHASE EYE PATTERN - System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols may be generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities. | 04-09-2015 |
20150103961 | DIGITAL FREQUENCY BAND DETECTOR FOR CLOCK AND DATA RECOVERY - A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR. | 04-16-2015 |
20150103962 | RECEIVING DEVICE AND DATA INTERPOLATION PROCESSING METHOD - There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed. | 04-16-2015 |
20150117578 | TRANSMISSION PROTOCOL DECODING METHOD, DEVICE, AND TRANSMISSION PROTOCOL DECODING CHIP - A transmission protocol decoding method, device, and a transport protocol decoder chip are provided for generating an oscillation signal; detecting a frame start signal, and outputting a sampling control signal when the frame start signal is detected; counting an oscillation period of the oscillation signal within a time period of low level bits of a frame start byte to obtain a count value after receiving the control signal, and then processing a division operation to the count value to output a quotient and a remainder; determining a sampling period according to the quotient and the remainder to generate a sampling pulse, and then decoding a data byte of a transmission data according to the sampling pulse. | 04-30-2015 |
20150117579 | RECEPTION CIRCUIT - A reception circuit includes: an equalizer; a comparator to compare an output signal of the equalizer with first, second, and third thresholds at a first-timing to output first, second, and third comparison-results, respectively; a selector to select any one of the first and second comparison-results based on a determination-result at a timing before the first-timing, and update the determination-result; a detector to detect a phase information based on the first or second comparison-result not selected; a shifter to adjust a sampling clock phase based on the phase information detected; and a controller to set a third threshold based on the first and second thresholds by either adjusting the first and second thresholds based on the output signal amplitude or adding/subtracting a first value to/from the output signal, detect an equalization-result based on the third comparison-result by the set third threshold, and adjust an equalization coefficient based on the detected equalization-result. | 04-30-2015 |
20150146829 | METHOD FOR SUPPRESSING INTERFERENCES IN A SAMPLING PROCESS AS WELL AS A DEVICE FOR CARRYING OUT THE METHOD - A method is provided for suppressing interferences in a sampling process. The method includes the method step of sampling an analog useful signal at a sampling frequency f as well as determining whether an interference amplitude is present. In the presence of an interference amplitude, a stochastic shift of the chronologically equidistant sampling points in time, which are determined by the sampling frequency f, is carried out within a range [=Δt; +Δt] ( | 05-28-2015 |
20150146830 | CLOCK RECOVERY FOR A DATA RECEIVING UNIT - Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value, wherein the selecting is performed depending on the early/late signal and depending on the phase rotation counter value. | 05-28-2015 |
20150295701 | MULTI-LANE N-FACTORIAL (N!) AND OTHER MULTI-WIRE COMMUNICATION SYSTEMS - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multi-lane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link. | 10-15-2015 |
20150312019 | Clock and Data Recovery Using Receiver Clock Spread Spectrum Modulation and Offset Compensation - A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock. | 10-29-2015 |
20150326384 | Circuit and method for clock data recovery and circuit and method for analyzing equalized signal - A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal. | 11-12-2015 |
20150326386 | COMMUNICATION RECEPTION WITH COMPENSATION FOR RELATIVE VARIATION BETWEEN TRANSMIT BIT INTERVAL AND RECEIVER SAMPLING INTERVAL - The effect of timing inaccuracy is compensated for in a communication receiver that receives a transmission of bits temporally separated by a bit interval. The compensation employs an oversampling clock whose frequency defines a sampling interval that is smaller than the bit interval, which bit interval is nominally a predetermined integer multiple of the sampling interval. The oversampling clock samples the received transmission to produce an incoming sample stream. The incoming sample stream is decoded by a plurality of different decoding operations to produce, respectively, a plurality of decoded sample streams. It is determined whether the received transmission is decodable from any of the decoded sample streams. | 11-12-2015 |
20150349943 | METHOD AND APPARATUS FOR GENERATING SAMPLING FREQUENCY - A method and apparatus for generating a sampling frequency are provided. A signal is generated, of which frequency is a predetermined multiple of a reference clock, and a frequency offset in a channel is extracted from the entire frequency offset. The amount of shift is calculated by dividing the extracted frequency offset by a predetermined value, and a final sampling frequency is obtained by shifting the frequency of the generated signal by the amount of shift. | 12-03-2015 |
20150349980 | PHASE INTERPOLATOR - A phase interpolator has: a mixer configured to synthesize phases of a plurality of input cosine-wave or sine-wave signals whose phases are different from each other; and a bias generator configured to output a bias signal in accordance with a phase control signal to the mixer, and the mixer outputs a signal with a phase in accordance with the phase control signal. | 12-03-2015 |
20150365226 | MULTI-WIRE SINGLE-ENDED PUSH-PULL LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols. | 12-17-2015 |
20150372803 | METHOD AND APPARATUS FOR DATA AIDED TIMING RECOVERY IN 10GBASE-T SYSTEM - A method of data-aided timing recovery for Ethernet systems is disclosed. A first device negotiates a pseudorandom number sequence with a second device and receives a data signal from the second device. The first device samples the received data signal to recover a first training sequence. The first device also generates a second training sequence based on the pseudorandom number sequence. The second training sequence is then synchronized with the first training sequence. The synchronized second training sequence is used to align a receive clock signal of the first device with the data signal received from the second device. | 12-24-2015 |
20160020896 | Probabilistic Digital Delay Measurement Device - A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value. | 01-21-2016 |
20160028534 | MULTI-LANE N-FACTORIAL (N!) AND OTHER MULTI-WIRE COMMUNICATION SYSTEMS - System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal. | 01-28-2016 |
20160056949 | METHOD AND APPARATUS FOR MANAGING ESTIMATION AND CALIBRATION OF NON-IDEALITY OF A PHASE INTERPOLATOR (PI)-BASED CLOCK AND DATA RECOVERY (CDR) CIRCUIT - A method for managing estimation and calibration of non-ideality of a Clock and Data Recovery (CDR) circuit. The method comprises A) selecting a first output path for calibration comprising at least a first Phase Interpolator (PI) of a plurality of PIs, at least one of a plurality of output-side programmable delay elements, an external delay element, at least one sampler, a first and a second external multiplexer, B) programming the output-side programmable delay element using a Digital Delay Control Code (DDCC), C) calibrating the external delay element until a given predetermined criterion based on an early-late detection method is met, D) upon satisfaction of the predetermined criterion, retaining a corresponding Digital External Delay Control Code (DEDCC) in the external delay element for subsequent use, E) selecting a second output path for calibration comprising at least a second PI of the plurality of PIs, the at least one of the plurality of output-side programmable delay elements, external delay element, at least one sampler, the first and second external multiplexers, F) calibrating the output-side programmable delay element until the given predetermined criterion based on the early-late detection method is met, G) upon satisfaction of the predetermined criterion, retaining the corresponding DDCC in the output-side programmable delay element for subsequent use, H) repeating the steps E-G for each of the remaining PIs such that the remaining output-side programmable delay elements are each separately calibrated, I) selecting a first input path for calibration comprising the at least first Phase Interpolator (PI) of the plurality of PIs, at least one of the plurality of input-side programmable delay elements, the external delay element, at least one sampler, the first and second external multiplexers, J) programming the input-side programmable delay element using the Digital Delay Control Code (DDCC), K) calibrating the external delay element until the given predetermined criterion based on the early-late detection method is met, L) upon satisfaction of the predetermined criterion, retaining a corresponding Digital External Delay Control Code (DEDCC) in the external delay element for subsequent use and M) assigning at least one value of a Binary Control Code (BCC) to select a unique phase in a given quadrant of a full phase cycle, N) calibrating the input-side programmable delay element until the given predetermined criterion based on the early-late detection method is met, O) upon satisfaction of the predetermined criterion, retaining the corresponding DDCBC in the input-side programmable delay element for subsequent use and P) repeating the steps M-O for each of the remaining unique phases in the inputs to the PI such that the remaining input-side programmable delay elements are each separately calibrated. | 02-25-2016 |
20160065357 | MULTI-LANE N-FACTORIAL (N!) AND OTHER MULTI-WIRE COMMUNICATION SYSTEMS - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multilane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link. | 03-03-2016 |
20160087787 | SAMPLE RATE CONVERTER AND METHOD OF CONVERTING SAMPLE RATE - A sample rate converter and a method of converting a sample rate are disclosed herein. The sample rate converter includes a data delay unit, a clock rate conversion unit, a Lagrange polynomial filter unit, a resample position calculation unit, and a resample position compensation unit. The data delay unit delays signals in response to an input clock signal. The clock rate conversion unit converts the sample rate of the signals. The Lagrange polynomial filter unit performs a filtering function on the signals whose rate has been converted. The resample position calculation unit outputs the value (Dint, dfrac) of the resample position of the signals based on a set resample ratio value. The resample position compensation unit corrects the error value of the signals by applying the value (Dint, dfrac) to the signals, and outputs a final signal. | 03-24-2016 |
20160099803 | TIME SIGNAL VERIFICATION AND DISTRIBUTION - The time signal verification and distribution device disclosed herein verifies and distributes a time signal to consuming devices. The device determines a time quality status of a first and second time signal, calculates a difference between a first and a second time signal, and compares the difference to a predetermined threshold. Based on the time quality status and the comparison, the time signal verification and distribution device distributes a time signal to a plurality of time signal consuming devices. Exceeding the predetermined threshold may indicate a spoofing attack or other problem with the time signals. | 04-07-2016 |
20160112186 | Frequency Planning for Digital Power Amplifier - Systems and techniques relating to wireless communication devices and digital power amplifiers include, according to an aspect, an apparatus including: processor electronics; transceiver electronics coupled with the processor electronics, the transceiver electronics including modulation circuitry and a digital power amplifier coupled with the modulation circuitry; a clock source coupled with the transceiver electronics to provide a clock signal from the clock source to the digital power amplifier at a sampling clock frequency; a local oscillator coupled with the transceiver electronics to provide a local oscillator signal from the local oscillator to the modulation circuitry at a local oscillator frequency; and one or more antennas coupled with the digital power amplifier in the transceiver electronics; wherein the local oscillator frequency is an integer multiple of the sampling clock frequency; and wherein a parasitic frequency response of circuitry in the transceiver electronics acts as an implicit out-of-band filter to remove alias signals. | 04-21-2016 |
20160119117 | OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER - A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter. | 04-28-2016 |
20160149694 | SIGNAL PROCESSING APPARATUS, SIGNAL RECOVERY APPARATUS, SIGNAL PROCESSING METHOD, AND SIGNAL RECOVERY METHOD - A method and apparatus for processing a signal, wherein the apparatus identifies a sample interval satisfying a predetermined reference using a change in a plurality of samples based on a downsampling, acquires, based a result of the identifying, a feature point of a signal before the downsampling is applied to the signal, and acquires time information corresponding to a position of the feature point in a feature sample interval including the feature point is provided. | 05-26-2016 |
20160149695 | OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER - A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter. | 05-26-2016 |
20160164661 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA - A data transceiving system, comprising: a data receiving apparatus, comprising a data receiving side command pin and at least one data receiving side data pin; a data transmitting apparatus, comprising a data transmitting side command pin and at least one data transmitting side data pin. The data receiving apparatus transmits a first command signal from the data receiving side command pin to the data transmitting side command pin, and the data transmitting apparatus transmits a first response signal from the data transmitting side command pin to the data receiving side command pin. The data transmitting apparatus transmits data from the data transmitting side data pin to the data receiving side data pin. The data transmitting apparatus transmits a first data sampling clock signal from the data transmitting side command pin to the data receiving side command pin, to sample the data. | 06-09-2016 |
20160164668 | MULTI-RATE TRANSCEIVER CIRCUITRY - Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit. | 06-09-2016 |
20160173271 | Sampling Clock Adjustment for an Analog to Digital Converter of a Receiver | 06-16-2016 |
20160380755 | METHOD TO ENHANCE MIPI D-PHY LINK RATE WITH MINIMAL PHY CHANGES AND NO PROTOCOL CHANGES - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods. | 12-29-2016 |
20160380756 | Real Time Subsample Time Resolution Signal Alignment in Time Domain - System and method for subsample time resolution signal alignment. First and second signals may be aligned by iteratively performing the following until a termination condition is met: current samples of the first and second signals may be acquired, a delayed copy of the current samples of the first signal may be generated and subtracted from the current samples of the first signal to generate a third signal, a delayed copy of the current samples of the second signal may be generated with a current subsample delay and subtracted from the current samples of the first signal to generate a fourth signal, and an alignment error may be generated based on the third and fourth signals and the current subsample may be delay adjusted accordingly. The iteratively adjusting may generate a subsample resolution delay aligning the second signal to the first signal. Subsequent samples the first signal and the second signal may be aligned and output per the subsample resolution delay. | 12-29-2016 |
20180026779 | APPARATUS AND METHOD FOR CENTERING CLOCK SIGNAL IN CUMULATIVE DATA EYE OF PARALLEL DATA IN CLOCK FORWARDED LINKS | 01-25-2018 |
20180026781 | DATA HANDOFF BETWEEN RANDOMIZED CLOCK DOMAIN TO FIXED CLOCK DOMAIN | 01-25-2018 |
20190149314 | CLOCK AND DATA RECOVERY FOR PULSE BASED MULTI-WIRE LINK | 05-16-2019 |