Class / Patent application number | Description | Number of patent applications / Date published |
375358000 | Feedback, receiver to transmitter | 16 |
20080226004 | METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES - A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices. The system controller further includes a detector for processing the first and second clock signals to detect a phase difference therebetween; and a synchronization controller for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference detected by the detector. | 09-18-2008 |
20080226005 | APPARATUS AND METHOD FOR SYNCHRONIZING A CHANNEL CARD IN A MOBILE COMMUNICATION SYSTEM - An apparatus and a method for synchronization in a channel card in a mobile communication system are provided. A channel card for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a mobile communication system includes the DSP modem for sending a reference signal, informing of a start of a transmission, to a Field-Programmable Gate Array (FPGA) modem, and the FPGA modem for comparing a reception time of the reference signal with a Global Positioning System (GPS) timer, for recording a GPS timer value corresponding to a start point based on the comparison, and for sending to the DSP modem the recorded GPS timer value corresponding to the start point at a preset GPS timer reference time. | 09-18-2008 |
20080292039 | Method for Synchronising Clock Pulse Devices - The invention relates to a method for synchronizing clock pulse devices. According to this method, an emission unit emits at least one narrow-band distant signal; clock pulse devices of receiving units are pre-synchronized by coupling the same to the source of one such distant signal; the emission unit emits a wide-band measured signal after a defined waiting time, and the receiving units receive said signal; and the receiving units correlate the wide-band measuring signal with a homogeneously modulated comparison signal, the receiving time of the wide-band measuring signal and the deviation in the synchronization of the clock pulse devices being determined and compensated on the basis of the correlation result. | 11-27-2008 |
20090074122 | DATA TRANSMISSION METHOD AND SYSTEM - A data transmission method for a data transmission system including a first device and a second device is disclosed. The method comprises the steps of transmitting a clock signal to synchronize the first device and the second device; transmitting a mode signal from the first device to the second device, wherein the mode signal indicates a transmission mode between the first device and the second device; and transmitting a serial data between the first device and the second device based on the clock signal, wherein the length of the serial data is determined based on the transmission mode. | 03-19-2009 |
20090168938 | COMMUNICATION SYSTEM FOR CONNECTING SYNCHRONOUS DEVICES THAT ARE UNCORRELATED IN TIME - A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices. | 07-02-2009 |
20090238319 | MODULAR, PORTABLE DATA PROCESSING TERMINAL FOR USE IN A RADIO FREQUENCY COMMUNICATION NETWORK - Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or “sleeping” states, a series of communication protocols provide for channel access to the communication network. The disclosed modular design also provides for automatic selection from a variety of available built-in and externally mounted antennas based on the particular type of radio transceiver(s) selected. | 09-24-2009 |
20090296865 | METHODS AND APPARATUS FOR PROVIDING SYNCHRONIZATION IN A MULTI-CHANNEL COMMUNICATION SYSTEM - A multi-channel processing module is arranged in series with multiple channels of a communication system. The processing module synchronizes downstream symbols among the channels, and synchronizes downstream symbols for at least a given one of the channels with upstream symbols for that channel. The synchronization of downstream symbols among the channels and the synchronization of downstream symbols for at least the given channel with upstream symbols for that channel are collectively achieved by adjusting downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths in the multi-channel processing module. The channels may comprise respective subscriber lines of a DSL communication system. | 12-03-2009 |
20100020908 | PHY Clock Synchronization In A BPL Network - A method and a communication modem for broadband communication over power transmission lines. The modem includes a coarse level synchronization mapping unit which maintains a regularly updated coarse level clock synchronization map of neighboring communication units with which it is likely to exchange communications; and a second level synchronization unit which utilizes session handshakes and session data capacity to increase the synchronization level with a neighboring communication unit to allow a communication session to be held at a higher modulation level than the coarse level synchronization is able to support. | 01-28-2010 |
20100067631 | SYSTEM AND METHOD FOR USING A COMPUTER AS A BRIDGE FOR DATA SYNCHRONIZATION BETWEEN A CELLULAR DEVICE AND A COMPUTER NETWORK - A method for data bridging and synchronization between a mobile device and a computer network, using a computer connected to the mobile device over a short range communication channel. | 03-18-2010 |
20110286561 | CLOCK-OUT AMPLITUDE CALIBRATION SCHEME TO ENSURE SINE-WAVE CLOCK-OUT SIGNAL - A clock generator includes, in part, a buffer, a peak detector and a control logic. The buffer generates a clock output signal in response to receiving a clock signal and a feedback signal that controls the gain of the buffer. If the peak detector detects that the amplitude of the output signal is higher than the upper bound of the predefined range, the gain value applied to the variable buffer is decreased. If the peak detector detects that the amplitude of the output signal is lower than the lower bound of the predefined range, the gain value applied to the variable buffer to increased. If the peak detector detects that the amplitude of the output signal is within the predefined range, no change is made to the gain value applied to the variable buffer. The control logic generates the feedback signal in response to the peak detector's output signal. | 11-24-2011 |
20140093022 | Method, System, and Apparatus for Dynamically Adjusting Link - A method, a system, and an apparatus for dynamically adjusting a link, where the method includes: determining, by a transmitting end, link adjustment information according to the data traffic change when detecting a change of data traffic, where the link adjustment information contains the number of required working links; and adjusting, by the transmitting end, the number of working links on an interface of the transmitting end according to the determined link adjustment information, and sending a configuration request to a receiving end, where the configuration request includes the link adjustment information; and after receiving the configuration request, adjusting, by the receiving end, the number of working links on an interface of the receiving end according to the configuration request. In the embodiments of the present invention, data transmission on an original working link is not affected, thereby saving bandwidth and power consumption. | 04-03-2014 |
20140105340 | MULTIPLE CHANNEL DISTRIBUTED SYSTEM AND METHOD - A complex acquisition system and method for synchronizing components thereof. The complex acquisition system further including a master acquisition module. The master acquisition module further including an analog to digital acquisition signal generator for generating an analog to digital acquisition signal, a memory acquisition signal generator for generating a memory acquisition signal, a delay calibration signal for generating a delay calibration signal, a step source signal generator for generating a step source signal, and a synchronization module. The complex acquisition system further includes a plurality of slave acquisition modules, each also including a synchronization module. The complex acquisition system additionally includes a distribution system for distributing each of the analog to digital acquisition signal, memory acquisition signal, delay calibration signal and step source signal to each of the synchronization modules in the master and plurality of slave acquisition modules. | 04-17-2014 |
20140362960 | RECEIVER, METHOD OF CALCULATING TIME DIFFERENCE, AND PROGRAM - There is provided a receiver including a first delay time calculating unit configured to calculate a first delay time indicating a time lag between transmission of a transmission signal by a transmitter and reception of the transmission signal by the receiver, a second delay time calculating unit configured to calculate a second delay time indicating a time lag between transmission of a response signal by the receiver and reception of the response signal by the transmitter, and a time difference calculating unit configured to calculate a time difference between a time of a clock in the transmitter and a time of a clock in the receiver. | 12-11-2014 |
20150318979 | SYMBOL CLOCK RECOVERY CIRCUIT - A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal. | 11-05-2015 |
20150372805 | ASYNCHRONOUS PULSE MODULATION FOR THRESHOLD-BASED SIGNAL CODING - A method of signal processing includes comparing an input signal with one or more positive threshold values and one or more negative threshold values. The method also includes generating an output signal based on the comparison of the input signal with the positive threshold(s) and negative threshold(s). The method further includes feeding the output signal back into a decaying reconstruction filter to create a reconstructed signal and combining the reconstructed signal with the input signal. | 12-24-2015 |
20160065435 | COMMUNICATION DEVICE AND COMMUNICATION SYSTEM - According to one embodiment, a communication device includes a clock to measure time, communication circuitry and processing circuitry. The communication circuitry transmits a request signal to the other communication device in a certain cycle, and receives a response signal transmitted in response to the request signal, from the other communication device. The processing circuitry changes a transmission timing of the request signal; compares first round-trip delay time with second round-trip delay time; and if a result of comparison shows that the second round-trip delay time is shorter than the first round-trip delay time, adjusts the time measured by the clock using a transmission time point of the second request signal and the reception time point of the second request signal in the other communication device, and the transmission time point of the second response signal from the other communication device and a reception time point of the second response signal. | 03-03-2016 |