Entries |
Document | Title | Date |
20080226006 | DATA PLAYER AND DATA PLAY METHOD - A synchronous pattern detection section checks coincidence between a predetermined reference synchronous pattern and a bit pattern included in a data stream. Each time a bit pattern which coincides with the reference synchronous pattern is detected, the synchronous pattern detection section extracts a frame length of a data frame corresponding to the bit pattern which is detected, and stores the extracted frame length in a storage section. Each time a bit pattern which coincides with the reference synchronous pattern is detected in the synchronous pattern detection section, a synchronization determination section determines whether or not the bit pattern detected by the synchronous pattern detection section is a correct synchronous pattern, based on a plurality of frame lengths stored in the storage section and a bit length of a data stream which is obtained after detection of the bit pattern. With this structure, a synchronous pattern included in the data stream can be detected with higher precision. | 09-18-2008 |
20080260084 | RADIO COMMUNICATION APPARATUS AND SYSTEM - A radio communication apparatus connected to a device including a digital signal processing unit generating a clock signal, the apparatus includes an acquisition unit acquiring frequency information concerning the clock signal from the digital signal processing unit, a first measurement unit measuring a signal power in a first frequency band, a comparison unit comparing the signal power with a threshold, a first selection unit selecting, from the first frequency band, a second frequency band necessary for data communication, a bandwidth of the first frequency band whose signal power is lower than the threshold being more than a bandwidth of the second frequency band, a second selection unit selecting an optimum communication scheme from a plurality of communication schemes of the data communication according to the frequency information, and a communication unit using the optimum communication scheme to perform the data communication in the second frequency band. | 10-23-2008 |
20080273641 | OFDM-BASED DEVICE AND METHOD FOR PERFORMING SYNCHRONIZATION - An OFDM-based device and method for synchronizing to a serving base station utilizes at least one of three frequency offset estimation techniques, which are each based on preambles, cyclic prefixes or pilot subcarriers. The device and method also utilizes a base station selecting scheme, a false detection scheme, a blocker detection scheme to provide robust synchronization. | 11-06-2008 |
20080298526 | Code Controller - A code controller that configures a code state at a substantially constant and low storage volume, and furthermore at a substantially constant computational processing amount, regardless of which state position a desired code state is present in within the state area of the code states. | 12-04-2008 |
20080304607 | System, Apparatus, and Method for a Robust Synchronization Scheme for Digital Communication Systems - A synchronization sequence (preamble) that is known to the receiver forms as an integral part of packet-based digital communication systems. The first operation in such digital communication systems is the detection of the beginning of a valid signal (packet). The present invention provides a system, apparatus, and method for a scheme to robustly detect the preamble. The scheme of the present invention has the following advantages: it is robust to noise and interference, it provides the frequency error directly without any additional computation, it provides information that is necessary to position the FFT window for an OFDM based modulation, it provides a real part of the peak that can be used for frame synchronization, and finally, it provides the peak for burst detection purposes. | 12-11-2008 |
20090010370 | Digital Broadcast Demodulator and Digital Broadcast Demodulation Method for Suppressing Degradation of Reception Characteristics - A digital broadcast demodulator receives a tuner signal output from a tuner and carries out demodulation processing on the tuner signal by using an internal clock signal that is synchronized with a reference signal. The digital broadcast demodulator has an internal clock-signal generator and an internal clock frequency controller. The internal clock-signal generator generates the internal clock signal, and the internal clock frequency controller controls a frequency of the internal clock signal in accordance with a reception channel. | 01-08-2009 |
20090041171 | ACCELERATED PROCESSING IN SUBSET OF HARDWARE ENGINES IN WIRELESS RECEIVER - Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow. | 02-12-2009 |
20090052600 | CLOCK AND DATA RECOVERY CIRCUITS - A data communication system comprising a first transmitter set configured to transmit a first output based on a first signal, the first output including one of a training pattern and a first data, the training pattern and the first data including clock information, a second transmitter set configured to transmit a second output based on the first signal, the second output including one of the training pattern and a second data, a first receiver set configured to generate a first received data based on the first output, a second receiver set configured to generate a second received data based on the second output, a clock and data recovery (CDR) circuit configured to extract the clock information based on the first signal and the first received data and provide a second signal indicating whether a frequency in-lock status is reached, a phase control circuit in the second receiver set, the phase control circuit being configured to detect a phase difference between the first received data and the second received data and provide a third signal indicating whether a phase in-lock status is reached, and a detector configured to generate the first signal based on the second signal and the third signal. | 02-26-2009 |
20090086868 | CLOCK DATA RECOVERY CIRCUIT - A clock data recovery circuit which reproduces clock contained in data sequence from data sequence which is serially input includes a digital control oscillator outputting reproduced clock whose frequency is controlled according to a control signal. A phase comparator compares a phase of the data sequence and a phase of the reproduced clock. A digital control circuit produces the control signal in accordance with an output of the phase comparator, first control information indicating a first period for which the frequency of the reproduced clock is changed, and a second control information indicating a number of steps by which the frequency of the reproduced clock is changed. | 04-02-2009 |
20090147899 | CLOCK CALIBRATION IN SLEEP MODE - In one embodiment, an improvement is described for synchronization between devices in, e.g., a wireless network, wherein at least one device includes both a slow clock and a fast clock for different modes of operation. The fast clock for an active mode of operation is calibrated after a sleep mode of operation during which the slow clock is employed for device timing. Calibration employs a filter-based technique. Counts for the slow clock and for the fast clock are measured over a first interval, and the number of slow-clock counts is measured over a second interval. An estimate for the number of fast counts over the second interval is generated, filtered to reduce noise and error effects, and then employed to update the fast clock in the active mode of operation. | 06-11-2009 |
20090154625 | JOINT ESTIMATION APPARATUS OF CHANNEL AND FREQUENCY OFFSET BASED ON MULTIBAND-ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING AND THEREOF - The present invention relates, in general, to a joint channel and frequency offset estimation apparatus and method based on a multi-band-orthogonal frequency division multiplexing system, and, more particularly, to a joint channel and frequency offset estimation apparatus and method based on an MB-OFDM system, which uses low-rank LMMSE channel estimation, in which a low-rank is applied to the MB-OFDM system, thus decreasing complexity, and adds a simple structure using the autocorrelation characteristics of an estimated channel, thus joining channel estimation to frequency offset estimation at low complexity. | 06-18-2009 |
20090168939 | HARDWARE SYNCHRONIZER FOR 802.15.4 RADIO TO MINIMIZE PROCESSING POWER CONSUMPTION - A method is disclosed for controlling the operation of a low power radio platform that realizes the physical layer (PHY) with a software portion and an analog front end, the analog front end disposed between the DSP and an antenna, and realizes the MAC layer with a microcontroller unit (MCU). The DSP, analog front end and MCU are maintained in a low power mode of operation when not in data communication. When data communication is initiated, a hardware controller controls at least one hardware interface disposed between the DSP and the analog front end to initiate multiple time based tasks to transfer data to and from a buffer. During the execution of these tasks, the controller causes a task in the DSP to be initiated for processing of data in the buffers and, upon completion of at least one of the tasks, notifying the MCU of such. The controller controls the hardware interface to terminate operation when predetermined time based events have occurred. The MCU in at least one mode of operation thereof is operable to initiate the operation of the hardware controller and then convert to a low power mode of operation to await notification. | 07-02-2009 |
20090257539 | TRANSMISSION APPARATUS AND METHOD, RECEPTION APPARATUS AND METHOD, PROGRAM, AND TRANSMISSION AND RECEPTION SYSTEM AND METHOD - Disclosed herein is a transmission apparatus, including: a control section configured to control the timing at which actual data from a data source is to be transmitted to a reception apparatus; and a transmission section configured to produce a control signal representative of the contents of the control of the control section, transmit the control signal to the reception apparatus through a first signal line, receive the actual data from the data source under the control of the control section and transmit the received actual data to the reception apparatus through a second signal line. | 10-15-2009 |
20090279653 | Clock and Data Recovery Loop with ISI Pattern-Weighted Early-Late Phase Detection - An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I and Q clocks, creating digital I-bit and Q-bit values, respectively. The I-bit values and Q-bit values are segmented into n-bit digital words. In response to analyzing the I-bit and Q-bit values, I clock phase corrections are identified. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. A phase error signal is generated by averaging the weighted I-bit values for each n-bit digital word, and I clock is modified in phase. | 11-12-2009 |
20090290669 | PHASE DIFFERENCE DETECTION DEVICE AND ROTATION POSITION DETECTION DEVICE - A phase difference detection device able to detect a phase with a high precision is provided. A phase difference detection device | 11-26-2009 |
20090304136 | SYNC DETECTOR AND COMMUNICATION APPARATUS SYNTHESIZING CORRELATION VALUES - A sync detector includes a correlation computing unit configured to receive signal values corresponding to respective sample points and to compute auto-correlation of the received signal values between sample points of interest and sample points that are situated at a distance equal to a constant number of sample points from the sample points of interest, a correlation value synthesizing unit configured to receive auto-correlation values corresponding to respective sample points obtained by the correlation computing unit and to synthesize the auto-correlation values with respect to at least two sample points among sample points that are spaced apart by the constant number of sample points thereby to compute a synthesized correlation value, and a peak-point detecting unit configured to detect a position of a sample point corresponding to a largest synthesized correlation value among synthesized correlation values corresponding to respective sample points obtained by the correlation value synthesizing unit. | 12-10-2009 |
20090310726 | METHOD FOR RECEIVING AND PROCESSING FRAMES AND A DEVICE HAVING FRAME RECEIVING AND PROCESSING CAPABILITIES - A device having frame receiving and processing capabilities and a method for receiving and processing frames. The method includes: receiving a frame; associating a frame timestamp with the frame; storing the frame and the associated timestamp at a certain buffer out of a group of buffers; generating a valid timing information frame indicator if the received frame is a valid timing information frame; and storing the valid timing information frame indicator at a certain buffer descriptor associated with the certain buffer. | 12-17-2009 |
20090316846 | METHOD AND SYSTEM FOR 60 GHZ WIRELESS CLOCK DISTRIBUTION - Aspects of a method and system for 60 GHz wireless clock distribution may include configuring a microwave communication link established between a first chip and a second chip via a wireline communication bus. The configuration may comprise adjusting beamforming parameters of a first antenna array communicatively coupled to the first chip, and of a second antenna array communicatively coupled to the second chip. The first chip and the second chip may communicate a clock signal via said microwave communication link. The microwave communication link may be routed via one or more relay chips, when the first chip and the second chip cannot directly communicate. Control data may be transferred between the first chip, the second chip, and/or the one or more relay chips, which may comprise one or more antennas. The relay chips may be dedicated relay ICs or multi-purpose transmitter/receivers. | 12-24-2009 |
20100091925 | Triple Loop Clock and Data Recovery (CDR) - In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream. | 04-15-2010 |
20100104056 | Controlling activation of electronic circuitry of data ports of a communication system - An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data. | 04-29-2010 |
20100195776 | Systems and Methods for Synchronous, Retimed Analog to Digital Conversion - Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch. | 08-05-2010 |
20100195777 | METHOD AND APPARATUS FOR IMPROVING LINEARITY IN CLOCK AND DATA RECOVERY SYSTEMS - Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal. | 08-05-2010 |
20100215134 | CLOCK RECOVERY CIRCUIT AND CLOCK DATA RECOVERY CIRCUIT HAVING THE SAME - A clock recovery circuit includes a frequency detection module and a correction module. The frequency detection module detects frequency offset information between a received signal and a reference clock according to a phase difference between the received signal on which timing information for reproducing the received signal is superimposed and a recovery clock. The correction module corrects a phase difference between the received signal and the recovery clock according to the frequency offset information detected by the frequency detection module. | 08-26-2010 |
20100226466 | System and Method for Transmitting Data Using Quantized Channel Rates - A quantized channel rate and corresponding rate multiplier is determined on a transmitter-side of a communication system based on a measured minimum required bandwidth. In certain embodiments, the quantized data rate may be an integer multiple of the system's reference clock. The determined rate multiplier is then transmitted to the receiver-side at a default data rate prior to or near the beginning of a data transmission session, such as upon initialization. Prior to transmission, the data stream may be padded with some determined amount of null data such that the actual transmitted data rate is approximately equal to the quantized channel rate, and the receiver-side can readily recover the data clock using its known reference clock and the previously-provided rate multiplier. | 09-09-2010 |
20100226467 | FRAME NUMBER DETECTING DEVICE - A frame number detecting device includes: a symbol counter that receives a received signal including frames each of which is formed of a predetermined number of symbols, and outputs a count value as a symbol number for each of the symbols by incrementing the count value by one every time one symbol is inputted, each of the frames including a frame synchronization signal including a part obtained by shifting a frame synchronization signal of a different frame on a symbol-by-symbol basis according to a predetermined rule; a sequence storage that stores a synchronization sequence based on at least one of the frame synchronization signals included in the received signal, and a pattern matching unit that performs pattern matching between the synchronization sequence stored in the sequence storage and the received signal. | 09-09-2010 |
20100246736 | CLOCK RECOVERY FROM DATA STREAMS CONTAINING EMBEDDED REFERENCE CLOCK VALUES - A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means. | 09-30-2010 |
20100246737 | CLOCK CHANGE DEVICE AND CLOCK CHANGE METHOD - A clock change method includes: converting the serial data synchronized to a first clock into parallel data; latching the serial-to-parallel converted data into a designated data storing circuit with a latch timing that occurs once in every a number of clock cycles of a second clock; and converting the latched parallel data into the serial data synchronized to the second clock, and wherein: each time a packet of serial data synchronized to the first clock is received, a timing adjustment is performed to adjust the latch timing so that the latch timing occurs a predetermined time after occurrence of a conversion timing for converting the serial data synchronized to the first clock into the parallel data. | 09-30-2010 |
20110026655 | FREQUENCY MODULATION OF CLOCKS FOR EMI REDUCTION - In an electronic system, a frequency modulator manages clock signals for electromagnetic interference (EMI) reduction. The illustrative frequency modulator comprises a core oscillator, and a clock divider coupled to the core oscillator that modulates frequency of the core oscillator and deterministically spreads clock spectral components of a digital clock signal whereby electromagnetic interference (EMI) is reduced. The frequency modulator further comprises a circuit coupled to the clock divider that receives the digital clock signal, combines the digital clock signal with a data bitstream for transmission across an isolation barrier, and resynchronizes to the digital clock signal. | 02-03-2011 |
20110085630 | TCP FLOW CLOCK EXTRACTION - A packet trace is received. The packet trace is transformed into a sequence of pulse signals in a temporal domain. The sequence of pulse signals in the temporal domain is transformed into a sequence of pulse signals in a frequency domain. Peaks are detected within relevant frequency bands in the sequence of pulse signals in the frequency domain. A fundamental frequency is identified within the peaks. The fundamental frequency, which represents the TCP flow clock, is returned. | 04-14-2011 |
20110096883 | SYMBOL SYNCHRONIZATION APPARATUS AND METHOD OF PASSIVE RFID READER - Provided is a symbol synchronization apparatus and method of a passive REID reader. The symbol synchronization apparatus includes: an edge clock detector generating edge clocks by detecting phase inversion positions of a received signal; a preamble detector detecting a preamble section by analyzing the generation times of the edge clocks; a symbol decision time extractor extracting a symbol decision time by averaging distances between the edge clocks consecutively generated in the preamble section, when the preamble section is detected; and a symbol decider deciding a symbol by analyzing the magnitude of the received signal, when the time reaches the symbol decision time. | 04-28-2011 |
20110103533 | Training a Data Path for Parallel Data Transfer - A system and method for training a data path for parallel data transfer are presented. A first part of the method includes determining a delay setting for each coupling of a plurality of parallel couplings between a first device and a second device. The delay setting for each coupling may substantially align reception of signals transmitted from the first device to the second device on each coupling with a system clock. A second part of the method includes determining the alignment of the plurality of parallel couplings relative to each other. A timing adjustment for one or more of the plurality of parallel couplings may then be determined, whereby after the timing adjustment, signals transmitted from the first device to the second device on the plurality of couplings are received by the second device in alignment with each other. | 05-05-2011 |
20110135048 | JOINT FREQUENCY AND UNIQUE WORD DETECTION - Systems, devices, processors, and methods are described for joint detection of frequency and unique word (UW) location(s) for burst transmissions. Embodiments receive a wireless signal. Frequency detection is performed, resulting in multiple possible frequency correlation peaks. A subset of the correlation peaks are each used to perform trial frequency corrections, thereby generating a set of trial sequences. A UW correlation is performed on each of the trial sequences to generate a maximum UW correlation value for each trial sequence. The UW correlation value and the frequency correlation peak value are weighted and combined to generate a joint detection correlation value. The trial sequence having largest joint detection correlation value may indicate the correct transmission frequency and UW location. The jointly detected information may then be used to identify the frequency and start time of the burst transmission, which may then be demodulated, decoded, etc. to recover its payload data. | 06-09-2011 |
20110228886 | FAST LINK RE-SYNCHRONIZATION FOR TIME-SLICED OFDM SIGNALS - Methods having corresponding apparatus and computer-readable media comprise: receiving an estimated frame index, and an estimated symbol index, for a time-sliced OFDM signal; identifying a plurality of possible frame indexes, and a plurality of possible symbol indexes, based on the estimated frame index and the estimated symbol index; selecting a plurality of possible forward error correction code offsets based on the possible frame indexes and the possible symbol indexes; and selecting one of the possible frame indexes, and one of the possible symbol indexes, based on the possible forward error correction code offsets and a SYNC byte of the time-sliced OFDM signal. | 09-22-2011 |
20110228887 | LINEAR PHASE DETECTOR AND CLOCK/DATA RECOVERY CIRCUIT THEREOF - A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter. | 09-22-2011 |
20110261915 | System and method for self-correcting the multiphase clock - A system for self-correcting the multiphase clock includes a transmitter, a receiver, a random code generator and a controller. The random code generator generates a random code stream, the random code stream is transformed to the high-speed serial data by the transmitter, the high-speed serial data are sent into the receiver and transformed to the parallel data by the receiver, the parallel data are sent into the controller, the controller stores the random code stream and detects the probability of the bit error of the parallel data output by the receiver. According to the test result of the bit error, the controller generates a phase adjustment control signal for adjusting the phase uniformity of the multiphase clock. Also, a method for self-correcting the phase uniformity of the multiphase clock of the present invention effectively makes up the sampling bit errors caused by the phase nonuniformity of the multiphase clock. | 10-27-2011 |
20110280355 | METHOD AND APPARATUS FOR IMPLEMENTING VARIABLE SYMBOL RATE - A method for implementing variable symbol rate, presetting counters M and N, and M= | 11-17-2011 |
20110311010 | DEVICE AND METHOD FOR NRZ CDR CALIBRATION - The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal. | 12-22-2011 |
20120008724 | NICAM DECODER WITH OUTPUT RESAMPLER - A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions. | 01-12-2012 |
20120014488 | METHOD AND SYSTEM FOR MANAGING WIRELESS LINKS IN A COMMUNICATION NETWORK - A method of operating a communication system comprises establishing a wireless device release time interval for a wireless device release timer at an access node upon establishing an initial network connection between a wireless device and the access node. An initial synchronization process is performed between the wireless device and the access node. The method continues with the access node sending an unsolicited synchronization message to the wireless device and starting the wireless device release timer. A second synchronization process is performed and upon successful completion of the second synchronization process, a success status synchronization response message is sent by the access node to the wireless device. The access node receives a synchronization confirmation message from the wireless device that comprises an identifier corresponding to the identity of the wireless device and upon receiving the confirmation message, the access node cancels the wireless device release timer. | 01-19-2012 |
20120027147 | Frame and Carrier Synchronization for Unbursted Packetized Transmissions Using Constant-Amplitude Continuous-Phase Frequency-Modulation - A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data. | 02-02-2012 |
20120027148 | SYSTEM AND METHOD FOR SYNCHRONIZATION TRACKING IN AN IN-BAND MODEM - Processing the synchronization of an inband modem to detect sample slip conditions is disclosed. Decision logic reliably detects the sample slip condition while minimizing the number of false alarms. | 02-02-2012 |
20120163522 | PLATFORM RFI MITIGATION - In some embodiments, SSC (e.g., discrete SSC) profiles with intentional and controlled gaps may be used to mitigate interference for platform radios. Targeted frequency gaps are placed in spectrum of spread clocks and clock-derived signals where they may otherwise result in problematic RFI to a platform radio. | 06-28-2012 |
20120170698 | DESIGN STRUCTURE FOR WINDOW COMPARATOR CIRCUIT FOR CLOCK DATA RECOVERY FROM BIPOLAR RZ DATA - A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data. | 07-05-2012 |
20120177159 | Full Digital Bang Bang Frequency Detector with No Data Pattern Dependency - A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data. | 07-12-2012 |
20120201337 | AM-PM SYNCHRONIZATION UNIT - One embodiment of the present invention relates to a method and apparatus for performing both phase modulation (PM) and amplitude modulation (AM) downstream of a controlled oscillator (e.g., by providing a baseband signal having no phase modulation to a controlled oscillator and performing phase modulation on a high frequency RF signal output from the oscillator), wherein the amplitude modulation is synchronized with the phase modulation. In one particular embodiment, the method and apparatus synchronize modulation of AM and PM signal paths in a manner that provides a polar modulated signal having an amplitude of zero at a symbol boundary (e.g., a transition between different symbols) having a phase of zero (e.g., a phase that crosses through a zero crossing point). | 08-09-2012 |
20120213318 | Network Synchronized Time Base Timer - A system and method are provided for synchronizing a programmable timer time base and external time signal. The method either accepts or supplies an external time signal (e.g., IEEE 1588) at an external interface, links a synchronized time base to the external time signal, and clocks a channel time base with the synchronized time base. Then, a timer channel can be used to perform programmable timer functions in response to the channel time base. Some programmable timer functions include input capture, output compare, quadrature decoding, pulse measurement, frequency measurement, and pulse width modulation (PWM) functions. In one aspect, accepting the external time signal at the external interface includes detecting a packet with a time value. In another aspect, the method uses the channel to detect an event at a channel external interface, and compares the channel time base counter value with an expected value to modify the synchronized time base. | 08-23-2012 |
20120257699 | ADJUSTMENT OF CLOCK SIGNALS REGENERATED FROM A DATA STREAM - Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time. | 10-11-2012 |
20120281795 | UNIVERSAL TIMING RECOVERY CIRCUIT - A timing recovery system that provides a timing estimate between a transmitter clock and a receiver clock. The system includes a down-converter that converts a received intermediate frequency signal in the receiver and down-converts, using Fs/4 down-conversion, the received signal into baseband in-phase and quadrature phase signals. The baseband in-phase and quadrature phase signals are sent to a direct down-converter that frequency shifts the in-phase and quadrature phase. The frequency-shifted in-phase and quadrature phase baseband signals are then low-pass filtered in order to isolate the frequency components of interest, reduce noise, and remove zeros that are artifacts of the Fs/4 down-conversion. The signals are sent to a square-law non-linearity circuit that provides squaring non-linearity to generate non-linear in-phase and quadrature phase signals. The non-linear in-phase and quadrature phase signals are sent to a single-pole, low-pass post-filter circuit that generates the timing estimate. | 11-08-2012 |
20120281796 | SNAPSHOT PROCESSING OF TIMING DATA - A method for providing timing recovery from a received digital data stream where the digital data stream is a series of consecutive data samples. The method separates the data stream into a series of consecutive observation periods where each observation period includes the same number of consecutive data samples. The method also includes identifying a series of consecutive timing recovery data samples in each observation period where the timing recovery data samples are used for timing recovery and other data samples in the observation period are not used for timing recovery, and where the number of data samples used for timing recovery in each observation period is less than the number of data samples that are not used for timing recovery in the observation period. The method then uses the timing recovery data samples for timing recovery in each observation period. | 11-08-2012 |
20130077723 | CLOCK-DATA RECOVERY WITH NON-ZERO h(-1) TARGET - In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample. | 03-28-2013 |
20130107997 | CLOCK DATA RECOVERY CIRCUIT | 05-02-2013 |
20130170591 | CLOCK PHASE ADJUSTMENT FOR A LOW-LATENCY FIFO - In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a phase relationship between the first clock and the second clock. Then, the phase-adjustment circuit in the clock-adjustment circuit adjusts a phase of the first clock relative to the second clock if the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that transfers data from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer. | 07-04-2013 |
20130251083 | Synchronization Between Devices - The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks. | 09-26-2013 |
20140003565 | APPARATUS AND METHOD FOR CHANGING A CLOCK RATE FOR TRANSMISSION DATA | 01-02-2014 |
20140270028 | SPDIF Clock and Data Recovery With Sample Rate Converter - A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value. | 09-18-2014 |
20140301514 | SIGNAL DELAY ESTIMATOR WITH ABSOLUTE DELAY AMOUNT AND DIRECTION ESTIMATION - A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively. | 10-09-2014 |
20140328442 | A Self-Synchronizing Probe Sequence - A method comprising modulating a plurality of synchronized signals by an orthogonal probe sequence (OPS) to generate a plurality of modulated synchronized signals, wherein the OPS comprises a zero element (0-element) column that indicates a start or an end of the OPS, and concurrently transmitting, using one or more transmitters, the plurality of modulated synchronized signals over a duration of a number of discrete multi-tone (DMT) symbols, wherein each of the plurality of modulated synchronized signals is intended for one of a plurality of receivers that are remotely coupled to the one or more transmitters via a vectored group of subscriber lines, and wherein the 0-element column causes all of the plurality of modulated synchronized signals to have a zero-amplitude during a first or a last of the DMT symbols. | 11-06-2014 |
20140348280 | CLOCK-EMBEDDED SERIAL DATA TRANSMISSION SYSTEM AND CLOCK RECOVERY METHOD - A clock-embedded serial data transmission system is disclosed. The clock-embedded serial data transmission system includes a combinational logic circuit. The combinational logic circuit includes a clock window generator and a clock generator. The clock window generator is used to generate a first clock window according to two clock phases. The clock generator is coupled to a clock window generator and used to select a periodic data within the first clock window from a serial data signal according to the first clock window and generate a recovery clock accordingly. | 11-27-2014 |
20140362961 | METHOD AND/OR SYSTEM FOR TRANSMITTING AND/OR RECEIVING DATA - Embodiments of a method and/or system of transmitting and/or receiving data is disclosed. | 12-11-2014 |
20150312024 | COMPUTER PROGRAM PRODUCTS, MODULES AND METHOD TO GENERATE INTEGER ZERO AUTOCORRELATION SEQUENCE - The present application provides a method, a module, and a computer program product to generating a zero autocorrelation sequence with all integer values in the sequence. When a user operates communication transmission, the present application is applied to generate a sequence with integer values for synchronization, which is able to make control signal and data transmission synchronized. | 10-29-2015 |
20150326385 | RECEPTION CIRCUIT - First and second determination units determine amplitude levels of an input data signal in synchronization with respective first and second clocks, a phase detector detects a phase relationship between the input data signal and the second clock based on the amplitude levels, and first and second phase adjusters adjust phases of the respective first and second clocks according to a detection result of the phase detector. Further, a correction unit corrects a skew generated between the first and second clocks which arrive at the first and second determination units. A correction amount determination unit determines a correction amount corresponding to the skew in the correction unit according to the detection result in the phase detector when a phase difference set between the first and second clocks is made zero. | 11-12-2015 |
20150341165 | METHOD AND/OR SYSTEM FOR TRANSMITTING AND/OR RECEIVING DATA - Embodiments of a method and/or system of transmitting and/or receiving data is disclosed. | 11-26-2015 |
20160380748 | CLOCK DOMAIN BRIDGE STATIC TIMING ANALYSIS - Examples for performing static timing analysis on clocked circuits are described. An example static timing analysis computing device includes a logic device, and a storage device holding instructions executable by the logic device, the instructions including instructions executable to receive an input representative of one or more delays within a signal path in a cross-domain circuit, the cross-domain circuit configured to transfer data between a first domain having a first clock and a second domain having a second clock asynchronous with the first clock, receive an input representative of a static timing analysis constraint to be met by a signal traveling the signal path in the cross-domain circuit, apply the constraint in a static timing analysis of the signal path in the cross-domain circuit, and output a result based upon applying the static timing analysis constraint. | 12-29-2016 |
20190149154 | DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFACE CIRCUIT | 05-16-2019 |