Class / Patent application number | Description | Number of patent applications / Date published |
380002000 | EQUIPMENT TEST OR MALFUNCTION INDICATION | 15 |
20080240419 | APPARATUS, SYSTEM, AND METHOD FOR TESTING DATA COMPRESSION AND DATA ENCRYPTION CIRCUITRY - An apparatus, system, and method are disclosed for testing data compression and data encryption circuitry. A pattern configuration module generates initial pattern parameters. Holding registers store the initial pattern parameters. A pattern generation module generates patterns for compression/encryption logic. A detection module detects a failure of the compression/encryption logic. The failure of the compression/encryption logic may be a cyclic redundancy check failure of a decompression module and/or a message authentication code failure of a decryption module. | 10-02-2008 |
20080292095 | Qkd Cascaded Network with Loop-Back Capability - A QKD cascaded network ( | 11-27-2008 |
20090028322 | System for an Encryption Key Path Diagnostic - A system is provided to perform a key path diagnostic that aids in isolating an error within the encryption storage system. The system includes at least one drive, a key proxy, a key server, a key manager, and a processor. The processor performs a first communication test on a path between the key proxy and the drive. The first communication test verifies that the path between the drive and the key proxy is operational. The processor performs a second communication test on a path between the key proxy and the key server. The second communication test verifies that the path between the key proxy and the key server is operational. In addition, processor sends a command to the key manager to attempt communication with the key manager. The communication attempt verifies the installation and configuration parameters related to the key manager. | 01-29-2009 |
20090147945 | Configurable ASIC-embedded cryptographic processing engine - Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic. | 06-11-2009 |
20090232300 | Securing data using integrated host-based data loss agent with encryption detection - A method and system for securing data in a computer system provides the capability to secure information even when it leaves the boundaries of the organization using a data loss agent integrated with encryption software. A method for securing data in a computer system comprises detecting attempted connection or access to a data destination to which sensitive data may be written, determining an encryption status of the data destination, allowing the connection or access to the data destination when the data destination is encrypted, and taking action to secure the sensitive data when the data destination is not encrypted. | 09-17-2009 |
20100215171 | TRANSPORT PACKET DECRYPTION TESTING IN A CLIENT DEVICE - In a method for testing a transport packet decrypting module of a client device, a first decryption operation of the transport packet decrypting module is implemented on a test encrypted control word using a content decryption key ladder to derive a test control word, a second decryption operation of the transport packet decrypting module is implemented on one or more test transport packets using the test control word via a predetermined content decryption algorithm, the KIV is derived from the decrypted transport packets, and the derived KIV is compared with a value stored in the client device to verify whether the transport packet decrypting module of the client device is functioning properly. | 08-26-2010 |
20110261953 | METHOD FOR TESTING CRYPTOGRAPHIC CIRCUITS, SECURED CRYPTOGRAPHIC CIRCUIT CAPABLE OF BEING TESTED, AND METHOD FOR WIRING SUCH CIRCUIT - The present invention relates to a method for testing cryptography circuits. It also relates to a secure cryptography circuit capable of being tested. The cryptography circuit includes registers and logic gates, and a test thereof performs a differential power analysis on the registers of the circuit. A cryptography circuit being secure and including a first half-circuit associated with a second half-circuit operating in complementary logic, the electric power supply of the first half-circuit is separated from the electric power supply of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two power supplies being combined into one and the same electric power supply after the test. | 10-27-2011 |
20110274267 | DETERMINING HDCP SOURCE KSV SUPPORT - Presented is a method for determining the maximum number of key selection vectors (KSVs) supported by an HDCP source. The method includes transmitting a number of KSVs to the HDCP source, determining whether the HDCP source has entered a failure mode in response to the transmitted number of KSVs, increasing or decreasing the number of KSVs in response to the HDCP source not entering or entering the failure mode, transmitting the increased or decreased number of KSVs to the HDCP source, determining whether the HDCP source has entered the failure mode in response to the transmitted increased or decreased number of KSVs, and repeating the increasing, decreasing, and determining steps until the difference between a lowest number of transmitted KSVs resulting in the HDCP source entering the failure mode and a highest number of transmitted KSVs resulting in the HDCP source not entering the failure mode is one. | 11-10-2011 |
20120008765 | DETERMINING HDCP SOURCE KSV SUPPORT - Presented is a method for determining the maximum number of key selection vectors (KSVs) supported by an HDCP source. The method includes providing a number of KSVs to the HDCP source, determining whether the HDCP source has entered a failure mode in response to the provided number of KSVs, increasing or decreasing the number of KSVs in response to the HDCP source not entering or entering the failure mode, providing the increased or decreased number of KSVs to the HDCP source, determining whether the HDCP source has entered the failure mode in response to the provided increased or decreased number of KSVs, and repeating the increasing, decreasing, and determining steps until the difference between a lowest number of provided KSVs resulting in the HDCP source entering the failure mode and a highest number of provided KSVs resulting in the HDCP source not entering the failure mode is one. | 01-12-2012 |
20120069991 | METHOD FOR AUTHENTICATING ACCESS TO A SECURED CHIP BY TEST DEVICE - A method for authenticating access to a secured chip SC by a test device TD, the test device storing at least one common key CK and one test key TK, the secured chip SC storing the same common key CK and a reference digest F(TK) resulting from a cryptographic function on the test key TK, the method comprising the steps of:—receiving, by the test device TD, a challenge R produced by the secured chip SC,—combining, by the test device TD, the received challenge R with the test key TK by applying a bidirectional mathematical operation (op), encrypting the result (TK op R) with the common key CK, obtaining a cryptogram CK(TK op R),—sending the cryptogram CK(TK op R) to the secured chip SC—decrypting, by the secured chip SC, the cryptogram CK(TK op R) with the common key CK, obtaining an image key TK′ representing the test key TK by applying, with the challenge R, the reverse operation (op-1) of the mathematical operation (op) previously used by the test device TD,—calculating an expected digest F(TK′) of the image key TK′ with a cryptographic one-way function,—verifying validity by comparing the expected digest F(TK′) with the reference digest F(TK),—if the result of the comparison between the digest F(TK′) of the image key TK′ and the reference digest F(TK) is positive, accessing, by the test device TD, the secure chip SC in a test mode. | 03-22-2012 |
20120201372 | HDCP Link Integrity Checking with Detection of Enhanced Link Verification Support - A method is disclosed for checking HDCP link integrity in a High-bandwidth Digital Content Protection (HDCP) transmitter. From an HDCP receiver communicatively coupled to the HDCP transmitter by an HDCP-protected interface, a single-bit value indicative of HDCP 1.1 feature support is read. When the single-bit value is true, HDCP Enhanced Link Verification is used in the HDCP transmitter. When the single-bit value is false, the method determines whether the HDMI receiver supports HDCP Enhanced Link Verification, and if so, HDCP Enhanced Link Verification is used in the HDCP transmitter. | 08-09-2012 |
20130121485 | METHOD FOR DETECTING AN ILLICIT USE OF A SECURITY PROCESSOR - This method for detecting an illicit use of a security processor used for the descrambling of different multimedia contents disseminated on several respective channels comprises:
| 05-16-2013 |
20150092939 | DARK BITS TO REDUCE PHYSICALLY UNCLONABLE FUNCTION ERROR RATES - Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array. | 04-02-2015 |
20160111025 | Method and Device for Automatic Development of a Behavior Model of an Apparatus Providing a Cryptographic Interface - The invention relates to a method for the automatic development, using a programmable device, of a behaviour model for an apparatus providing a cryptographic interface. This method comprises the following steps, carried out by a processor of the programmable device:—obtaining ( | 04-21-2016 |
20160148020 | TWO-WAY PARITY ERROR DETECTION FOR ADVANCED ENCRYPTION STANDARD ENGINES - A method of improving the operation of a processor executing a cryptographic process, by automatically detecting faults during both encryption and decryption operations by the cryptographic process, comprises segmenting the data to be encrypted and encrypting the data segments using a complex non-linear algorithm that can lead to faults; computing an output parity bit from a selected step of the algorithm for a selected data segment, based on the input value of that segment; comparing the actual output parity bit of the selected segment with the computed output parity bit for that segment; and determining whether a fault exists, based on whether the actual output parity bit matches the computed output parity bit for the selected segment. | 05-26-2016 |