Class / Patent application number | Description | Number of patent applications / Date published |
438687000 | Copper of copper alloy conductor | 22 |
20080227294 | Method of making an interconnect structure - A method of making an interconnect structure includes providing a die ( | 09-18-2008 |
20080233745 | Interconnect Structures for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 09-25-2008 |
20080242088 | METHOD OF FORMING LOW RESISTIVITY COPPER FILM STRUCTURES - A method for forming low (electrical) resistivity Cu film structures by depositing a metal nitride barrier film on a substrate, depositing a Ru film on the metal nitride barrier film, depositing a Cu seed layer on the Ru film, and depositing bulk Cu metal on the Cu seed layer. The method further includes heat treating the Ru film prior to the Cu seed layer deposition, heat treating the bulk Cu metal, or heat treating both the Ru film prior to the Cu seed layer deposition and the bulk Cu metal. According to one embodiment, a method is provided for forming low resistivity Cu interconnect structures for integrated circuits. | 10-02-2008 |
20080254624 | METAL CAP FOR INTERCONNECT STRUCTURES - A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap. | 10-16-2008 |
20080299772 | Methods of fabricating electronic devices using direct copper plating - The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention. | 12-04-2008 |
20080318424 | Photoresist residue remover composition and semiconductor circuit element production process employing the same - A photoresist residue remover composition is provided that removes a photoresist residue formed by a resist ashing treatment after dry etching in a step of forming, on a substrate surface, wiring of any metal of aluminum, copper, tungsten, and an alloy having any of these metals as a main component, the composition including one or two or more types of inorganic acid and one or two or more types of inorganic fluorine compound. There is also provided a process for producing a semiconductor circuit element wherein, in a step of forming wiring of any metal of aluminum, copper, tungsten, and an alloy having any of these metals as a main component, the photoresist residue remover composition is used for removing a photoresist residue formed by a resist ashing treatment after dry etching. | 12-25-2008 |
20090047783 | METHOD OF REMOVING UNWANTED PLATED OR CONDUCTIVE MATERIAL FROM A SUBSTRATE, AND METHOD OF ENABLING METALLIZATION OF A SUBSTRATE USING SAME - A method of removing unwanted material from a substrate includes providing a system ( | 02-19-2009 |
20090081870 | METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING COPPER WIRING LAYERS OF DIFFERENT WIDTHS HAVING METAL CAPPING LAYERS OF DIFFERENT THICKNESSES FORMED THEREON - In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer. | 03-26-2009 |
20090176369 | LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES - A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N | 07-09-2009 |
20090186482 | METHOD OF FORMING CAPPING STRUCTURES ON ONE OR MORE MATERIAL LAYER SURFACES - Methods of forming capping structures on one or more different material surfaces are provided. One embodiment includes disposing a semiconductor structure in a reduced pressure chamber, forming a capping GCIB within the reduced pressure chamber, and directing the capping GCIB onto at least one of the one or more different material surfaces, so as to form at least one capping structure on the one or more surfaces onto which the capping GCIB is directed. | 07-23-2009 |
20100009535 | METHODS AND SYSTEMS FOR BARRIER LAYER SURFACE PASSIVATION - This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment. | 01-14-2010 |
20100136789 | Dielectric Barrier Deposition Using Oxygen Containing Precursor - A method is provided for depositing a dielectric barrier film including a precursor with silicon, carbon, oxygen, and hydrogen with improved barrier dielectric properties including lower dielectric constant and superior electrical properties. This method will be important for barrier layers used in a damascene or dual damascene integration for interconnect structures or in other dielectric barrier applications. In this example, specific structural properties are noted that improve the barrier performance. | 06-03-2010 |
20110021024 | SURFACE TREATMENT IN SEMICONDUCTOR MANUFACTURING - The present invention provides a process for forming a capping layer on a conducting interconnect for a semiconductor device, the process comprising: providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface; exposing the surface of the substrate to a vapour of β-diketone or a β-ketoimine; and depositing a capping layer on the surface of at least some of the one or more conductors. The present invention further provides an apparatus for carrying out this method. | 01-27-2011 |
20110027992 | MEMORY DEVICE WITH IMPROVED DATA RETENTION - The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second and into which ions from the passive layer may be provided, and from which the ions may be provided into the passive layer. The active layer is made up of a base material and an impurity therein. The combined the material and impurity have a lower diffusion coefficient than the base material alone. | 02-03-2011 |
20110130000 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING COMPOSITIONS FOR ETCHING COPPER - A method of manufacturing a semiconductor device includes preparing a substrate on which a fuze line containing copper is formed. The method further includes cutting the fuze line by emitting a laser beam, and applying a composition for etching copper to the substrate to finely etch a cutting area of the fuze line and to substantially remove at least one of a copper residue and a copper oxide residue remaining near the cutting area. The composition for etching copper includes about 0.01 to about 10 percent by weight of an organic acid, about 0.01 to 1.0 percent by weight of an oxidizing agent, and a protic solvent. | 06-02-2011 |
20120040531 | METHOD TO FABRICATE THIN METAL VIA INTERCONNECTS ON COPPER WIRES IN MRAM DEVICES - A scheme for forming a thin metal interconnect is disclosed that minimizes etch residues and provides a wet clean treatment for via openings. A single layer interlayer dielectric (ILD), BARC, and photoresist layer are successively formed on a substrate having a copper layer that is coplanar with a dielectric layer. In one embodiment, the ILD is silicon nitride with 100 to 600 Angstrom thickness. After a via opening is formed in a photoresist layer above the copper layer, a first RIE process including BARC main etch and BARC over etch steps is performed. Then a second RIE step transfers the opening through the ILD to uncover the copper layer. Photoresist and BARC are stripped with oxygen plasma and a low DC bias. Wet cleaning may involve a first ST250 treatment, ultrasonic water treatment, and then a third ST250 treatment. A bottom electrode layer may be deposited in the via opening. | 02-16-2012 |
20120270396 | ETCHANT AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME - Disclosed are an etchant which is used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel, and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant to be used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode, including hydrogen peroxide, an organic acid, and an organic phosphonic acid, wherein the organic acid is at least one member selected from citric acid and malic acid; a content of hydrogen peroxide is from 0.75 to 12% by mass; a content of the organic acid is from 0.75 to 25% by mass; and a content of the organic phosphonic acid is from 0.0005 to 1% by mass, and a method for manufacturing a semiconductor device using the etchant. | 10-25-2012 |
20130084701 | TREATMENT METHOD FOR REDUCING PARTICLES IN DUAL DAMASCENE SILICON NITRIDE PROCESS - A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH | 04-04-2013 |
20130323927 | MANUFACTURING METHOD OF CIRCUIT STRUCTURE - A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. The metal layer and the surface passivation layer are dipped into a modifier, and the modifier is selectively absorbed and attached to the surface passivation layer, so as to form a covering layer. The covering layer has a plurality of nanoparticles and covers the surface passivation layer. | 12-05-2013 |
20140273453 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring. | 09-18-2014 |
20140370706 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased. | 12-18-2014 |
20160083675 | CLEANING LIQUID COMPOSITION - The purpose of the present invention is to provide a cleaning liquid composition useful in cleaning substrates, etc., which have undergone treatment such as chemical mechanical polishing (CMP) in a process for manufacturing electronic devices such as semiconductor elements. This cleaning liquid composition for cleaning substrates having Cu wiring includes one or more basic compounds and one or more heteromonocyclic aromatic compounds containing a nitrogen atom, and has a hydrogen ion concentration (pH) of 8-11. | 03-24-2016 |