Class / Patent application number | Description | Number of patent applications / Date published |
455218000 | Squelch | 8 |
20100081406 | Dynamic squelch detection power control - In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed. | 04-01-2010 |
20120015617 | Squelch Detection Circuit and Method - A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold. | 01-19-2012 |
20130029622 | SQUELCH DETECTOR CIRCUIT AND METHOD - A squelch detector includes a first circuit, a second circuit, and a comparator. The first circuit is configured to receive a first pair of differential input signals and in response output a second pair of differential signals. The second pair of differential signals have higher voltages than the first pair of differential input signals. The second circuit is coupled to the first circuit and is configured to extract first and second voltage levels from the second pair of differential signals. The comparator is configured to output a squelch level signal based on a comparison of the first voltage level and a third voltage level. The third voltage level is based on the second voltage level and a reference voltage. | 01-31-2013 |
455219000 | With automatic gain or volume control | 2 |
20080233912 | METHOD AND APPARATUS FOR POWER REDUCTION FOR INTERCONNECT LINKS - A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling. | 09-25-2008 |
20100317307 | RADIO FREQUENCY HANDING DEVICE - A radio frequency signal handling device and a mobile communication device comprising such a radio frequency signal handling device. The radio frequency signal handling device comprises a first terminal interfacing external entities in the form of an input where radio frequency signals are to be received, at least one signal scaling unit having a first end where a signal provided by a terminal interfacing external entities is received, and one signal detector provided for each signal scaling unit and being connected to a second end of the corresponding signal scaling unit for detecting a signal provided by this signal scaling unit. The signal scaling unit only includes passive reactive components and comprises at least one such passive reactive component. | 12-16-2010 |
455222000 | Noise controlled | 3 |
20100003938 | NOISE MEASUREMENT FOR RADIO SQUELCH FUNCTION - A method implementable in an audio receiver having an input for receiving broadcast signals including a set of channels and a squelching controller includes converting the signals associated with each channel into respective digital signals, and tuning the digital signals associated with a first subset of the channels. For each channel of the first channel subset, a respective set of amplitudes associated with respective frequencies of the associated digital signal is determined. A random-noise-level value associated with each channel of the first channel subset is determined from each set of the signal amplitudes. If a signal amplitude associated with a first channel of the first channel subset exceeds the random-noise-level of the first channel, a second subset of the channels of the set is tuned. Otherwise, the random-noise-levels are provided to the squelching controller. | 01-07-2010 |
20100130149 | INTEGRATED SQUELCH CIRCUIT WITH PROGRAMMABLE ENGAGEMENT THRESHOLD - A method, system, and apparatus for squelching a signal in telecommunications systems. The apparatus includes a filter, two power detectors, a divider, two comparators, a logic gate, and a gain control block. The apparatus receives an input signal, and the power of the signal is detected. The input signal is also filtered to pass only the noise portion of the signal, and the power of the filtered signal is detected. A ratio between the filtered signal power and the input signal power is determined. A first comparator receives the filtered signal power and a second comparator receives the ratio of the filtered signal power and the input signal power. The logic gate receives the outputs from the first and second comparators. The gain control block receives as inputs the logic gate's output and the input signal to the apparatus. The gain control block may attenuate the input signal based on the logic gate's output. The gain control block generates the output signal of the apparatus. | 05-27-2010 |
455223000 | Short duration (noise blankers) | 1 |
20080261549 | Noise blanker circuit and method for removing noise and correcting a signal - A noise blanker circuit and method of removing impulse noise from a signal and correcting the signal is provided. The circuit includes a detection stage, a pulse removal stage, and a pulse removal correction stage. The detection stage includes at least an input that emits an input signal along a first signal path and a second signal path. The first and second signal paths are in communication with a blank pulse generator. The pulse removal stage is in communication with the input and includes at least a sample and hold device that samples and holds the input signal based upon an output of the blank pulse generator. The pulse removal correction stage includes at least a pulse removal device in communication with the detection stage and the pulse removal stage and corrects the input received from the pulse removal stage based upon the output of the blank pulse generator. | 10-23-2008 |