Class / Patent application number | Description | Number of patent applications / Date published |
703028000 | In-circuit emulator (i.e., ICE) | 47 |
20080243471 | SYSTEM AND A METHOD FOR CHECKING LOCK-STEP CONSISTENCY BETWEEN AN IN CIRCUIT EMULATION AND A MICROCONTROLLER - A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. The virtual microcontroller and the microcontroller simultaneously and independently run a microcontroller code. The microcontroller includes a first memory and the virtual microcontroller residing in the ICE includes a second memory. A host computer copies a content of the first memory and a content of the second memory in the host computer memory when the execution of the code is halted. The host device compares the content of the first memory and the content of the second memory for consistency. In case of a disparity between the content of the first memory and the content of the second memory, a user traces the execution of the code in a trace buffer residing in the ICE and debugs the faulty code accordingly. | 10-02-2008 |
20080270107 | Method of Debugging an Executable Computer Program Having Instructions for Different Computer Architectures - A method of debugging an executable computer application comprising instructions of a first computer architecture instruction set and instructions of a second computer architecture instruction set. The method comprises determining whether an instruction being debugged is from the second architecture instruction set; and obtaining debug information from an emulator of the second architecture in a first architecture environment when the instruction being executed is from the second architecture instruction set. The debug information results from emulation of the instruction being debugged. | 10-30-2008 |
20080288238 | Computing System with Guest Code Support of Transactional Memory - A data structure of readily accessible units of memory is provided as computer useable media having computer readable program code logic providing information tables and a software emulation program to enable hardware to run new software that uses transactional memory and a bit associated with a transaction for executing transactional memory constructs. The data structure with Guest PTRAN bit is used in emulation of software written for a given computer on a different computer which executes a different set of instructions. The emulating instructions are used to provide transactional memory instructions on a computer which does not support those instructions natively | 11-20-2008 |
20090006074 | ACCELERATED ACCESS TO DEVICE EMULATORS IN A HYPERVISOR ENVIRONMENT - A hypervisor environment configured for accelerated access to device emulators comprises a hypervisor that intercepts a device access instruction to a child partition processor and routes said device access instruction to a root partition. A processor instruction emulator emulates said device access instruction along with any number of next instructions of the processor in said child partition, thereby dispatching accesses to a device emulator on behalf of the processor in said child partition. By emulating these instructions in the root partition, accesses to the device emulator are greatly accelerated. | 01-01-2009 |
20090177459 | FAULT SUPPORT IN AN EMULATION ENVIRONMENT - An emulator is disclosed that allows for diagnoses of failures or defects within the emulator. A map of faulty resources is generated to identify which resources should be avoided during compilation. Thus, in a transparent and automated manner, defects found during diagnostics are stored in a database of unusable emulator resources. A compiler has access to the database and compiles the design taking into account unusable resources. In another embodiment, the defects of an emulator board are stored on the emulator board itself. This allows each board to store its own maintenance information that can be used at the manufacturing site for changing defective chips. Defects stored on the board itself allow the defects to be obtained independent of a position of a board within the emulator to simplify identification of the faulty resource. | 07-09-2009 |
20090204383 | Procedure and Device for Emulating a Programmable Unit Providing System Integrity Control - A method and corresponding equipment for emulation of a target programmable unit, which has at least one CPU, by means of an external emulation device, which is coupled to the target programmable unit by means of a communication link, comprising: transferring predetermined initialization data through the communication link to the emulation device for initializing the emulation; transferring through the communication link to the emulation device a CPU clock signal and emulation data; emulating the target programmable unit in the external emulation device using the transferred emulation data; ascertaining respective trace data from the emulation in the external emulation device and storing and/or outputting the trace data; deriving respective target integrity-control data and emulation integrity-control data from respective target-internal data and emulation-internal data; and transferring the derived target integrity-control data from the target programmable unit to the external emulation device. | 08-13-2009 |
20090204384 | DEBUGGING DEVICE, DEBUGGING METHOD AND HARDWARE EMULATOR - A hardware emulator having: a verification target circuit that includes a CPU in which progress of instruction execution is controlled by a program counter, and a circuit that operates according to the instruction execution by the CPU; at least one replica circuit that is formed by replication of the verification target circuit; a debug controller that starts operation of the verification target circuit upon receipt of an operation start signal from an outside of the hardware emulator, and that stops operation of the verification target circuit and the replica circuit when a value of the program counter of the verification target circuit reaches a predetermined breakpoint; an execution start delaying portion that causes the replica circuit to start execution of an instruction with a delay equivalent to a predetermined number of instructions after the verification target circuit starts execution of the same instruction; a program counter controller that performs control so that the value of the program counter of the verification target circuit and a value of a program counter of the replica circuit are simultaneously updated when both of the verification target circuit and the replica circuit complete the execution of their respective running instructions; and an output portion that sends an output from any one of the verification target circuit and the replica circuit to the outside of the hardware emulator in response to a request from the outside of the hardware emulator. | 08-13-2009 |
20090222254 | SYSTEM AND METHOD FOR INTEGRATED CIRCUIT EMULATION - A system and method for integrated circuit emulation. One embodiment provides a system for in-circuit emulation of an integrated circuit device with program-controlled components. The system includes an integrated circuit device with program-controlled components used in a system for normal operation. The integrated circuit device having at least one program-controlled emulation unit emulating at least one of the program-controlled components of the integrated circuit device, and at least one statistics memory for storing statistical data of the program-controlled emulation unit during emulation. | 09-03-2009 |
20090271174 | EMULATION SYSTEM AND DRIVING METHOD THEREOF - An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit. | 10-29-2009 |
20090287468 | EVENT-DRIVEN EMULATION SYSTEM - A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect. | 11-19-2009 |
20090299723 | MONITORING PHYSICAL PARAMETERS IN AN EMULATION ENVIRONMENT - A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time, such as after a periodic update. In one embodiment, a monitoring portion of the emulator periodically monitors the emulator boards and power supplies for physical information. The physical information is communicated to a workstation for communication to a user. For example, the workstation can display the physical information in a graphical user interface (GUI) that shows which boards are plugged in the system and which slots are empty. In yet another aspect, the user can select a particular board in the system and view communication information, such as data errors, status, link errors, global errors, etc. In a further aspect, power supply information can be viewed, such as current and voltage levels, air temperature, fan speed, board temperatures at particular points, etc. In another aspect, the IC layout on a board can be viewed with a graphical presentation of which ICs are malfunctioning. Even further, the sections within a particular IC can be viewed with a graphical presentation of sections within the IC that are malfunctioning. | 12-03-2009 |
20090313004 | Platform-Independent Application Development Framework - Embodiments of the invention provide a platform-independent application development framework for programming an application. The framework comprises a content interface configured to provide an Application Programming Interface (API) to program the application comprising a programming code to be executed on one or more platforms. The API provided by the framework is independent of the one or more platforms. The framework further comprises an application environment configured to provide an infrastructure that is independent of the one or more platforms and one or more plug-in interfaces configured to provide an interface between the application environment and the one or more platforms. | 12-17-2009 |
20100070260 | Verification device, verifying apparatus and verification system - Provided is a verification system which improves the efficiency of operation verification in the development of digital LSIs. In the verification system, a verification device can communicate with a verifying apparatus through a bus interface. In the verification device, first and second partial circuits communicating with each other constitute a target for operation verification, i.e., a to-be-verified circuit. The verifying apparatus includes a software emulator which causes a CPU to execute, through a program, calculation corresponding to processing executed by the first partial circuit. A destination selection circuit is installed in a connection path between the first and second partial circuits, and is capable of switching a communication destination of the second partial circuit between the first partial circuit and the software emulator. | 03-18-2010 |
20100145672 | MICROCOMPUTER AND EMBEDDED SOFTWARE DEVELOPMENT SYSTEM - In an aspect of the present invention, a microcomputer includes a CPU core section, and a plurality of external input terminals. A testing section selects a selection external input terminal from the plurality of external input terminals, detects an intermediate voltage of the selection external input terminal, and outputs an interrupt processing signal related to the detection of the intermediate voltage to the CPU core section. | 06-10-2010 |
20100161309 | Apparatus and Methods Thereof for Configuration and Control of a System-On-Chip Emulation Platform - An apparatus, protocol and methods for configuration of a platform for prototyping and emulation of a system-on-chip (SOC) device. The apparatus is an extensible platform for configurable prototyping of SOCs using an integrated circuit board comprised of a configurable board controller and a plurality of configurable modules which implement the SOC functionality. A plurality of such platform boards may be linked together to provide emulation and prototyping functionality for a multi-core system. The protocol specifies the SOC platform configuration data, commands for configuration and reading and writing data to each module and the communications between the host computer and the platform. The apparatus uses methods for configurable execution of the configuration commands by the board controller, and for the preparation of the configuration specification by the host computer. The host computer provides a user interface for management of the configuration specification preparation. | 06-24-2010 |
20100169072 | MULTI-PLATFORM SOFTWARE APPLICATION SIMULATION SYSTEMS AND METHODS - An exemplary system includes a development subsystem configured to facilitate development of a software application and a simulation subsystem selectively and communicatively coupled to the development subsystem. The simulation subsystem is configured to emulate a plurality of processing device platforms, receive data representative of a selection of at least one of the plurality of processing device platforms, and simulate an execution of the software application by one or more processing devices associated with the at least one selected processing device platform. | 07-01-2010 |
20100262417 | BINARY VALUE INPUT/OUTPUT PROCESSING APPARATUS AND METHOD - The invention relates to a binary value input/output processing apparatus and method for automatically inputting binary values. A binary value that is inputted first is temporarily stored in a buffer. When a symbol indicating a binary value, such as “0x” or “0X”, is detected from the next input character string, the binary value stored in the buffer is automatically outputted to the screen, following the symbol. Then, a user selects to output, to the output device, the binary value automatically outputted to the screen or to output a new binary value to the output device, instead of the binary value. When the new binary value is outputted, the binary value stored in the buffer is deleted, and the new binary value is stored in the buffer. | 10-14-2010 |
20100318345 | System and Method Implementing Full-Rate Writes For Simulation Acceleration - A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus arid an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus. | 12-16-2010 |
20100332213 | DEBUGGING SYSTEM, EMULATOR, AND DEBUGGING METHOD - A debug system includes: a microcomputer mounted on a target system; an emulator configured to execute emulation of the microcomputer based on a user program embedded in the microcomputer; and a computer connected with the emulator in radio communication and configured to instruct start of the emulation and to execute a debugging operation of the microcomputer based on a result of the emulation. The emulator includes: a control section configured to execute the emulation of the microcomputer based on control data from the computer; a radio communication state monitoring section configured to monitor a state of the radio communication between the computer and the emulator when the emulation is performed; and a storage section configured to store substitution control data. The control section acquires the substitution control data from the storage section, when the radio communication is in a non-communicable state, and controls the microcomputer based on the substitution control data such that the target system is set to a predetermined state. | 12-30-2010 |
20110004460 | VIRTUAL TESTBED FOR SYSTEM VERIFICATION TEST - A virtual testbed for system verification test is provided in which emulated responses are associated with certain steps of a system verification test. The emulated responses can be manually entered or populated with previous test results obtained from execution of the emulation-enabled steps on a real testbed. When the emulation-enabled steps are executed, the system verification test uses the emulated responses as the responses corresponding to the actions of the emulation-enabled steps as if the steps were executed on the real testbed, without actually executing the emulation-enabled steps on the real testbed. Therefore, the virtual testbed of the present invention allows development of test scripts for system verification test without constant, actual access to the real testbed. | 01-06-2011 |
20110046938 | Verification apparatus and design verification program - A design verification apparatus includes a dataset generator to generate verification datasets which associate each unit process of a plurality of procedures (processing scenarios) described in a design specification of a target product with an identifier (label) designating which portion of the design specification is to be verified. A process priority setting unit assigns a process priority to each verification dataset according to specified identifiers. An output processor outputs data identifying the verification datasets, together with explicit indication of their process priorities. | 02-24-2011 |
20110106522 | VIRTUAL PLATFORM FOR PROTOTYPING SYSTEM-ON-CHIP DESIGNS - A system to prototype a system-on-chip design is presented. In one embodiment, the system includes an electronic board comprising a logic device programmable to emulate system components. The system further comprises a processor to execute a virtual machine monitor which redirects an input/output request to the system components via an interconnect. | 05-05-2011 |
20110119045 | MONITORING PHYSICAL PARAMETERS IN AN EMULATION ENVIRONMENT - A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time, such as after a periodic update. In one embodiment, a monitoring portion of the emulator periodically monitors the emulator boards and power supplies for physical information. The physical information is communicated to a workstation for communication to a user. For example, the workstation can display the physical information in a graphical user interface (GUI) that shows which boards are plugged in the system and which slots are empty. In yet another aspect, the user can select a particular board in the system and view communication information, such as data errors, status, link errors, global errors, etc. In a further aspect, power supply information can be viewed, such as current and voltage levels, air temperature, fan speed, board temperatures at particular points, etc. In another aspect, the IC layout on a board can be viewed with a graphical presentation of which ICs are malfunctioning. Even further, the sections within a particular IC can be viewed with a graphical presentation of sections within the IC that are malfunctioning. | 05-19-2011 |
20110131031 | DYNAMIC GENERATION OF TESTS - Generation of a test based on a test template comprising of branch instructions. The test template may be a layout test template, defining a set of possible control flows possibilities between template instructions in the layout test template. The test is generated by a test generator which may simulate a state of a target computerized system executing the test. The simulation may be performed during generation of the test. The test generator may further verify previously generated instructions. The test generator may further generate instructions associated with leftover template instructions. | 06-02-2011 |
20110184717 | Method and System for Packet Switch Based Logic Replication - A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels. The destination logic may emulate the source logic synchronized with the plurality of clock domains delayed by the delay period. | 07-28-2011 |
20110251836 | CIRCUIT EMULATION SYSTEMS AND METHODS - An apparatus for circuit emulation may include a first circuit board, one or more circuit emulation resource on the first circuit board, a first interconnection interface on the first circuit board, and a second interconnection interface on the first circuit board. The first circuit board may include conductive wiring paths. The circuit emulation resource is on the first circuit board and coupled with a portion of the conductive wiring paths, with each circuit emulation resource being configured to emulate a portion of an electronic circuit by receiving input signals and producing output signals in response to the input signals. The first interconnection interface is on the first circuit board and coupled with at least a first portion of the circuit emulation resource, The first interconnection interface may be configured to couple with an interconnection interface of a second circuit board having a second group of conductive wiring paths and having a second group of circuit emulation resources. The second interconnection interface is on the first circuit board and coupled with at least a second portion of the at least one circuit emulation resource. The second interconnection interface may be configured to couple with an interconnection interface of a third circuit board having a third group of conductive wiring paths and having a third group of circuit emulation resources. | 10-13-2011 |
20110264435 | MODULAR CIRCUIT EMULATION SYSTEM - A modular circuit emulation system includes a plurality of emulation boards that each include at least one programmable circuit. A system backplane has a switching matrix that selectively couples the plurality emulation boards. A broadcast bus broadcasts data from one of the plurality of emulation boards to other ones of the plurality of emulation boards. | 10-27-2011 |
20110264436 | CLOCK SYNCHRONIZATION IN A MODULAR CIRCUIT EMULATION SYSTEM - A modular circuit emulation system includes a global clock generator that generates a plurality of clock signals. A plurality of emulation boards each include at least one programmable circuit and a clock buffer. The clock buffer generates at least one synchronized clock signal for clocking the programmable circuit or circuits, based on at least one of the plurality of global clock signals. | 10-27-2011 |
20110307239 | Hardware Emulation Proxy for Hardware Software Co-Emulation - The invention provides for the interaction of an emulator emulating an electronic design having a communication bus communicating with a software application over the emulated communication bus. The interaction is facilitated in such a manner as to provide an appropriate latency for the emulated communication bus. According to various implementations of the invention, a protocol proxy is provided. The protocol proxy is designed to be emulated along with an electronic design and configured to communicate to software executing on a computer connected to the emulator. The protocol proxy includes a protocol module that communicates to the electronic design being emulated in the emulator environment. Furthermore, the protocol proxy includes a software control module that communicates to the software outside the emulator through proxy communication channels. Further still, the protocol proxy includes a data storage component. | 12-15-2011 |
20110313753 | Multicast emulation - Systems and methods for emulating the reception of a multicast message considering simulated host channel characteristics. Methods, according to various embodiments, may comprise executing a plurality of host applications subscribing to a first multicast group address. The methods may also comprise executing a plurality of sockets. The methods may also comprise receiving a data packet indicating the first multicast group address. The data packet may be modified according to a first channel impairment condition to generate a first impaired data packet, which may be directed to a first host application selected from the plurality of host applications via a first socket selected from the plurality of sockets. The first socket may correspond to the first host. The data packet may be modified according to a second channel impairment condition to generate a second impaired data packet directed to a second host application via a second socket. | 12-22-2011 |
20120166173 | METHOD AND SYSTEM FOR DETERMINING AN ARBITRARY CHARGING PROTOCOL IN USB CHARGING PORTS - An emulation system for determining an arbitrary charging protocol in USB charging ports and for optimally charging portable devices. The emulation system comprises a power switch for powering on the emulation system, a high-speed data switch for transferring data to and from the portable device, a USB receptacle port including data pins (D | 06-28-2012 |
20120203537 | Autonomous, Scalable, Digital System For Emulation of Wired-Or Hardware Connection - A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states. | 08-09-2012 |
20120226488 | MONITORING PHYSICAL PARAMETERS IN AN EMULATION ENVIRONMENT - A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time, such as after a periodic update. In one embodiment, a monitoring portion of the emulator periodically monitors the emulator boards and power supplies for physical information. The physical information is communicated to a workstation for communication to a user. For example, the workstation can display the physical information in a graphical user interface (GUI) that shows which boards are plugged in the system and which slots are empty. In yet another aspect, the user can select a particular board in the system and view communication information, such as data errors, status, link errors, global errors, etc. | 09-06-2012 |
20120232881 | Trace Routing Network - Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device. | 09-13-2012 |
20120265517 | Dedicated Memory Window for Emulation Address - This invention allows code emulation in a memory system by implementing a fixed location and size emulation segment that is only accessible to emulation requests, and may be mapped to any area of the physical memory space by the Extended Memory Controller. All areas of the memory space are visible to the emulation process, whether there is a functional segment mapped to that area or not. | 10-18-2012 |
20120271616 | METHOD OF EMULATING A CONTROLLER PILOT DATA LINK COMMUNICATION HUMAN MACHINE INTERFACE - A computing-platform emulator for use on a vehicle is provided. The computing-platform emulator includes a display, a processor communicatively coupled to the display, a data-entry interface communicatively coupled to the processor, and at least one electronic interface to interface a host system in the vehicle to the processor. The host system implements at least one application and at least one protocol for use on the computing-platform emulator. The display, the data-entry interface, and the at least one electronic interface function as a multifunction control display unit. | 10-25-2012 |
20120323553 | Mobile Emulator Integration - Aspects of the subject matter described herein relate to recommending data sources. In aspects, a request to provide recommendations of data enrichments for a database is received at a recommendation engine. The recommendation engine may perform static and dynamic analysis of data associated with the database and may further refine recommendations based on policies. The recommendation engine may then provide the recommendations, if any, of data enrichments to allow a software developer, for example, to indicate whether the data enrichments are to be used. | 12-20-2012 |
20130035925 | METHOD AND APPARATUS FOR VERSATILE CONTROLLABILITY AND OBSERVABILITY IN PROTOTYPE SYSTEM - A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation. | 02-07-2013 |
20130117007 | METHOD AND APPARATUS FOR TURNING CUSTOM PROTOTYPE BOARDS INTO CO-SIMULATION, CO-EMULATION SYSTEMS - A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design. | 05-09-2013 |
20130132063 | SYSTEMS AND METHODS FOR DEBUGGING JUST-IN-TIME STATIC TRANSLATION IN AN EMULATED SYSTEM - Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system. | 05-23-2013 |
20130138420 | Managing Varying Instrumentation Volumes to Prevent Data Loss - This invention is a method and apparatus for monitoring an electronic apparatus. Capture units capture data to be monitored. A first-in-first-out buffer corresponding to each capture unit buffers the captured data. The buffered data supplies a utilization unit. Captured data may be merged after or before buffering. This merged data may be further merged with other buffered data. | 05-30-2013 |
20130166273 | CIRCUIT EMULATION APPARATUS AND CIRCUIT EMULATION METHOD - A circuit emulation apparatus includes an emulator unit configured to emulate an operation of a circuit, a replacement unit configured to replace one or more redundant bits with a predetermined bit pattern when information bits and the one or more redundant bits of read data that is read from a first memory by the circuit are all zeros, and a supply unit configured to supply the information bits and the predetermined bit pattern as the read data to the circuit. | 06-27-2013 |
20130275115 | CROSSTALK EMULATOR FOR XDSL CABLE - A crosstalk emulator for a cable, preferably a xDSL telecommunication cable, represented by several emulation paths each comprising a first segment (L | 10-17-2013 |
20130311164 | DYNAMIC GENERATION OF TEST SEGMENTS - A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a target computerized system, the test template comprises a template segment, the template segment comprising one or more instruction and one or more directives or control constructs related to the instructions; a test generator for generating a test associated with the template segment, said test generator comprises: a state simulator for determining a state of the target computerized system associated with an execution of the test; a template instruction or segment selector for selecting a template instruction or segment from the test template based on the state of the target system determined by said state simulator; and an instruction template segment generator configured to generate a multiplicity of instructions based on the state of the target computerized system and the template segment selected by said template instruction selector, wherein the test generator further comprises an instruction verifier configured to verify that a previously generated instruction is in line with the current state of the target computerized system and with the template instruction or segment selected by said template instruction or segment selector. | 11-21-2013 |
20140046650 | TRACE ROUTING NETWORK - Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device. | 02-13-2014 |
20140100841 | Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit - A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system. | 04-10-2014 |
20140156253 | FUNCTIONAL BUILT-IN SELF TEST FOR A CHIP - According to one embodiment, a self-test system integrated on a chip is provided, the chip including a functional logic module for performing a selected application. The self-test system includes a primary interface a primary interface to the functional logic module, the primary interface configured to interface with a primary device, an input interface protocol generator for generating a pattern to be inserted into the primary interface and a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device. The system also includes an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with a secondary device coupled to the secondary interface, wherein the emulator engine tests the function when no secondary device is coupled to the chip. | 06-05-2014 |