Class / Patent application number | Description | Number of patent applications / Date published |
710262000 | Interrupt inhibiting or masking | 58 |
20080270661 | Interruption Management - The present invention relates to a method, system | 10-30-2008 |
20080288693 | Parallel Processing Device and Exclusive Control Method - To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P | 11-20-2008 |
20080294825 | Handling Interrupts When Virtual Machines Have Direct Access to a Hardware Device - In virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system and has direct access to a hardware device coupled to the virtualized computer system via a communication interface, a computer-implemented method of handling interrupts from the hardware device to the guest operating system includes: (a) receiving a physical interrupt from the hardware device on a shared interrupt line of an interrupt controller; (b) masking the shared interrupt line of the interrupt controller; (c) generating a virtual interrupt corresponding to the physical interrupt to the guest operating system; and (d) the guest operating system executing an interrupt service routine. | 11-27-2008 |
20090006694 | MULTI-TASKING INTERFERENCE MODEL - The subject disclosure pertains to a multi-tasking interference system. A gatekeeper receives primary and secondary inputs, and a quantifier ascertains attention values associated with primary inputs and interruption values associated with secondary inputs. Attention values are ascertained based on attributes associated with primary inputs such as type or genre of media presentation, temporal location within media presentation, or a likelihood of impending commercials. Based on a comparison between attention values and interruption values the gatekeeper determines whether, when, and how to interrupt the primary input with the secondary input and accordingly thereafter interrupts the primary input with the secondary input based on the foregoing assessment. | 01-01-2009 |
20090006695 | METHOD AND APPARATUS FOR MEDIATING AMONG MEDIA APPLICATIONS - In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server. | 01-01-2009 |
20090006696 | COMPUTER SYSTEM, PROCESSOR DEVICE, AND METHOD FOR CONTROLLING COMPUTER SYSTEM - A computer system which significantly improves responsiveness to a sleep request includes: a processor device switching between an execution mode and a suspension mode; and an access controlling unit accessing a functional block in response to a command request received from the processor device, wherein, in response to a sleep request signal received from the external device, the processor device responds with a sleep response signal and asserts a suspension notification signal indicating a switch to the suspension mode, and the access controlling unit: masks an input of a further command request after receiving the command request from the processor device, in the case where the processor device has outputted the command request when the access controlling unit receives the suspension notification signal; masks an input of a command request in the case where the processor device has not outputted the command request; and removes the mask when the suspension notification signal is negated. | 01-01-2009 |
20090177826 | SYSTEM AND METHOD FOR PREEMPTIVE MASKING AND UNMASKING OF NON-SECURE PROCESSOR INTERRUPTS - The present disclosure describes systems and methods for preemptive masking and unmasking of non-secure processor interrupts. At least some embodiments provide a system that includes a processor capable of operating in a non-secure mode, and preemption logic coupled to the processor (the preemption logic capable of asserting an interrupt signal to the processor). If the processor is operating in the non-secure mode, the preemption logic preemptively inhibits a non-secure assertion of the interrupt signal in response to a mask event. If the processor is operating in the non-secure mode, the preemption logic preemptively enables the non-secure assertion of the interrupt signal in response to an unmask event. | 07-09-2009 |
20090177827 | METHODS, SYSTEMS, AND DEVICES FOR PROVIDING AN INTERRUPT SCHEME IN AUTOMATED PHARMACEUTICAL DISPENSING MACHINES WITHOUT CENTRALIZED ARBITRATION - In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrically connected by the primary interrupt line. A unique delay time for requesting an interrupt is associated with each of the plurality of slave nodes. A second interrupt request is asserted by the one of the plurality of slave nodes via a secondary interrupt line electrically connecting the plurality of slave nodes. The second interrupt request is asserted in response to successfully asserting the first interrupt request and after the unique delay time associated with the one of the plurality of slave nodes. A message is then transmitted from the one of the plurality of slave nodes to the master node via the bus. Related systems and devices are also discussed, including the use of the primary and secondary interrupt request lines to provide bus arbitration between the plurality of slave nodes for communication with the master node. | 07-09-2009 |
20090204739 | Interruptible write block and method for using same - A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register. | 08-13-2009 |
20090271549 | INTERRUPT HANDLING USING SIMULTANEOUS MULTI-THREADING - Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing system in a simultaneous multi-threading mode. At least a first logical processor and a second logical processor associated with the at least one physical processor are partitioned. The first logical processor is assigned to manage interrupts and the second logical processor is assigned to dispatch runnable user threads. | 10-29-2009 |
20090282179 | METHOD AND SYSTEM OF GROUPING INTERRUPTS FROM A TIME-DEPENDENT DATA STORAGE MEANS - A method of grouping interrupts from a time-dependent data storage means in accordance with the types of the interrupts, the method comprising the steps of providing each part of the data storage means with an indicator of an event associated with the part, generating interrupts upon the occurrence of events in different parts of the data storage means, allocating interrupts associated with substantially the same part of the data storage means to a same processing means. | 11-12-2009 |
20090327553 | Method, device, and system for guaranteed minimum processor power state dwell time - A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state. | 12-31-2009 |
20100036986 | SYSTEM FOR DEBUGGING THROUGHPUT DEFICIENCY IN AN ARCHITECTURE USING ON-CHIP THROUGHPUT COMPUTATIONS - A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate array), a other subsystem module associated with the subsystem module to execute a specified function of the integrated circuit, an interconnect module comprising a transmission line to associate the subsystem module to the other subsystem module, and a throughput monitor circuit (e.g., may continuously determine the throughput value) located in the integrated circuit and coupled with the interconnect module to measure a throughput value as a specified number of data bits per a specified period of time. The system may include, an interrupt generation circuit located in the integrated circuit and coupled with the throughput monitor circuit to determine whether the throughput value is less than a specified throughput value. | 02-11-2010 |
20100049892 | METHOD OF ROUTING AN INTERRUPT SIGNAL DIRECTLY TO A VIRTUAL PROCESSING UNIT IN A SYSTEM WITH ONE OR MORE PHYSICAL PROCESSING UNITS - The present disclosure relates to a method of processing an interrupt comprising a peripheral unit sending an interrupt, the interrupt being intended for a virtual unit executed by a processing unit, transmitting the interrupt to an interrupt control unit coupled to a processing unit, and the interrupt control unit storing the interrupt in an interrupt register. According to an embodiment of the present disclosure, the interrupt is transmitted to the interrupt control unit in association with an identifier of the virtual unit receiving the interrupt, the interrupt register in which the interrupt belonging to a set of registers is stored comprising one interrupt register per virtual unit likely to be executed by the processing unit, the interrupt being transmitted to the processing unit if the virtual unit receiving the interrupt is being executed by the processing unit. | 02-25-2010 |
20100122007 | MICROCONTROLLER WITH CONFIGURABLE LOGIC ARRAY - A microcontroller may have a central processing unit (CPU); a programmable logic device receiving input signals and having input/outputs coupled with external pins, and an interrupt control unit receiving at least one of the internal input signals or being coupled with at least one of the input/outputs and generating an interrupt signal fed to the CPU. | 05-13-2010 |
20100180059 | DETECTION CIRCUIT AND SENSOR DEVICE - Provided is a detection circuit for monitoring a power supply voltage with a circuit configuration in which power consumption is reduced, and a sensor device including the detection circuit. A detection circuit ( | 07-15-2010 |
20100241777 | Power efficient interrupt detection - Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from the processor indicating whether the processor is currently processing an interrupt; a detection circuit for detecting an interrupt request and outputting an interrupt request signal to a data processing apparatus; disabling logic for disabling at least a portion of the detection circuitry; wherein in response to detecting the processor is currently processing an interrupt; the detection circuit is configured to detect a change in value of the interrupt signal caused by assertion of the interrupt signal indicating an interrupt request and to output an interrupt request signal to output circuitry in response to detecting the interrupt signal assertion; and in response to detecting the processor is not currently processing an interrupt; the disabling logic is configured to disable at least a portion of the detection circuit; and the detection circuit with the at least a portion disabled, is configured to output the interrupt signal as the interrupt request signal to the output circuitry. | 09-23-2010 |
20100293314 | COMPUTER SYSTEM AND METHOD OF CONTROLLING COMPUTER SYSTEM - CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction. | 11-18-2010 |
20110016246 | INFORMATION PROCESSING APPARATUS, INTERRUPT CONTROL DEVICE AND INTERRUPT CONTROL METHOD - An information processing device in which interrupts are generated when some events are occurred. The information processing device includes: an interrupt generating unit to generate an interrupt; an interrupt control unit to receive the generated interrupt, count an interrupt reception count per unit time, notify of the interrupt and delay, if the counted interrupt reception count per unit time exceeds a predetermined value, the interrupt notification; and an interrupt processing unit to process the notified interrupt. | 01-20-2011 |
20110099313 | SYSTEM AND METHOD FOR CONTROLLING INTERRUPTION OF A PROCESS IN ELECTRONIC EQUIPMENT BASED ON PRIORITY OF THE PROCESS, AND PROGRAM - System, method, and program to determine whether to interrupt a process, e.g., a write function, to carry out another process, e.g., a high priority read function, in a device that uses memory devices, e.g., eMMC devices, that use a single channel to carry out two different processes, e.g., write and read processes. | 04-28-2011 |
20110106993 | VIRTUAL MACHINE CONTROL DEVICE, VIRTUAL MACHINE CONTROL PROGRAM, AND VIRTUAL MACHINE CONTROL CIRCUIT - The interrupt level storing unit ( | 05-05-2011 |
20110119422 | SCHEDULING SYSTEM - The present invention provides a scheduling method for a data processing system comprising at least one physical CPU, and one or more virtual machines each assigned to one or more virtual CPUs, the method comprising: a first scheduling step in which one of said virtual machines is elected to run on said physical CPU; and a second scheduling step in which at least one of the virtual CPUs assigned to the elected virtual machine is elected to run on said physical CPU. The second scheduling step is applied to the virtual machine only. When a virtual machine instance is elected to run on a given CPU, the second level scheduling determines the virtual CPU instance to run. The second level scheduling is global and can cause a virtual CPU migration from one physical CPU to another. In order to ensure correct task scheduling at guest level, virtually equivalent (in terms of calculation power) virtual CPUs should be provided to the scheduler. This is achieved by the second level scheduler using a virtual CPU election criteria based on time statistics. | 05-19-2011 |
20110138094 | INFORMATION PROCESSING APPARATUS AND CLOCK SIGNAL CONTROLLING METHOD - An information processing apparatus includes an interrupting signal control device including a mask controller, the mask controller controlling whether or not to mask at least one interrupting signal serving as a trigger signal triggering a predetermined process; and a clock control device including an interrupting clock signal controller, the interrupting clock signal controller sends a clock signal to the interrupting signal control device when at least one interrupting signal is not masked, and stops sending the clock signal to the interrupting signal control device when at least one interrupting signal is masked. | 06-09-2011 |
20110161542 | EMULATION OF AN INPUT/OUTPUT ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER - Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic. | 06-30-2011 |
20110213906 | Interrupt Controller and Methods of Operation - Methods of operation and interrupt controllers for generating interrupt signals to a unit, which could enter an active mode and a non-active mode, are disclosed. The interrupt controllers have interrupt logic ( | 09-01-2011 |
20110238878 | METHOD AND APPARATUS FOR HANDLING AN INTERRUPT DURING TESTING OF A DATA PROCESSING SYSTEM - A method for handling an interrupt during testing of at least one logic block of a processor includes performing a test on at least one logic block of a processor; during the performing, receiving an interrupt; determining a progress status of the test in response to receiving the interrupt; and determining when the processor responds to an interrupt, wherein the determining when the processor responds to an interrupt is based on the progress of the test. | 09-29-2011 |
20110307641 | Lazy Handling of End of Interrupt Messages in a Virtualized Environment - Techniques enable reducing a number of intercepts performed by a hypervisor by reducing a number of End Of Interrupt (EOI) messages sent from a virtual central processing unit (CPU) to a virtual advanced programmable interrupt controller (APIC). The EOI path of the guest operating system running on the virtual CPU is altered to leave a marker indicating that the EOI has occurred. At some later time the hypervisor inspects the marker and lazily updates the virtual APIC state. | 12-15-2011 |
20120005387 | INTERRUPT BLOCKER - A method comprises maintaining, in a first electronic device, a list of one or more electronic devices associated with a user, receiving, in the first electronic device, a first command, in response to the first command, forwarding a command to block interrupts on one or more electronic devices on the list of electronic devices. Other embodiments may be described. | 01-05-2012 |
20120036299 | Secure Information Processing - Apparatus, systems, and methods may operate to receive from a requesting device, at a memory device, a request to access a memory domain associated with the memory device, and to deny, by the memory device, the request if the memory domain comprises any part of a secure domain, and the requesting device has not asserted a secure transfer indication. Additional operations may include granting the request if the memory domain comprises some part of the secure domain and the requesting device has asserted the secure transfer signal, or if the memory domain comprises only a non-secure domain. Additional apparatus, systems, and methods are disclosed. | 02-09-2012 |
20120137035 | COMPUTING DEVICE AND SERIAL COMMUNICATION METHOD OF THE COMPUTING DEVICE - A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC. | 05-31-2012 |
20130124769 | EMULATION OF AN INPUT/OUTPUT ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER - Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model, The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic. | 05-16-2013 |
20130145066 | ANALOG-TO-DIGITAL CONVERTER WITH EARLY INTERRUPT CAPABILITY - An early interrupt feature enables generation of interrupts prior to completion of an analog-to-digital conversion to be used in a processor PID calculation. Even though an analog-to-digital conversion is still in process, the PID application software can use the early interrupt time to begin execution of an interrupt service routine (ISR). The early interrupt can improve the throughput and response time of the PID control loop by overlapping the completion of the ADC conversion with the processor overhead associated with the interrupt request. A plurality of pipelined registers, each having substantially the same delay time as the pipelined stages of the ADC, are selectable to provided a delay time that may be used to generate an early interrupt, wherein the latency time between an ADC conversion and processing of an interrupt relating to that ADC conversion may thereby be shortened. | 06-06-2013 |
20130159575 | ADAPTIVE RECOVERY FOR PARALLEL REACTIVE POWER THROTTLING - Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for example, whether they execute tasks of the same job or receive power from the same converter. Once one of compute nodes in the group detects that a parameter (i.e., temperature, current, power consumption, etc.) has exceeded a first threshold, power throttling on all the nodes in the group may be activated. However, before deactivating power throttling, a plurality of parameters associated with the group of compute nodes may be monitored to ensure they are all below a second threshold. If so, the power throttling for all of the compute nodes is deactivated. | 06-20-2013 |
20130159576 | METHOD AND APPARATUS FOR CONTROLLING SYSTEM INTERRUPTS - A method and apparatus are provided for controlling system management interrupts is disclosed. An interrupt filter comprises a memory, a comparator and a logic circuit. The memory is adapted to contain a list indicating one or more devices with permission associated with an interrupt signal. The comparator is adapted to receive an interrupt signal containing type information from the one or more devices. The comparator is adapted to compare the interrupt type against the list to determine if the one or more devices is permitted to send the interrupt signal. The logic circuit blocks or passes the interrupt signal in response to the result of the comparison. | 06-20-2013 |
20130159577 | SEMICONDUCTOR DATA PROCESSING DEVICE, TIME-TRIGGERED COMMUNICATION SYSTEM, AND COMMUNICATION SYSTEM - The variation of the timing of starting interrupt processing in response to a timer interrupt request is reduced regardless of the condition of processing of other interrupts. A semiconductor data processing device incorporated in each of plural electronic control devices coupled to a network for time-triggered communication system is provided with a central processing unit, a communication control circuit and an interrupt control circuit. The communication control circuit has a local time timer for use in time-triggered communication and issues, based on time counting by the local time timer, a timer interrupt request for time-triggered communication. When a timer interrupt request for time-triggered communication is received, the interrupt control circuit performs control to cause the central processing unit to delay, by a predetermined reservation time, starting the interrupt processing to be performed in response to the timer interrupt request. | 06-20-2013 |
20130166803 | DEQUEUE OPERATION USING MASK VECTOR TO MANAGE INPUT/OUTPUT INTERRUPTIONS - A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset. | 06-27-2013 |
20130290586 | ACCESS DEVICE, COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND DATA ACCESS METHOD - The access device comprises a memory and a device controller configured to send and receive a data control right between the data recording device and a central controller provided in a host device. When having received a request to interrupt transfer of data from the central controller while data is being transferred from the data recording device, the device controller releases the data control right from the data recording device, and has the data recording device determine whether or not mismatching has occurred in file system management information for data stored in the memory. The device controller then returns the data control right to the data recoding device when it is determined that mismatching has occurred in the file system management information. The data recording device releases the data control right after eliminating the mismatching in the file system management information according to the returned data control right. | 10-31-2013 |
20130326102 | Virtualized Interrupt Delay Mechanism - A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register ( | 12-05-2013 |
20130339561 | PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT - A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. | 12-19-2013 |
20130339562 | PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT - A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. | 12-19-2013 |
20140082241 | METHOD AND AN APPARATUS FOR COHERENCY CONTROL - The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction. | 03-20-2014 |
20140095752 | INTERRUPT SUPPRESSION STRATEGY - The disclosed embodiments provide a system that suppresses interrupts to facilitate efficient use of a processor in a computer system. The system includes a node that transmits a first interrupt to the processor upon receiving a first packet for processing at the processor and disables subsequent interrupts to the processor during an interrupt-suppression state in the processor. The system also includes the processor, which processes the first packet upon receiving the first interrupt and transmits a first acknowledgment of the first packet to the node to enable the interrupt-suppression state. | 04-03-2014 |
20140108689 | INTERRUPT BLOCKER - A method comprises maintaining, in a first electronic device, a list of one or more electronic devices associated with a user, receiving, in the first electronic device, a first command, in response to the first command, forwarding a command to block interrupts on one or more electronic devices on the list of electronic devices. Other embodiments may be described. | 04-17-2014 |
20140164661 | Methods and Systems for Time Keeping in a Data Processing System - Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period. | 06-12-2014 |
20140201411 | DEFERRED INTER-PROCESSOR INTERRUPTS - A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI. | 07-17-2014 |
20140244877 | Emulating Level Triggered Interrupts of Physical Devices Assigned to a Virtual Machine - Systems and methods are disclosed for handling a level triggered interrupt generated by a device assigned to a virtual machine running on a host machine. An example system includes a host machine that hosts a virtual machine and a device coupled to the host machine. The device is assigned to the virtual machine and generates one or more interrupts. The example system also includes an interrupt handler that receives an interrupt generated by the device, masks the interrupt, injects the interrupt into the virtual machine, receives an indication that the virtual machine has attempted to access the device, and in response to the indication that the virtual machine has attempted to access the device, unmasks the interrupt from the device. | 08-28-2014 |
20140310439 | LOW LATENCY INTERRUPT WITH EXISTENCE OF INTERRUPT MODERATION - A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold. | 10-16-2014 |
20140317327 | SOFTWARE DEBOUNCING AND NOISE FILTERING MODULES FOR INTERRUPTS - Systems and methods for debouncing a signal line within a computer device are provided. The mechanical nature of physical buttons and switches oftentimes present irregular or noisy signals on a signal line when depressed by a user. Thus, noise and/or irregular waveforms may be present on a signal line that is monitored to produce interrupt signals, when deemed valid and genuine. In many embodiments given herein, debounce modules and techniques set a debounce interval timer and/or a noise filtering interval timer in which debounce modules and/or techniques may note whether the signal line is still asserted (e.g., possibly a genuine interrupt signal) during the debounce interval timer and stable (e.g., no further interrupts have fired) during the noise filtering interval timer. | 10-23-2014 |
20140344491 | LOCKING A SYSTEM MANAGEMENT INTERRUPT (SMI) ENABLE REGISTER OF A CHIPSET - Example embodiments disclosed herein relate to locking a system management interrupt (SMI) enable register of a chipset. Example embodiments include at least one contact configuration register to configure a contact of a chipset, and a contact SMI enable register of a chipset to store an enable value or a disable value. In example embodiments, the disable value stored in the contact SMI enable register is to prevent the chipset from providing an SMI request to a processor in response to an SMI signal received at the contact. Example embodiments further include locking the contact SMI enable register. | 11-20-2014 |
20140365697 | SLAVE DEVICE, MASTER DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD - In a communication system, a master device gives a data control to one of a plurality of slave devices, and stops controlling data transmission and reception in the master device. A dual-role device executes the data transmission and reception with the other slave devices according to the data control given by the master device. The master device transmits an abort signal to the dual-role device while data is being transmitted and received by the dual-role device according to the data control. The dual-role device receives the abort signal from the master device, and transmits an interrupt signal to the master device when no data is being transmitted or received. | 12-11-2014 |
20150089101 | MANAGING NETWORK INTERFACE CONTROLLER-GENERATED INTERRUPTS - Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets. | 03-26-2015 |
20150089102 | SOLID STATE DRIVES THAT CACHE BOOT DATA - Methods and structure for utilizing a Solid State Drive (SSD) to enhance boot time for a computer. The computer includes an SSD that stores a boot cache for an Operating System of a computer, a Hard Disk Drive that stores the Operating System, and a processor. The processor is able to load an interrupt handler that intercepts Input/Output requests directed to the Hard Disk Drive prior to loading a kernel of the Operating System. The interrupt handler is able to determine whether each intercepted request can be serviced with data from the boot cache, and to redirect a request to the SSD instead of the Hard Disk Drive if the request can be serviced with data from the boot cache. | 03-26-2015 |
20150143010 | METHOD AND APPARATUS FOR COMPENSATING FOR DELAY IN REAL-TIME EMBEDDED SYSTEM - In a real-time embedded system, if a higher-level interrupt having a higher priority than a lower-level interrupt being processed occurs, the lower-level interrupt is stopped from being processed and the higher-level interrupt is processed. Upon completion of the processing of the higher-level interrupt, delay information about the lower-level interrupt is recorded in a compensation timer register corresponding to the lower-level interrupt, and when the processing is stopped, the lower-level interrupt is restarted. Upon completion of the processing of the lower-level interrupt, the next period of the lower-level interrupt is adjusted based on the delay information recorded in the compensation timer register to compensate for the delay. | 05-21-2015 |
20150378943 | DELAYING FLOATING INTERRUPTION WHILE IN TX MODE - A computer implemented method and system for delaying a floating interruption while a processor is in a transactional-execution mode. A floating interruption mechanism can detect a floating interruption request for one or more floating interruption eligible processors. Based on each eligible processor being in TX mode, the method and system can delay, using a predetermined period of time, performing the floating interruption at a selected processor of the one or more of the processors. A first processor of the one or more processors can be selected based on the first processor exiting the transactional execution mode within the predetermined period of time. Based on the predetermined period of time expiring, the method and system can cause an interrupt to one of the plurality of processors, and the interrupt can cause the processor to abort a transaction. | 12-31-2015 |
20160077987 | DEFERRED INTER-PROCESSOR INTERRUPTS - A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred WI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI. | 03-17-2016 |
20160179716 | TIMER MANAGEMENT APPARATUS | 06-23-2016 |
20160188503 | VIRTUAL LEGACY WIRE - In an example, a system on chip (SoC) includes virtual legacy wire (VLW) functionality. The VLW signal virtualizes a physical interrupt existing in legacy systems to enable a peripheral to cause a processor to enter an interrupt handling routine relevant to the peripheral. The VLW interrupt is broadcast to all cores or agents within the SoC. However, to save power, if one or more agents are asleep when the interrupt occurs, the agents are not awakened to receive the interrupt. Rather, the VLW is broadcast with a mask to exclude those agents, and the state of those agents is stored in a register or buffer. Once a power management agent notifies the VLW broadcaster that an agent has newly awakened. The VLW interrupt is then re-broadcast, with a mask that excludes all but the newly-awakened agent. | 06-30-2016 |
20160378543 | IMPLEMENTING PSEUDO NON-MASKING INTERRUPTS BEHAVIOR USING A PRIORITY INTERRUPT CONTROLLER - A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto. | 12-29-2016 |