Class / Patent application number | Description | Number of patent applications / Date published |
710269000 | Handling vector | 59 |
20080235426 | Handling shared interrupts in bios under a virtualization technology environment - A custom interrupt service routine may be developed to handle interrupt requests that would not be appropriately handled by either of two operating system guests in a virtualization technology (VT) environment. In some embodiments, the custom interrupt service routine does not in any way interfere with the operation of the interrupt handling in a non-VT environment. | 09-25-2008 |
20090119434 | METHOD AND APPARATUS FOR BINDING SHADOW REGISTERS TO VECTORED INTERRUPTS - A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond to the interrupts. The exception vector considers the type of interrupt and the priority level of the interrupt when selecting the exception vector. Shadow set mapping logic is coupled to the vector generator. The mapping logic contains a number of fields that correspond to the different exception vectors that may be generated. The fields are programmable by kernel mode instructions, and contain data mapping each field to one of a number of shadow register sets. When an interrupt occurs, the vector generator generates a corresponding exception vector. In addition, the shadow set mapping logic looks at the field corresponding to the exception vector, and retrieves the data stored therein. The data is used to switch to one of the shadow register sets for use by an interrupt routine. Upon return from the interrupt routine, the previously used register set is selected. | 05-07-2009 |
20090172233 | METHODS AND APPARATUS FOR HALTING CORES IN RESPONSE TO SYSTEM MANAGEMENT INTERRUPTS - A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with at least one other processing core of the computer system in response to determining that the at least one processing core is halted. An associated system and machine readable medium are also disclosed. | 07-02-2009 |
20090204740 | Method and Device for Performing Switchover Operations in a Computer System Having at Least Two Execution Units - A method and device for performing switchover operations in a computer system having at least two execution units are provided, in which switchover units are included which are configured in such a way that they switch over between at least two operating modes, a first operating mode corresponding to a compare mode, and a second operating mode corresponding to a performance mode. An interrupt controller is provided and, furthermore, at least three memory areas are provided, and the access to the memory areas is implemented in such a way that one first memory area is assigned to at least one first execution unit, and one second memory area is assigned to the at least one second execution unit, and at least one third memory area is assignable to the at least two execution units. | 08-13-2009 |
20090271550 | Method and Apparatus for Adding a Communication Connection to a Vectored Group - Methods for adding a communication connection to a vectored group of communication connections and corresponding apparatuses are disclosed. | 10-29-2009 |
20100023667 | HIGH AVAILABILITY SYSTEM AND EXECUTION STATE CONTROL METHOD - A high availability system includes a first server computer for a first virtual computer and a first hypervisor and a second server computer for a second virtual computer and a second hypervisor. The first virtual computer executes a processing and the second virtual computer executes the processing behind from the first virtual computer. Information associated with an event is transmitted. The event provides an input to the first virtual computer. In the second hypervisor, a control unit performs, control based on the information to match the execution state of the second virtual computer and that of the first virtual computer, and control associated with the information, when the event associated with the information is predetermined one of an I/O completion interrupt from the first virtual storage and an interrupt handler call corresponding to the interrupt, after the interrupt from the second virtual storage corresponding to the interrupt is caught. | 01-28-2010 |
20100036987 | Apparatus and Methods for Speculative Interrupt Vector Prefetching - Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition. | 02-11-2010 |
20100191888 | Guest Interrupt Manager to Aid Interrupt Virtualization - In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt manager is configured to record the interrupt in a data structure in the memory system to ensure that the interrupt is delivered to the guest even if the guest is not active in the system at a time that the interrupt message is received. | 07-29-2010 |
20100191889 | MEMORY STRUCTURE TO STORE INTERRUPT STATE FOR INACTIVE GUESTS - In an embodiment, a system comprises a memory system configured to store a data structure. The data structure stores at least an interrupt request state for each destination in each of a plurality of guests executable on the system. The interrupt request state identifies which interrupts have been requested at the corresponding interrupt controller in the corresponding guest of the plurality of guests. A guest interrupt manager is coupled to receive an interrupt message targeted at a first destination in a first guest of the plurality of guests, and the guest interrupt manager is configured to update the interrupt request state in the data structure that corresponds to the first destination and the first guest. | 07-29-2010 |
20100274941 | Interrupt Optimization For Multiprocessors - Technologies are described herein for allocating interrupts within a multiprocessor computing system. Information communicated to an interrupt controller module can support allocating interrupt response resources so as to maintain processor affinity for interrupt service routines. This affinity can support caching efficiency by executing a specific interrupt handler on a processor that previously executed that interrupt handler. The caching efficiency may be balanced against the benefits of assigning execution of the interrupt hander to another processor that is currently idle or currently processing a lower priority task. | 10-28-2010 |
20100299472 | MULTIPROCESSOR SYSTEM AND COMPUTER PROGRAM PRODUCT - In a multiprocessor system including a plurality of processors, the processors execute, at a time of migration a task operating in own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and when an interrupt request to be received and executed by an interrupt handler accompanying the migration target task is generated during transmission of the migration target task, the transmitting task receives the interrupt request instead of the interrupt handler and starts the interrupt handler. | 11-25-2010 |
20100325329 | MULTIPROCESSOR SYSTEM, AND METHOD FOR SHARED USE OF DEVICES AMONG OPERATING SYSTEMS OF MULTIPROCESSOR SYSTEM - With a system in which a plurality of OSs run on a multi-core processor and which is based on a client-server approach where one OS performs device access on behalf of the other OSs, if a device is to be accessed from tasks on the plurality of OSs, there have been problems of a reduction in performance and an increase in design and manufacturing cost due to the necessity of providing proxy servers. | 12-23-2010 |
20110066783 | Secure Handling and Routing of Message-Signaled Interrupts - Encryption of interrupt vectors and authentication of device drivers prevents unauthorized modules from interfering with an interrupt handler. An operating system may encrypt an interrupt vector for a PCI device, initializing a Local Interrupt Controller of a CPU with the key to enable decryption of the interrupt vector, initializing a redirection table on an I/O Interrupt Controller of the CPU with the encrypted interrupt vector, and initializing the PCI device with an encrypted MSI vector for subsequent use in an interrupt request. The PCI device may raise an interrupt that can only be decrypted by the Local Interrupt Controller and used be used by the processor to handle the interrupt. The operating system may also authenticate a driver before executing a request to register, deregister or change an interrupt handler. An authentication code is sent from the OS to the device driver for use in any request. The request is executed only if the operating system determines that the authentication code in the request matches the authentication code stored by the operating system for that device driver. | 03-17-2011 |
20110106995 | DATA PROCESSING SYSTEM AND METHOD OF INTERRUPT HANDLING - A data processing system is provided which comprises at least two processing units ( | 05-05-2011 |
20110145462 | Implementing Gang Interrupts - A method includes receiving a first interrupt request from a first device instance of a plurality of device instances. The first interrupt request is requesting an interrupt of a processor. The method also includes updating a bit vector based on the first interrupt request. The bit vector comprises a plurality of bits representing an accumulation of interrupt requests. The method further includes generating a gang interrupt comprising the updated bit vector. The method also includes transmitting the gang interrupt to call a first device driver associated with the first interrupt request based on the bits in the bit vector. | 06-16-2011 |
20110153894 | INTERRUPT-HANDLING-MODE DETERMINING METHOD OF EMBEDDED OPERATING SYSTEM KERNEL - Provided is a method capable of providing an improved response property appropriate for the characteristics of a system by automatically choosing an interrupt handling mode used for each device. The method is a method in which the embedded operating system kernel determines a handling mode for all individual interrupts, the method includes: dividing interrupt handling modes into a first interrupt handling mode and a second interrupt handling mode which has a different process speed from the first interrupt handling mode, and variably determining a distribution ratio in which each of the interrupts are distributed to the first interrupt handling mode or to the second interrupt handling mode according to a predetermined process condition during boot-up. | 06-23-2011 |
20110246696 | Interrupt Vector Piggybacking - A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to branch to a piggyback interrupt handler corresponding to a piggyback interrupt vector. Based upon the determination, the hypervisor either branches to the piggyback interrupt handler or to an administrating interrupt handler that corresponds to the administrating interrupt vector. | 10-06-2011 |
20110320663 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used. | 12-29-2011 |
20110320664 | CONTROLLING A RATE AT WHICH ADAPTER INTERRUPTION REQUESTS ARE PROCESSED - The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions. | 12-29-2011 |
20110320665 | Managing Concurrent Serialized Interrupt Broadcast Commands In A Multi-Node, Symmetric Multiprocessing Computer - Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced. | 12-29-2011 |
20120131249 | METHODS AND SYSTEMS FOR AN INTERPOSER BOARD - In accordance with at least some embodiments, a system ( | 05-24-2012 |
20120144081 | Automatic Interrupt Masking in an Interrupt Controller - In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor. | 06-07-2012 |
20120191893 | SCALABLE CALL STACK SAMPLING - An interrupt is generated based on an event. Further, a thread is selected for monitoring. In addition, an interrupt handler captures information for the monitored thread. An affinity of the monitored thread is set such that the monitored thread runs only on a current processor without being able to migrate to a different processor. A sampler thread that runs on the current processor retrieves a call stack associated with a monitored thread after the affinity of the monitored thread has been set to the current processor. | 07-26-2012 |
20120198114 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used. | 08-02-2012 |
20120203947 | ON-DEMAND INTERRUPT VECTOR ALLOCATION BASED ON ACTIVITY DETECTION - A method and system for dynamically allocating interrupt vectors on demand. A computer system measures a rate of activities associated with an event. Based on the rate of activities, the computer system determines whether to allocate a dedicated interrupt vector to the event. The rate of activities can be an interrupt request (IRQ) rate. | 08-09-2012 |
20120226845 | Hardware interrupt processing circuit - A hardware interrupt processing circuit converts selected hardware interrupts to an interrupt vector having bits corresponding to the selected hardware interrupts. The hardware interrupt processing circuit includes circuit assemblies that correspond to the selected hardware interrupts. Each circuit assembly includes a detector circuit and a persistent capture circuit. The detector circuit is to output a pulse responsive to the corresponding selected hardware interrupt being asserted. The persistent capture circuit is triggered by the persistent capture circuit to output a corresponding bit of the interrupt vector until a ready signal has been asserted. | 09-06-2012 |
20120254492 | TRAFFIC CLASS BASED ADAPTIVE INTERRUPT MODERATION - An apparatus which comprises two or more moderation timers associated with an interrupt vector is presented. In one embodiment, the apparatus comprises two or more interrupt vectors and moderation timers are set with different interrupt rates. An interrupt vector logic unit sends an interrupt vector if there is an interrupt event from the queue associated with a moderation timer and the moderation timer expires. | 10-04-2012 |
20130103872 | COMPUTER APPARATUS AND METHOD FOR DISTRIBUTING INTERRUPT TASKS THEREOF - A computer apparatus and a method for distributing interrupt tasks thereof are provided. The computer apparatus has a plurality of CPUs and a chipset, and the chipset is electrically coupled to each of the CPUs. The chipset is configured for receiving an interrupt request sent from an external hardware device and judging whether or not a task type corresponding to the interrupt request has ever been performed by any one of the CPUs. If a judging result thereof is yes, the chipset assigns the interrupt request to the CPU that has ever performed the task type, so as to perform a corresponding interrupt task. | 04-25-2013 |
20130179616 | Partitioned Shared Processor Interrupt-intensive Task Segregator - Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors. | 07-11-2013 |
20130232288 | POSTING INTERRUPTS TO VIRTUAL PROCESSORS - Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure. | 09-05-2013 |
20130275639 | METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH MULTIPLE INTERRUPT VECTORS - Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device. | 10-17-2013 |
20130290587 | MICROCOMPUTER - A rewriting area of a flash ROM stores a main program, which includes a user vector with respect to each of interrupt factors that are different from each other in respect of types. The user vector with respect to a subject interrupt factor indicates an address, which stores an interrupt processing program that is executed when the subject interrupt factor arises. This user vector is stored in a predetermined address dedicated for the subject interrupt factor. The predetermined address of the user vector is enabled to be specified by an interrupt vector or interrupt changeover program, both of which are stored in a non-rewriting area of the flash ROM. Even when an address of the interrupt processing program is changed, the changed address is enabled to be indicated by using the user vector. | 10-31-2013 |
20140006668 | Performing Emulated Message Signaled Interrupt Handling | 01-02-2014 |
20140059262 | TASK SCHEDULING IN BIG AND LITTLE CORES - One aspect provides a method comprising: ascertaining an interrupt at an information handling device having two or more cores of different size; determining if the interrupt should be directed to one of a bigger core and a littler core based on a policy for scheduling interrupts; directing the interrupt to the little core if the interrupt does not qualify as an exception based on the policy for scheduling interrupts; and processing the interrupt on an appropriate core according the policy for scheduling interrupts. Other aspects are described and claimed. | 02-27-2014 |
20140068129 | METHOD FOR IMPLEMENTING SECURE DATA CHANNEL BETWEEN PROCESSOR AND DEVICES - Apparatuses, systems, and methods are directed to securely store, transfer, and/or process data especially sensitive data sent from input devices to processors. In one embodiment, sensitive data may be packaged with at least one interrupt vector to provide a single posted write transaction initiated by an input device. The single posted write transaction may then be directly sent to a predetermined memory block allocated from a processor. In response to the single posted write transaction, a memory decoder associated with the processor may generate an emulated message signaled interrupt (MSI) signal to invoke an interrupt handler or an interrupt service routine (ISR) to service the emulated MSI using interrupt data, including the sensitive data, retrieved from the predetermined memory block. Once the sensitive data are processed by the processor, they may be removed from the processor before the processor exits the interrupt handler. | 03-06-2014 |
20140089546 | INTERRUPT TIMESTAMPING - A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor. | 03-27-2014 |
20140108691 | HANDLING INTERRUPTS IN A MULTI-PROCESSOR SYSTEM - A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request. | 04-17-2014 |
20140136746 | TECHNIQUE FOR COMMUNICATING INTERRUPTS IN A COMPUTER SYSTEM - A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO). | 05-15-2014 |
20140173152 | TECHNIQUES FOR IDENTIFYING AND HANDLING PROCESSOR INTERRUPTS - A method for identifying and reporting interrupt behavior includes incrementing a counter when an interrupt signal is a designated type and is not received from an approved peripheral device, and performing a corrective action when the counter reaches a threshold value. In some embodiments, the designated type of the interrupt signal comprises a System Management Interrupt (SMI), which has the capability of halting operations at all processors within a system to execute associated instructions within a protected circumstance, resuming normal operations for each of the plurality of processors when the corrective action has been completed. In another embodiment, the corrective action includes creating a report identifying, within the same protected circumstance, the interrupt signal as an SMI. In some embodiments, the method performs a different corrective action when an interrupt signal is a designated type and is received from an approved peripheral device and decrements a counter. In some embodiments, the interrupt signal includes information indicating its source. | 06-19-2014 |
20140195709 | DELIVERING REAL TIME INTERRUPTS WITH AN ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER - Embodiments of apparatuses and methods for delivering real time interrupts with an APIC are disclosed. In one embodiment, an apparatus includes a local advanced programmable interrupt controller including a storage location to store a non-maskable interrupt vector. | 07-10-2014 |
20140207989 | ACCESS CONTROL TO A JOINTLY EXCLUSIVELY USABLE TRANSMISSION MEDIUM - A computing system and a method are specified. The computing system has a plurality of components which are configured to use a resource exclusively jointly, an activity monitoring unit which records a number of activities of a component on the resource and an interrupting unit which is configured to interrupt access of the components for use of the resource when the number of activities of the component reaches an activity threshold, so that an assignment strategy can assign the exclusively jointly used resource to another component. | 07-24-2014 |
20140281092 | SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS - Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed. | 09-18-2014 |
20140325110 | Enabling Virtualization Of A Processor Resource - In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed. | 10-30-2014 |
20140344492 | METHODS AND SYSTEMS FOR REDUCING SPURIOUS INTERRUPTS IN A DATA STORAGE SYSTEM - A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system. | 11-20-2014 |
20140351471 | HANDLING AND ROUTING INTERRUPTS TO VIRTUAL PROCESSES - An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory. | 11-27-2014 |
20140351472 | METHOD AND APPARATUS FOR INTERRUPT HANDLING - A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level. | 11-27-2014 |
20150067220 | REAL-TIME EMBEDDED SYSTEM - A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system. | 03-05-2015 |
20150074311 | SIGNAL INTERRUPTS IN A TRANSACTIONAL MEMORY SYSTEM - In some embodiments, a method includes executing an atomic transaction in a system having a transactional memory. The method includes receiving a signal interrupt during executing of the atomic transaction. The method includes storing a state of the signal interrupt to enable subsequent execution of the signal interrupt. The method includes returning to executing the atomic transaction until the atomic transaction is at least one of completed and aborted. The method includes after executing the atomic transaction is at least one of completed and aborted, determining whether the signal interrupt is received during executing of the atomic transaction. The method includes after determining that the signal interrupt is received during executing of the atomic transaction, retrieving the state of the signal interrupt. The method includes executing an interrupt handler for processing the signal interrupt and returning from executing of the atomic transaction. | 03-12-2015 |
20150089104 | METHOD FOR CONTROLLING MULTIPLE CAN INTERFACES THROUGH SINGLE SPI BUS - The disclosure is applied to a field of communication technologies and relates to a method for controlling multiple CAN interfaces through a single SPI bus. The method includes: when a reception mailbox of any of a plurality of CAN chips finishes receiving data on a CAN bus, triggering an interrupt by the CAN chip to deliver an interrupt signal; configuring the CAN chip triggering the interrupt through the SPI bus to disable interrupts in the CAN chip, so that the CAN chip exits the interrupt; inquiring the data received by the reception mailboxes of each CAN chip triggering the interrupt, reading the data into a memory buffer of an MCU through the SPI bus, setting a data identifier in the memory buffer of the MCU, and enabling interrupts in the CAN chip triggering the interrupt to allow the CAN chip triggering the interrupt to continue receiving data; and detecting whether the data identifier is present in the memory buffer of the MCU by an application program on the MCU, and copying the data from the memory buffer of the MCU to a memory buffer of the application program if the data identifier is present in the memory buffer of the MCU; otherwise, returning a result as a failure. The invention reads the data into the MCU upon interrupts generated by CAN chips, thereby reducing costs without affecting communication. | 03-26-2015 |
20150089105 | ELECTRONIC COMPUTING DEVICE AND REBOOT METHOD THEREOF - An electronic computing device comprises first and second nonvolatile memories. The second nonvolatile memory serves as a main memory of the device. A processor clears the second nonvolatile memory in response to shutdown command according to a setting reflecting a first user operation. A processor clears the second nonvolatile memory and loads the kernel from the first nonvolatile memory to the second nonvolatile memory in response to a boot command according to a condition of a second user operation detected by the processor regardless of the setting reflecting the first user operation. | 03-26-2015 |
20150120979 | METHOD OF CONTROLLING COMPUTER AND COMPUTER - A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control module for obtaining identifiers of the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores of the second processor core group that are associated with the kept identifiers, wherein the second processor core group receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, wherein the interrupt control module issues startup interrupt to the second processor core group. | 04-30-2015 |
20150127867 | SEMICONDUCTOR DEVICE - A microcomputer includes a central processing unit (CPU) and a data transfer controller (DTC). The data transfer controller (DTC) reads out data transfer information including transfer mode information from a storage device (RAM) or the like. The data transfer controller (DTC) analyzes the transfer mode information to change at least one of a transfer source address, a transfer destination address, the number of transfer operations, and data transfer information that is used next. | 05-07-2015 |
20160092382 | AVOIDING PREMATURE ENABLING OF NONMASKABLE INTERRUPTS WHEN RETURNING FROM EXCEPTIONS - A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed. | 03-31-2016 |
20160124875 | Method of Providing Timing Information for Interrupts - It is desirable for interrupt handling routines to be aware of the interrupt latency—the time between a interrupt request is received and the time when the interrupt service routine begins executing. A method is shown wherein the latency is measured by a dedicated counter and is available to the interrupt service routine. Alternately, a threshold may be set indicating the maximum acceptable latency and the interrupt service routine is signaled when said maximum is reached. | 05-05-2016 |
20160147679 | POSTED INTERRUPT ARCHITECTURE - An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt. | 05-26-2016 |
20160149580 | System and Method for Managing Pipelines in Reconfigurable Integrated Circuit Architectures - A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfacesand an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations isknown before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate timeswrite-enable inputs of configuration registers are disabled. | 05-26-2016 |
20160253222 | TECHNIQUES FOR PROCESSING CUSTOM EVENTS | 09-01-2016 |
20160378677 | EVENT SPECIFIC PAGE FAULTS FOR INTERRUPT HANDLING - Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution stack to cause a page fault on a known address after execution of an interrupt service routine. The page fault on the known address can be used to trigger instrumentation operations and also to return to the interrupted process. | 12-29-2016 |
20160378699 | IMPLEMENTING PSEUDO NON-MASKING INTERRUPTS BEHAVIOR USING A PRIORITY INTERRUPT CONTROLLER - A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a PNMI, executing a PNMI interrupt handler. If the received interrupt is a regular interrupt, the method further comprises reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further: if the mask flag indicates that regular interrupts are enabled, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing, a regular interrupt handler, and disabling interrupts in the processor; and if the mask flag indicates that regular interrupts are disabled, saving the interrupt vector for subsequent handling. | 12-29-2016 |