Entries |
Document | Title | Date |
20080209105 | Memory Controller, Control Method For Accessing Semiconductor Memory And System - A memory controller sequentially holds access requests including access addresses. A semiconductor memory includes a plurality of banks each having a plurality of pages. The memory controller decides page hit/page miss of the bank corresponding to each of the held access addresses. Further, the memory controller outputs an all-banks precharge command for performing a precharge operation of all the banks when deciding, based on an analysis of the successive access addresses, that outputting the all-banks precharge command results in improvement in access efficiency. It is possible to precharge the plural banks only by supplying the all-banks precharge command once, and therefore, in a case where the number of empty cycles for the insertion of a command is small, it is possible to supply the command efficiently to the semiconductor memory according to the states of the banks. | 08-28-2008 |
20080222345 | METHOD FOR ACCESSING MEMORY DATA - A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly. | 09-11-2008 |
20080235434 | Information processing method, and information processing system - A user-information managing unit controls reading of information stored in a user-information DB and a rule DB and writing of information to these databases. A customization processing unit receives a request for customizing rule information stored in the rule DB and, according to the request, customizes the rule information stored in the rule DB via the user-information managing unit. | 09-25-2008 |
20080313386 | MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD - A memory control apparatus and a memory control method are provided to enable an effective utilization of buffer memory in a system LSI by comprising buffer memory for temporarily storing data stored in memory, and comprising the processes of: receiving an instruction to the memory; transmitting a buffer memory security-dedicated use packet for securing the capacity of memory in the buffer memory required by the instruction on the basis of the received instruction; receiving a buffer memory validation signal corresponding to the transmitted buffer memory security-dedicated use packet; and executing the received instruction on the basis of the received buffer memory validation signal. | 12-18-2008 |
20090049229 | NONVOLATILE MEMORY DEVICE, METHOD OF WRITING DATA,AND METHOD OF READING OUT DATA - A nonvolatile memory device ( | 02-19-2009 |
20090049230 | FSA Context Switch Architecture for Programmable Intelligent Search Memory - Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata (FSA) and then programmed in PRISM for evaluating content with the search rules. PRISM architecture comprises of a plurality of programmable PRISM Search Engines (PSE) organized in PRISM memory clusters that are used simultaneously to search content presented to PRISM. A context switching architecture enables transitioning of PSE states between different input contexts. | 02-19-2009 |
20090089480 | SUPPORTING UN-BUFFERED MEMORY MODULES ON A PLATFORM CONFIGURED FOR REGISTERED MEMORY MODULES - A RDIMM enabled memory controller may support a UDIMM by way of a register chip and a PLL chip being implemented in operational relationship with a memory slot and a memory controller configured to support a RDIMM. The memory controller may drive address and control signals from the memory controller to the register chip, and the address and control signals may be provided from the register chip to the memory slot after one clock cycle, in response to the register chip latching onto the address and control signals from the memory controller on a rising clock edge. | 04-02-2009 |
20090138649 | Nonvolatile memory system and method of decentralizing the peak current in a nonvolatile memory system - A nonvolatile memory system has a controller chip connected to a memory medium and several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused by the operation and thereby improve the stability of the system. | 05-28-2009 |
20090144485 | PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE) - In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory. | 06-04-2009 |
20090150593 | DYNAMTIC STORAGE HIERARACHY MANAGEMENT - The invention relates to an architecture for optimization that can leverage the several advantages of flash memory or hard disk technology, while simultaneously compensating for associated disadvantages. In a system with a flash module and a hard disk, respective memory can be dynamically allocated as a function of demand, preference, or utilization of respective applications in order to optimize overall system performance. | 06-11-2009 |
20090172245 | DELIVERING SECURED MEDIA USING A PORTABLE MEMORY DEVICE - In some embodiments an interface of a portable memory device is used to store content information in a hidden memory region of the portable memory device. The interface is also used to store information in a visible memory region of the portable memory device. The information stored in the visible memory region allows the content information stored in the hidden memory region to be accessed. Other embodiments are described and claimed. | 07-02-2009 |
20090193175 | IDENTIFICATION OF AN ONBOARD MEMORY BUFFER DEVICE FROM A SYSTEM ADDRESS - Disclosed herein are techniques and methods for identifying a target onboard memory buffer device from a system address of a computer system. The techniques and methods can be employed in a computer system having a system controller, main memory having memory devices, and onboard memory buffer devices between the system controller and the main memory. One embodiment of the method obtains a system address that conveys a physical address within the computer system, decodes the system address to determine a target channel controller in the computer system, and identifies at least one memory buffer device associated with the target channel controller. | 07-30-2009 |
20090198868 | METHOD OF ACCESSING VIRTUAL STORAGE DEVICE THROUGH VIRTUAL DATA ROUTER - A method of accessing a virtual storage device through a virtual data router (VD router) is described. A virtual disk device on a controller may be accessed from various controllers through different paths based on asynchrony of data sending/receiving of a VD router. Moreover, the method is advantageous in having high access efficiency and consistency of data access via different paths at the same time. | 08-06-2009 |
20090276560 | Copyback Optimization for Memory System - In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory. | 11-05-2009 |
20090307410 | Memory controller - A memory controller provides interfaces for one or more thin film memory circuits. The controller may include an analog interface for one or more thin film memories. Such an analog interface may accept analog signals representative of an associated thin film memory's memory state, condition and sense the signal, and encode the signal into a digital value. | 12-10-2009 |
20090327577 | HYBRID STORAGE - Solid-state memory and mechanical disk memory can be used together to create a reliable storage unit with desirable performance characteristics. Initially, memory can be entered to the solid-state memory until filled as well as backed-up upon the mechanical disk memory. After the solid-state memory fills, less used information can be deleted from the solid-state memory yet retained upon the mechanical disk such that the less used information is not lost. To determine information use, an algorithm can be employed, such as an exponential algorithm. | 12-31-2009 |
20100100662 | ACCESSING APPARATUS AND METHOD USING THE SAME - An accessing apparatus and a method using the same are provided for accessing a non-volatile memory storage device by an external electronic device. The accessing apparatus includes a fixing unit, a transmission interface device, and a transmission media. The transmission interface device has a resilience power interface unit and a data interface unit. One end portion of the transmission media is electrically connected to the transmission interface device. When the external electronic device accesses the non-volatile memory storage device, the transmission media transmits power to the non-volatile memory storage device through the resilience power interface unit for driving the non-volatile memory storage device so that the transmission media is capable of transmitting either an accessing command or an accessing data to the data interface unit. | 04-22-2010 |
20100161876 | METHOD AND SYSTEM FOR DATA STRUCTURE MANAGEMENT - Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device. | 06-24-2010 |
20100268862 | RECONFIGURABLE PROCESSOR AND METHOD OF RECONFIGURING THE SAME - A technology for controlling a reconfigurable processor is provided. The reconfigurable processor dynamically loads configuration data from a peripheral memory to a configuration memory while a program is being executed, in place of loading all compiled configuration data in advance into the configuration memory when booting commences. Accordingly, a reduction in capacity of a configuration memory may be achieved. | 10-21-2010 |
20110252181 | FLEXIBLE WAY OF SPECIFYING STORAGE ATTRIBUTES IN A FLASH MEMORY-BASED OBJECT STORE - Approaches for performing a write operation on a solid state device (SSD). One or more containers are maintained on the solid state device. Each container is a logical grouping of objects independent from where the logical grouping of objects are physically stored on the solid state device. When a write operation is received at the SSD, the manner is which changes requested by the write operation should be stored are determined based on which container is being written. Containers provide a flexible approach for specifying attributes of how data should be stored and accessed which is independent from where the data is physically stored. Containers also have particular utility in performing load balancing and ensuring high availability and recovery. | 10-13-2011 |
20110252182 | Storage Device with Wireless Capability - Wireless USB device with security that allows the information to be automatically exchanged with the USB device wirelessly when it is in one location, and when in another location, only certain information can be so exchanged. | 10-13-2011 |
20130013845 | PERFORMING A COPY OPERATION ON A REPLICATED VIRTUAL CARTRIDGE - A replicated virtual cartridge is received into a media vault of a first virtual tape library and appears in a shadow library. The virtual cartridge is visible to a backup application via the shadow library to allow the backup application to perform a copy operation on the virtual cartridge. | 01-10-2013 |
20130036250 | METHOD AND APPARATUS TO MOVE PAGE BETWEEN TIERS - The thin provisioning storage system maintains migration history between the first and the second group which the unallocated pages of virtual volume would be allocated from, and updates on writes against storage areas of virtual volume having migration history. Before the storage controller determines to migrate data allocated in the first group to the second group, the storage controller checks the migration history and if the data stored in the first group has been previously migrated from the second group and is still maintained in the second group, the storage controller would change the allocation between the virtual volume and the first group to the second group for the data subject to migration and not perform the data migration. | 02-07-2013 |
20130111102 | SEMICONDUCTOR MEMORY DEVICES | 05-02-2013 |
20140019668 | MEMORY MANAGEMENT SYSTEMS AND METHODS FOR EMBEDDED SYSTEMS - Methods and systems are provided for managing static memory associated with software of an embedded system. The method includes performing one or more steps on one or more processors. The steps include selectively assigning memory objects to static memory segments based on access of the memory object by the software; managing data of the memory segments based on the assigning; and selectively restoring the data of the memory segments based on the managing. | 01-16-2014 |
20140068139 | DATA TRANSFER SYSTEM AND METHOD - A system includes: a memory controller; a memory module with memory blocks in communication with the memory controller; an input controller in communication with the memory controller, where the memory controller notifies the input controller of a Next Address To Write corresponding with a Next Memory Block To Write in the memory module, each input block contains an address to a next block, and data is written to the is Memory Block To Write at the Next Address To Write in the memory module; and an output controller in communication with the other controllers, receives a starting address from the input controller of a first memory block to read from the memory module, a starting address is a Next Address To Read from a Next Memory Block To Read in the memory module, and the memory controller compares the Next Address To Write with the Next Address To Read. | 03-06-2014 |
20150074326 | ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY - Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period. | 03-12-2015 |
20150324705 | LONG-TIME LOW-LATENCY QUANTUM MEMORY BY DYNAMICAL DECOUPLING - This disclosure relates to preserving a quantum state in a quantum memory. A controller of the quantum memory determines based on a characteristic of noise that causes deterioration of the quantum state a dynamical decoupling base sequence. The duration of the base sequence is shorter than or equal to an access latency time of the quantum memory to allow access to the quantum state within the access latency time. Further, the deterioration of the quantum state is bounded to an upper deterioration limit when the base sequence is repeatedly applied to the quantum system. This provides acceptable access times while simultaneously allowing long term storage of data in the quantum state with low error rates. Repeatedly applying the base sequence to the quantum system will first yield an increasing deterioration but that deterioration will eventually reach the upper limit. As a result, over time the error rates will not exceed that upper limit and the quantum state is stable. | 11-12-2015 |
20160162213 | METHODS FOR OPERATING A MEMORY ARRAY - Methods of operating memory arrays are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation are also described. | 06-09-2016 |
20160196064 | STORAGE CONTROL DEVICE, CONTROL METHOD AND STORAGE SYSTEM | 07-07-2016 |