Class / Patent application number | Description | Number of patent applications / Date published |
711120000 | Parallel caches | 41 |
20080235452 | DESIGN STRUCTURE FOR SHARED CACHE EVICTION - A design structure embodied in a machine readable storage medium for of designing, manufacturing, and/or testing for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores is provided. The design structure includes means for receiving from a processor core a request to load a cache line in the shared cache; means for determining whether the shared cache is full; means for determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and means for evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache. | 09-25-2008 |
20080313403 | APPARATUS, SYSTEM, AND METHOD FOR SELECTING AN INPUT/OUTPUT TAPE VOLUME CACHE - An apparatus, system, and method are disclosed for selecting an input/output tape volume cache (TVC). A history module maintains access history instances for a plurality of clusters. A request module receives an access request for a logical volume. An adjustment module weights the access history instances in favor of recent access history instances. A calculation module calculates an affinity of the logical volume for each cluster of the plurality of clusters. The calculation module may calculate the affinity of the logical volume for each cluster of the plurality of clusters using read/write/scratch granularity and an algorithm. Further, the calculation module may filter out clusters. A selection module selects a cluster TVC with a highest affinity as the TVC for the logical volume. | 12-18-2008 |
20090077318 | CACHE MEMORY - A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made. | 03-19-2009 |
20090132765 | DUAL CONTROLLER STORAGE APPARATUS AND CACHE MEMORY MIRROR METHOD THEREOF - A dual controller storage apparatus and a cache memory mirror method thereof are described. The storage apparatus includes a imaging environment module, a storage device, a first controller, and a second controller. The first controller has a virtual disk and a first cache memory. The second controller has a second cache memory. The present invent provides a imaging environment function to select the first or the second controller to serve an extranet according to the request of the extranet. If the imaging environment function selects the second controller, the data received from the extranet is written into the second cache memory. Communication between the second controller and the first controller is established, and the data of the second controller received from the extranet into the first cache memory and the virtual disk. | 05-21-2009 |
20090144501 | DATA STORAGE SYSTEM WITH COMPLEX MEMORY AND METHOD OF OPERATING THE SAME - A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile memory buffer unit and a flash memory unit. The non-volatile memory buffer unit includes a plurality of buffers arranged in parallel. The flash memory unit includes a plurality of data storage devices arranged in parallel to input and output data using a parallel method. In the method, a writing request is first classified into one of a plurality of grades according to a writing request frequency when there is a writing request and the writing requested data is stored in one of the non-volatile memory buffer unit and the flash memory unit according to the writing request frequency. | 06-04-2009 |
20090240888 | SYSTEM AND METHOD FOR OBSCURING HAND-HELD DEVICE DATA TRAFFIC INFORMATION - Increasing security for a hand-held data processing device with communication functionality where such a device includes an access-ordered memory cache relating to communications carried out by the device. The hand-held data processing device has a locked state that is entered by the device receiving or initiating a trigger. On occurrence of the trigger to enter the locked state the memory cache is reordered so as to disrupt the access-ordering of the cache to obscure device traffic information and thus increase the security of the device in the locked state. | 09-24-2009 |
20090313435 | Optimizing concurrent accesses in a directory-based coherency protocol - In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed. | 12-17-2009 |
20100146209 | METHOD AND APPARATUS FOR COMBINING INDEPENDENT DATA CACHES - Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change. | 06-10-2010 |
20100228919 | SYSTEM AND METHOD FOR PERFORMING RAPID DATA SNAPSHOTS - A storage system is provided that includes storage controller logic that performs rapid data snapshots. The storage controller logic may provide block-level access to a storage volume. The storage controller logic may store all data blocks of the storage volume in a first solid state memory cache. The storage controller logic may form a snapshot of the storage volume in a second solid state memory cache. The first and second solid state memory caches are addressable with a processor. The storage system may complete the snapshot extremely quickly because the processor may copy from one memory location to another between the first and second solid state memory caches. | 09-09-2010 |
20100268880 | Dynamic Runtime Modification of Array Layout for Offset - Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system. | 10-21-2010 |
20110022801 | APPARATUS, SYSTEM, AND METHOD FOR REDUNDANT WRITE CACHING - An apparatus, system, and method are disclosed for redundant write caching. The apparatus, system, and method are provided with a plurality of modules including a write request module, a first cache write module, a second cache write module, and a trim module. The write request module detects a write request to store data on a storage device. The first cache write module writes data of the write request to a first cache. The second cache write module writes the data to a second cache. The trim module trims the data from one of the first cache and the second cache in response to an indicator that the storage device stores the data. The data remains available in the other of the first cache and the second cache to service read requests. | 01-27-2011 |
20110258393 | MIRRORED CACHE PROTECTION - Methods of protecting cache data are provided. For example, various methods are described that assist in handling dirty write data cached in memory by duplication into other locations to protect against data loss. One method includes caching a data item from a data source in a first cache device. The data item cached in the first cache device is designated with a first designation. In response to the data item being modified by a data consumer, the designation of the data item in the first cache device is re-assigned from the first designation to a second designation, and the data item with the second designation is copied to a second cache device. | 10-20-2011 |
20110320719 | PROPAGATING SHARED STATE CHANGES TO MULTIPLE THREADS WITHIN A MULTITHREADED PROCESSING ENVIRONMENT - A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications network and without attempting to access any copy of the shared state data in a shared memory to which the parallel threads of execution are also coupled. Through the use of an on-chip communications network, changes to the shared state data may be communicated quickly and efficiently to multiple threads of execution, enabling those threads to locally update their local copies of the shared state. Furthermore, by avoiding attempts to access a shared memory, the interface to the shared memory is not overloaded with concurrent access attempts, thus preserving memory bandwidth for other activities and reducing memory latency. Particularly for larger shared states, propagating the changes, rather than an entire shared state, further improves performance by reducing the amount of data communicated over the on-chip communications network. | 12-29-2011 |
20120166728 | SYSTEMS AND METHODS FOR PERFORMING PARALLEL MULTI-LEVEL DATA COMPUTATIONS - Systems and methods for performing parallel multi-level data computations in a storage system are provided. One system includes a memory storing data, multiple caches, and a processor. The processor is configured to perform the method below. One method includes determining the total amount of data in the memory, dividing the amount of data by each cache capacity to determine the number of nodes needed for processing the data in the memory, and automatically creating the nodes. Here, the nodes form a tree structure including multiple levels where the lowest level includes a first number of nodes equal to the amount of data divided by the cache memory capacity. Also, each lowest level node is configured to process an amount of data equal to the cache memory capacity and each level above the lowest level is configured to include one or more nodes for receiving an input from lower level nodes. | 06-28-2012 |
20130042067 | FLUSHED DATA ALIGNMENT WITH PHYSICAL STRUCTURES - A method and system are disclosed herein for performing operations on a parallel programming unit in a memory system. The parallel programming unit includes multiple physical structures (such as memory cells in a row) in the memory system that are configured to be operated on in parallel. The method and system perform a first operation on the parallel programming unit, the first operation operating on only part of the parallel programming unit and not operating on a remainder of the parallel programming unit, set a pointer to indicate at least one physical structure in the remainder of the parallel programming unit, and perform a second operation using the pointer to operate on no more than the remainder of the parallel programming unit. In this way, the method and system may realign programming to the parallel programming unit when partial writes to the parallel programming unit occur. | 02-14-2013 |
20130138886 | SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD - A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area. | 05-30-2013 |
20130198457 | COMPUTER SYSTEM AND STORAGE CONTROL METHOD - The entirety or a part of free space of a second storage device included in a host computer is used as a cache memory region (external cache) outside of a storage apparatus. If Input/Output (I/O) in the host computer is Write, a Write request is transmitted from the host computer to a storage apparatus, the storage apparatus writes data associated with the Write request into a main cache that is a cache memory region included in this storage apparatus, and the storage apparatus writes the data in the main cache into a first storage device included in the storage apparatus. The storage apparatus writes the data in the main cache into an external cache included in the host computer. If the I/O in the host computer is Read, the host computer determines whether or not Read data as target data of the Read exists in the external cache. If a result of the determination is positive, the host computer reads the Read data from the external cache. | 08-01-2013 |
20130262767 | Concurrently Accessed Set Associative Overflow Cache - An apparatus for concurrently accessing a primary cache and an overflow cache, comprising a core logic unit configured to perform a first instruction that accesses the primary cache and the overflow cache in parallel, determine whether the primary cache stores a requested data, determine whether the overflow cache stores the requested data, and access a main memory when the primary cache and the overflow cache do not store the requested data, wherein the overflow cache stores data that overflows from the primary cache. | 10-03-2013 |
20140052917 | USING A SHARED LAST-LEVEL TLB TO REDUCE ADDRESS-TRANSLATION LATENCY - The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations. | 02-20-2014 |
20140173203 | Block Memory Engine - In an embodiment, a processor is disclosed and includes a cache memory and a memory execution cluster coupled to the cache memory. The memory execution cluster includes a memory execution unit to execute instructions including non-block memory instructions, and block memory logic to execute one or more block memory operations. Other embodiments are described and claimed. | 06-19-2014 |
20140258620 | METHOD, APPARATUS, SYSTEM FOR HANDLING ADDRESS CONFLICTS IN A DISTRIBUTED MEMORY FABRIC ARCHITECTURE - Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents. | 09-11-2014 |
20140297957 | OPERATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS - An operation processing apparatus includes an operation processing unit to perform an operation process using first data administered by the own operation processing apparatus and second data acquired from another operation processing apparatus; a main memory to store the first data; and a control unit to include a storing unit to store status of data indicating whether or not the first data is held by another operation processing apparatus and a indicating unit to indicate a transition between the status in which the first data is held by another operation processing apparatus and the status in which the first data is not held thereby, wherein when the indicating unit indicates that the first data is not held by another operation processing apparatus and a data acquisition request occurs for the first data, the control unit skips a process for referring to the status of use of the first data. | 10-02-2014 |
20140344521 | STORAGE CONTROL APPARATUS AND METHOD FOR DETECTING WRITE COMPLETION OF DATA - A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and updates a first counter to a value corresponding to the number of the transmitted write request packets. The communication control module writes a data block element associated with the write request packet to a cache memory, updates a third counter to a value corresponding to the number of the transmitted data block elements, and reflects the third counter to a second counter. The processor determines that the data block is written to the cache memory when the second counter reaches the first counter after all write request packets are transmitted. | 11-20-2014 |
20150046650 | Flexible Configuration Hardware Streaming Unit - A processor having a streaming unit is disclosed. In one embodiment, a processor includes a streaming unit configured to load one or more input data streams from a memory coupled to the processor. The streaming unit includes an internal network having a plurality of queues configured to store streams of data. The streaming unit further includes a plurality of operations circuits configured to perform operations on the streams of data. The streaming unit is software programmable to operatively couple two or more of the plurality of operations circuits together via one or more of the plurality of queues. The operations circuits may perform operations on multiple streams of data, resulting in corresponding output streams of data. | 02-12-2015 |
20150121008 | Write Cache Destaging - Disclosed is a system for controlling write actions to a plurality of data storage devices, the system comprising a plurality of write caches, wherein each cache is associated with a set of said data storage devices; and a controller adapted to issue write permissions to said data storage devices, said write permissions including a permission to perform a data destage operation from a cache to a data storage device; wherein each cache has a first performance score expressed as the difference between the number of data destage operations said cache has in flight and the maximum number of data destage actions said cache is permitted to issue in parallel; and wherein the controller is adapted to offer a data destage operation permission to the cache in said plurality of caches associated with the highest first performance score. | 04-30-2015 |
20150127907 | METHOD, APPARATUS AND SYSTEM FOR HANDLING CACHE MISSES IN A PROCESSOR - In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed. | 05-07-2015 |
20150134911 | DISTRIBUTED CACHE ARRANGEMENT - Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache). | 05-14-2015 |
20150134912 | SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD - A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area. | 05-14-2015 |
20150331635 | Real Time Cloud Bursting - A method and system for real-time cloud bursting is provided. The method and system are directed to extending a data center with cloud computing resources by decoupling computing resources and storage devices in a virtualized data center, and booting the decoupled computing resources in a staged process while storage devices are divided and prioritized into components. Data and boot instructions are re-routed and cached as needed through a proxy system. | 11-19-2015 |
20150331801 | CACHING OF LOOK-UP RULES BASED ON FLOW HEURISTICS TO ENABLE HIGH SPEED LOOK-UP - In one embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code including computer readable program code configured to initialize an internal look-up table cache provided internally to a switching processor, the internal look-up table cache being configured to store a plurality of look-up entries and being organized into at least three segments: a persistent flows entries segment, a non-persistent flows entries segment, and an access control list (ACL) segment. Each look-up entry relates to a traffic flow which has been or is anticipated to be received by a switching processor configured to access the internal look-up table cache. The computer readable program code is also configured to manage the internal look-up table cache to store entries relating to a particular segment type into a corresponding segment of the internal look-up table cache. | 11-19-2015 |
20150347308 | RECONFIGURABLE FETCH PIPELINE - A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access. | 12-03-2015 |
20150363321 | PARALLEL LOOKUP IN FIRST AND SECOND VALUE STORES - A data processing apparatus | 12-17-2015 |
20160026409 | STORAGE SYSTEM AND METHOD FOR MIGRATING THE SAME - The present invention provides a storage system capable of performing data migration without stopping the IO access from a host computer, without having to copy data in an external connection storage subsystem to a migration destination storage subsystem. A configuration information of a migration source volume in a migration source storage subsystem is migrated to the migration destination storage subsystem, and during migration, cache memories of the respective subsystems are used to duplicate and store write data from the host computer, and the migration destination storage subsystem reflects the write data to the external connection storage subsystem. Reading of data is also performed by the migration destination storage subsystem. | 01-28-2016 |
20160034395 | Method and Apparatus for Ensuring Data Cache Coherency - A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality. | 02-04-2016 |
20160041912 | DATA PROCESSING DEVICE - The disclosed invention enables the operation of an MIMD type, an SIMD type, or coexistence thereof in a multiprocessor system including a plurality of CPUs and reduces power consumption for instruction fetch by CPUs operating in the SIMD type. A plurality of CPUs and a plurality of memories corresponding thereto are provided. When the CPUs fetch instruction codes of different addresses from the corresponding memories, the CPUs operate independently (operation of the MIMD type). On the other hand, when the CPUs issue requests for fetching an instruction code of a same address from the corresponding memories, that is, operate in the SIMD type, the instruction code read from one of the memories by one access is parallelly supplied to the CPUs. | 02-11-2016 |
20160041917 | SYSTEM AND METHOD FOR MIRRORING A VOLATILE MEMORY OF A COMPUTER SYSTEM - A system and method for mirroring a volatile memory to a CPIO device of a computer system is disclosed. According to one embodiment, a command buffer and a data buffer are provided to store data and a command for mirroring the data. The command specifies metadata associated with the data. The data is mirrored a non-volatile memory of the CPIO device based on the command. | 02-11-2016 |
20160110284 | DISTRIBUTED CACHE FRAMEWORK - A system includes a database that stores data on one or more memory devices and a business object layer that receives a request for data associated with a user stored on the database. The system includes a first cache that reads and stores the requested data from the database in response to the request from the business object layer, where the first cache is partitioned into different segments and the different segments are stored across multiple different computing devices. The system includes a second cache that reads and stores the requested data from the first cache. The business object layer filters and applies business logic to the data before the second cache reads the requested data from the first cache. The second cache is stored on a single computing device that received the request. The business object layer delivers the requested data from the second cache. | 04-21-2016 |
20160124854 | INCREASED BANDWIDTH OF ORDERED STORES IN A NON-UNIFORM MEMORY SUBSYSTEM - A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store. | 05-05-2016 |
20160154605 | USE OF FLASH CACHE TO IMPROVE TIERED MIGRATION PERFORMANCE | 06-02-2016 |
20160162404 | MEMORY MODULE WITH LOCAL SYNCHRONIZATION - A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in groups, each group including at least one memory device, while the data buffer control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits, a respective buffer circuit corresponding to a respective group of memory devices. The plurality of buffer circuits are distributed across a surface of the memory module such that each data buffer control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits include clock regeneration circuits to regenerate a clock signal received from the module control device and to provide regenerated clock signals to respective groups of memory devices. | 06-09-2016 |
20160188466 | CACHING FOR HETEROGENEOUS PROCESSORS - A multi-core processor providing heterogeneous processor cores and a shared cache is presented. | 06-30-2016 |