Class / Patent application number | Description | Number of patent applications / Date published |
711140000 | Cache pipelining | 25 |
20080235459 | PROCESSOR, METHOD, AND DATA PROCESSING SYSTEM EMPLOYING A VARIABLE STORE GATHER WINDOW - A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads. | 09-25-2008 |
20080307166 | Store Handling in a Processor - In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load. | 12-11-2008 |
20090006763 | Arrangement And Method For Update Of Configuration Cache Data - An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory ( | 01-01-2009 |
20090063779 | CACHE MEMORY AND A METHOD FOR SERVICING ACCESS REQUESTS - A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages. | 03-05-2009 |
20100095071 | Cache control apparatus and cache control method - A cache control apparatus includes a plurality of processing units, each performing, in a mutually independent manner, corresponding processing that constitutes a pipeline process of outputting cache data with respect to requests belonging to threads, holding units, each being disposed corresponding to one of the processing units and each holding a thread-specific valid bit that corresponds to a request under processing in corresponding processing unit and that indicates whether a pipeline process for a thread to which the request under processing belongs is stalled, a storing unit that sequentially stores in a register a request that is under processing in a processing unit corresponding to a holding unit holding a valid bit that indicates pipeline process stalling, and a feeding unit that determines a priority for the request stored in the register by the storing unit and a request newly input from outside, and feeds either one of stored request and newly input request to the processing units. | 04-15-2010 |
20110302373 | OPERATION APPARATUS, CACHE APPARATUS, AND CONTROL METHOD THEREOF - An apparatus comprising first holding units each of which includes first nodes connected in series and shifts first data in each first node in a first direction, second holding units each of which includes second nodes connected in series and shifts second data in each second node in a second direction is provided. Each first node corresponds to at least one of the second nodes. The apparatus further comprises an operation unit which executes, for a node of interest which is a first node, an operation using first data in the node of interest, and second data in at least one of the second nodes to which the node of interest corresponds, and an input unit which inputs, in parallel, the first data to at least two out of the first holding units, and serially inputs the second data to at least two out of the second holding units. | 12-08-2011 |
20110320735 | DYNAMICALLY ALTERING A PIPELINE CONTROLLER MODE BASED ON RESOURCE AVAILABILITY - A mechanism for dynamically altering a request received at a hardware component is provided. The request is received at the hardware component, and the request includes a mode option. It is determined whether an action of the request requires an unavailable resource and it is determined whether the mode option is for the action requiring the unavailable resource. In response to the mode option being for the action requiring the unavailable resource, the action is automatically removed from the request. The request is passed for pipeline arbitration without the action requiring the unavailable resource. | 12-29-2011 |
20110320736 | PREEMPTIVE IN-PIPELINE STORE COMPARE RESOLUTION - A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request. | 12-29-2011 |
20120191919 | METHOD FOR MANAGING MULTI-LAYERED DATA STRUCTURES IN A PIPELINED MEMORY ARCHITECTURE - A method for managing multi-layered data structures in a pipelined memory architecture, comprising the steps of:—providing a multi-level data structure where each level corresponds to a memory access;—storing each level in a separate memory block with respect to the other levels. In this way, a more efficient usage of memory is achieved. | 07-26-2012 |
20120198177 | SELECTIVE MEMORY ACCESS TO DIFFERENT LOCAL MEMORY PORTS AND METHOD THEREOF - A data processor is disclosed that definitively determines an effective address being calculated and decoded will be associated with an address range that includes a memory local to a data processor unit, and will disable a cache access based upon a comparison between a portion of a base address and a corresponding portion of an effective address input operand. Access to the local memory can be accomplished through a first port of the local memory when it is definitively determined that the effective address will be associated with an address range. Access to the local memory cannot be accomplished through the first port of the local memory when it is not definitively determined that the effective address will be associated with the address range. | 08-02-2012 |
20130042075 | SYSTEM AND METHOD FOR SLICE PROCESSING COMPUTER-RELATED TASKS - A computer-based systems and methods for task processing in a computing device are provided. A method includes the step of entering a slice mode for at least one task, the entering comprising reserving one or more portions of a cache memory to yield a slice cache memory for the task. The method also includes the step of storing a slice in the slice cache memory, wherein the slice comprises at least one program residing in at least one memory space outside of the slice cache memory and associated with the at least one task. The method further includes the step of processing the at least one task utilizing the at least one program by accessing the at least one slice cache memory until the slice mode is terminated. | 02-14-2013 |
20130061002 | PERFORMANCE OPTIMIZATION AND DYNAMIC RESOURCE RESERVATION FOR GUARANTEED COHERENCY UPDATES IN A MULTI-LEVEL CACHE HIERARCHY - A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit. | 03-07-2013 |
20130080708 | DYNAMIC MODE TRANSITIONS FOR CACHE INSTRUCTIONS - A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter, selecting one of the plurality of requests as a selected request, the selected request having been provided by a first state machine, determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache, determining that the location in the cache is unavailable, and replacing the mode with a modified mode that only includes the second step. | 03-28-2013 |
20130145103 | REDUCING SEQUENCE CACHE LATCH CONTENTION IN A DATABASE SYSTEM - In a database system having a plurality of concurrently executing session processes, the method commences by establishing a master list of sequences, the master list comprising a plurality of sequence objects which in turn define a sequence of values used for numbering and other identification within the database system. To reduce sequence cache latch access contention, multiple tiers of latches are provided. Methods of the system provide a first tier having a first tier “global” latch to serialize access to the master list such that at any point in time, only one of the concurrently executing session processes is granted access to the master list, from which master list are allocated sequences on demand. A second tier of latches is provided, the second tier having multiple second tier latches to serialize access to corresponding allocated sequences of values such that at any point in time, only one of the concurrently executing session processes is granted access to the allocated sequence. The multiple tiers serve to reduce the likelihood of contention to the first tier latch. | 06-06-2013 |
20140082298 | OS Friendly Microprocessor Architecture - The present invention is a microprocessor architecture for efficiently running an operating system. The improved architecture provides higher performance, improved operating system efficiency, enhanced security, and reduced power consumption. | 03-20-2014 |
20140082299 | PRIORITIZING REQUESTS TO MEMORY - According to an embodiment, a computer system for cache management includes a processor and a cache, the computer system configured to perform a method including receiving a first store request for a first address in the cache and receiving a first fetch request for the first address in the cache. The method also includes executing the first store request and the first fetch request, latching the first store request in a store write-back pipeline in the cache, detecting, in the processor, a conflict following execution of the first store request and the first fetch request and receiving the first store request from a recycle path including the store write-back pipeline and executing the first store request a second time. | 03-20-2014 |
20140089598 | METHODS AND APPARATUS FOR MANAGING PAGE CROSSING INSTRUCTIONS WITH DIFFERENT CACHEABILITY - An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached. | 03-27-2014 |
20140089599 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor includes a cache write queue configured to store write requests, based on store instructions directed to a cache memory issued by an instruction issuing unit, into entries provided with stream_wait flag, and to output a write request including no stream_wait flag set thereon, from among the stored write requests, to a pipeline operating unit which performs pipeline operation with respect to the cache memory, the cache write queue being further configured to determine, when a stream flag attached to the store instruction is set, that there will be succeeding store instruction directed to a data area same as that accessed by the store instruction, to set the stream_wait flag so as to store the write request into the entry, to merge the write requests based on the store instructions, directed to the same data area, into a single write request, and then to hold the merged write request. | 03-27-2014 |
20140108743 | STORE DATA FORWARDING WITH NO MEMORY MODEL RESTRICTIONS - Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a largest contiguous granularity of data returned from a cache. Another aspect includes determining that the load address matches at least one block address. Another aspect includes, based on determining that there is an address match, reading a data block from a buffer register and sending the data to satisfy the load request; comparing a unique set id of the data block to the set id of the matching address after sending the data block; based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address to no store-forwarding and rejecting the load request. | 04-17-2014 |
20140136796 | ARITHMETIC PROCESSING DEVICE AND METHOD FOR CONTROLLING THE SAME - An arithmetic processing device includes a cache memory, a first controller configured to control the cache memory and a second controller assigned a non-cache space to be accessed without use of the cache memory, wherein, when a condition, that out-of-order processing of a first and a second access requests for the non-cache space is possible and access targets of the first and second access requests are the same, is satisfied, the first controller issues the second access request to the second controller without waiting for a completion notification from the second controller with respect to the first access request previously issued to the second controller, and when the condition is not satisfied, the first controller issues the second access request to the second controller after waiting for a completion notification from the second controller with respect to first access request previously issued to the second controller. | 05-15-2014 |
20140244939 | TEXTURE CACHE MEMORY SYSTEM OF NON-BLOCKING FOR TEXTURE MAPPING PIPELINE AND OPERATION METHOD OF TEXTURE CACHE MEMORY - A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result. | 08-28-2014 |
20140331012 | SYSTEM AND METHOD OF ARBITRATING CACHE REQUESTS - This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof. | 11-06-2014 |
20150032969 | COHERENCY CONTROL MESSAGE FLOW - A coherent memory system includes a plurality of level 1 cache memories | 01-29-2015 |
20150074356 | PROCESSOR WITH MEMORY-EMBEDDED PIPELINE FOR TABLE-DRIVEN COMPUTATION - A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction. | 03-12-2015 |
20160004651 | SYSTEM AND METHOD OF ARBITRATING CACHE REQUESTS - This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof. | 01-07-2016 |