Entries |
Document | Title | Date |
20080215821 | DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION UTILIZING AN IN COHERENCY STATE - A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain. | 09-04-2008 |
20080235460 | APPARATUS AND METHOD FOR INFORMATION PROCESSING ENABLING FAST ACCESS TO PROGRAM - A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table. | 09-25-2008 |
20080244192 | MULTIPROCESSOR SYSTEM - A multiprocessor system includes cache memories each of which is provided in correspondence with one of processor cores and includes a tag storage unit configured to store validity information representing whether a cache line as a unit to store data is valid, update information representing whether data in the cache line has been rewritten, and address information of the data in the cache line, a shared memory shared by the processor cores, and an arbitration circuit configured to arbitrate access requests from the processor cores to the shared memory and send the arbitrated access request to the cache memories. Each cache memory includes a violation detection circuit configured to detect a violation access by comparing the information in the tag storage unit with the access request from the arbitration circuit. | 10-02-2008 |
20080256303 | Cache memory - An apparatus for processing data comprises a cache memory having a plurality of cache rows each operable to store a cache line of data values, a memory management unit responsive to a page table entry to control access to a corresponding group of memory addresses forming a memory page, and a cache controller coupled to said cache memory and responsive to a cache miss to trigger a line fill operation to store data values into a cache row. The cache controller is responsive to a cache line size specifier associated with at least one page table entry to vary the number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier. Accordingly, by associating cache line size specifiers with page table entries, the number of data values to be stored in a line fill operation can be controlled on a memory page basis, which is advantageous because data values within the same page of memory are likely to be subject to similar types of access behaviour in the cache. Additionally, controlling cache line size on a page basis is more efficient, in terms of computation and storage, than controlling cache line size on a cache row or virtual address basis. | 10-16-2008 |
20080294849 | Recording controller and recording control method - In a recording controller, an invalidation-request issuing unit, when a second data is recorded on a recording location for a first data that is to be recorded in a memory and a third data corresponding to the second data is recorded in the cache, issues an invalidation request for invalidating the third data, and a notifying unit, when the third data is invalidated, outputs data for identifying a recording request for the first data to an output source of the recording request, and notifies to the output source that recording of the first data is completed. | 11-27-2008 |
20080313410 | Promoting a Line from Shared to Exclusive in a Cache - Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache. | 12-18-2008 |
20080313411 | SYSTEM CONTROLLER AND CACHE CONTROL METHOD - A processor module having a cache device and a system controller having a copy TAG2 of a tag of the cache device configure a system to which a protocol representing the states of a data block of the cache device by six states, that is, an invalid state I, a shared state S, an exclusive state E, a modified state M, a shared modified state O, and a writable modified state W can be applied. In order to implement the concept, information about a new state in a cache device of a requester is included in a reply packet from the cache device for transmitting the data block. After the completion of the snooping process of the TAG2 until the reception of the reply packet from the cache device for transmitting the data block and the determination of the next state, an object data block is locked in the TAG2. | 12-18-2008 |
20080320235 | Processor cache management with software input via an intermediary - Software assists a processor subsystem in making cache replacement decisions by providing an intermediary with information regarding how instructions and/or data of a working set are expected to be used and accessed by the software. The intermediary uses this information along with its knowledge of system requirements, policy and the cache configuration to determine cache usage and management hints for the working sets. The cache usage and management hints are passed by the intermediary to the processor subsystem. | 12-25-2008 |
20090024801 | METHOD AND SYSTEM TO DETECT A CACHED WEB PAGE - A method and system to determine whether a web page has been cached is provided. An example system comprises a cookie generator, a cookie distributor, and a cookie evaluator. The cookie distributor may be configured to provide the code to a client system, in response to a request for web content from the client system. A value of the code to be updated at the client system in response to the client system initiating a request for the web content. The cookie evaluator may be configured to compare a value of the code to the default value. The cached status detector may be configured to use a result of the comparing to determine a cached status of the web content, the cached status to indicate whether the web content has been cached by the client system. | 01-22-2009 |
20090037667 | Electronic device data access system and method - An electronic device data access method comprising sharing, by an operating system and a pre-boot environment module, data stored in a hard disk drive in the electronic device and accessing the data using a block location list identifying a storage location for each portion of the stored data. | 02-05-2009 |
20090063782 | Method for Reducing Coherence Enforcement by Selective Directory Update on Replacement of Unmodified Cache Blocks in a Directory-Based Coherent Multiprocessor - Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors. | 03-05-2009 |
20090083496 | Method for Improved Performance With New Buffers on NUMA Systems - A method and apparatus are provided for managing buffer allocations in a multiple processor computer system. A cache invalidate command is issued in response to a buffer allocation from a remote processor, wherein the cache lines present in the buffer allocation must be invalidated by the remote processor before data can be stored therein. The remote invalidate command specifies multiple cache lines to support invalidation of the specified multiple cache lines in a single communication. Following confirmation of invalidation of the cache lines, the processing to which the buffer has been allocated can write data to the invalidated cache lines. | 03-26-2009 |
20090083497 | MULTI-MEDIA PROCESSOR CACHE WITH CAHE LINE LOCKING AND UNLOCKING - The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line. | 03-26-2009 |
20090094418 | SYSTEM AND METHOD FOR ACHIEVING CACHE COHERENCY WITHIN MULTIPROCESSOR COMPUTER SYSTEM - An embodiment of a multiprocessor computer system comprises main memory, a remote processor capable of accessing the main memory, a remote cache device operative to store accesses by said remote processor to said main memory, and a filter tag cache device associated with the main memory. The filter cache device is operative to store information relating to remote ownership of data in the main memory including ownership by the remote processor. The filter cache device is operative to selectively invalidate filter tag cache entries when space is required in the filter tag cache device for new cache entries. The remote cache device is responsive to events indicating that a cache entry has low value to the remote processor to send a hint to the filter tag cache device. The filter tag cache device is responsive to a hint in selecting a filter tag cache entry to invalidate. | 04-09-2009 |
20090113138 | Combined Response Cancellation for Load Command - A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption. | 04-30-2009 |
20090132768 | Cache memory system - Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for identifying whether or not a region of the cache memory contains data that has been accessed from the cache memory by an external device. | 05-21-2009 |
20090144507 | APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS - An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid. | 06-04-2009 |
20090172298 | CACHED DIRTY BITS FOR CONTEXT SWITCH CONSISTENCY CHECKS - Embodiments of an invention using cached dirty bits for context switch consistency checks are disclosed. In one embodiment, a processor includes control logic and a cache. The control logic is to cause a consistency check to be performed on a subset of a plurality of state components during a first context switch. The cache is to store a dirty entry for each state component to indicate whether the corresponding state component is included in the subset. | 07-02-2009 |
20090193199 | Method for Increasing Cache Directory Associativity Classes Via Efficient Tag Bit Reclaimation - In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an memory space. An amount of memory that is in an actually configured portion of the memory space is determined. A minimum number of bits necessary to address each memory location in the actually configured portion of the memory space is determined. Each address tag is configured in each associativity class to include the minimum number of bits necessary to address each memory location in the actually configured portion of the memory space. The cache directory is configured to include a maximum number of associativity classes per line in the cache directory. | 07-30-2009 |
20090292883 | Apparatus, Method, and Computer Program Product for Memory Validation Operations in a Memory - In accordance with an example embodiment of the present invention, an apparatus, comprising a first memory, wherein the first memory is configured to store data related to a first event, store a memory validation indicator related to a second event, and a second memory, wherein the second memory is configured to store a memory validation indicator related to the first event, wherein the first memory validation is based at least in part on the second memory validation indicator. | 11-26-2009 |
20090300294 | UTILIZATION OF A STORE BUFFER FOR ERROR RECOVERY ON A STORE ALLOCATION CACHE MISS - A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination. | 12-03-2009 |
20090327615 | Access Speculation Predictor with Predictions Based on a Scope Predictor - An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary. | 12-31-2009 |
20100106915 | POLL BASED CACHE EVENT NOTIFICATIONS IN A DISTRIBUTED CACHE - Systems and methods that supply poll based notification system in a distributed cache, for tracking changes to cache items. Local caches on the client can employ the notification system to keep the local objects in sync with the backend cache service; and can further dynamically adjust the “scope” of notifications required based on the number and distribution of keys in the local cache. The server can maintain the changes in an efficient fashion (in blocks) and returns the changes to clients that perform the appropriate filtering. Notifications can be associated with a session and/or an application. | 04-29-2010 |
20100115207 | METHOD AND SYSTEM FOR IMPLEMENTING MULTIUSER CACHED PARAMETERIZED CELLS - An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data. | 05-06-2010 |
20100122038 | METHODS AND APPARATUSES FOR IMPROVING SPECULATION SUCCESS IN PROCESSORS - Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue. | 05-13-2010 |
20100131718 | MULTIPROCESSOR SYSTEM - A multiprocessor system includes cache systems arranged in correspondence with processor cores, and each including a cache memory which stores a cache line, a shared memory shared by the processor cores, and an arbiter configured to arbitrate access requests sent from the cache systems to the shared memory, and configured to send the arbitrated access request to the shared memory and the cache systems. The cache system includes a determination circuit configured to determine an access state using line information and the access request sent from the arbiter, a flag circuit configured to set a flag for each cache line based on a determination result of the determination circuit, and a control circuit configured to confirm the flag when a read access or a write access is made to a cache line held in the cache memory, and configured to detect a violation access based on the flag. | 05-27-2010 |
20100138614 | Compression Status Bit Cache And Backing Store - One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data. | 06-03-2010 |
20100153657 | OPERATION OF AN INPUT/OUTPUT LINK - Included are embodiments for facilitating operation of an input/output (I/O) link. At least one embodiment of a method includes receiving a first cache line from a memory controller and determining whether the first cache line corresponds to a first portion of data. Some embodiments include, when the first cache line corresponds to the first portion of data, determining whether a second cache line is received and when the second cache line is not received, processing the first cache line. Similarly, some embodiments include when the first cache line does not correspond to the first portion of data, waiting for a cache line that does correspond to the first portion of data. | 06-17-2010 |
20100235586 | MULTI-CORE PROCESSOR SNOOP FILTERING - Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit having a plurality of cores. A cache memory management system may be associated with each core that includes a cache memory device configured to store a plurality of cache lines, a page status table configured to track pages of memory stored in the cache memory device and to indicate a status of each of the tracked pages of memory, and a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request based at least in part on the status of one of the tracked pages in the page status table. | 09-16-2010 |
20100241813 | Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications - A system supporting producer-consumer pre-fetch communications includes a first processor, wherein the first processor is a producer node, and a second processor, wherein the second processor is a consumer node. The system further includes a data subscribe mechanism for performing a data subscribe operation at the consumer node, wherein the data subscribe operation records that a memory address is subscribed at the consumer node, a data publish mechanism for performing a data publish operation at the producer nod; wherein the data publish operation sends data of the memory address from the producer node to the consumer node if the memory address is subscribed at the consumer node, and a communication network coupled to the producer node and the consumer node for enabling communicating between the producer node and the consumer node. | 09-23-2010 |
20100241814 | BANDWIDTH-EFFICIENT DIRECTORY-BASED COHERENCE PROTOCOL - Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line. | 09-23-2010 |
20100287340 | Concurrent Execution of Critical Sections by Eliding Ownership of Locks - One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section. | 11-11-2010 |
20100306478 | DATA CACHE WITH MODIFIED BIT ARRAY - A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organization. The first functional unit writes data to a cache line of the data array. The first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array has been modified. The second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified. The second functional unit reads a partial status of the corresponding cache line from the tag array. The partial status does not indicate whether the cache line has been modified. The tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line. | 12-02-2010 |
20100318747 | ATOMIC MEMORY OPERATION CACHE PROTOCOL WITH OPPORTUNISTIC COMBINING - An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory. | 12-16-2010 |
20100332766 | SUPPORTING EFFICIENT SPIN-LOCKS AND OTHER TYPES OF SYNCHRONIZATION IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM - Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations. | 12-30-2010 |
20110107034 | CACHE DEVICE - A cache device comprises: data memory that includes a plurality of ways for storing a part of data of a main memory; tag memory that includes a plurality of ways, each of which is for storing tag contained in address of data recorded in each way of the data memory; comparison circuit that decides whether tag contained in address to be accessed agrees with the tag recorded in the tag memory or not; next address generation circuit that calculates address to be accessed next time as second address by referring to first address to be accessed at present time; and tag reading control circuit that pre-reads tag corresponding to index of the second address from the tag memory and ceases to read tags hereafter from the tag memory in a case where the tag contained in the second address agrees with the pre-read tag. | 05-05-2011 |
20110119451 | NON-BLOCKING DATA TRANSFER VIA MEMORY CACHE MANIPULATION - A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented. | 05-19-2011 |
20110131382 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 06-02-2011 |
20110191546 | MEMORY ACCESS PREDICTION - An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, and a physical memory shared with the processors, saturation counters and memory caches. Upon a cache miss for a data item, a cache snoop and access to physical memory are initiated in parallel for the data item if the indicator bit is a first predetermined bit (one (1) or zero (0)) whereas a cache snoop is initiated if the most significant bit is a second predetermined bit (zero (0) or one (1)). | 08-04-2011 |
20110264866 | TECHNIQUE FOR USING MEMORY ATTRIBUTES - A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner. | 10-27-2011 |
20110289278 | METHOD OF ESTIMATING READ LEVEL FOR A MEMORY DEVICE, MEMORY CONTROLLER THEREFOR, AND RECORDING MEDIUM - A method of estimating a read level for a memory device includes calculating first information corresponding to at least one among information about the number of cells having a particular logic level in data to be programmed and information about the number of cells having a particular cell state and storing the first information during a program operation; reading the data based on a threshold level that has been set and calculating second information about the number of cells in at least one state defined by the threshold level with respect to the read data; calculating third information about the number of cells in the at least one state, which corresponds to the second information, using a probability based on the first information; comparing the second information with the third information; and determining whether to change the threshold level according to the comparison result. | 11-24-2011 |
20110289279 | DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds to data stored in the shared memory, the data also stored in a local pipeline cache corresponding to a client processing module. The configuration controller sends the atomic update request to the client processing modules. Each client processing module determines presence of an active access operation of a cache line in the local cache corresponding to the data of the atomic update request. If the active access operation of the cache line is absent, the client processing module writes the cache line from the local cache to shared memory, clears a valid indicator corresponding to the cache line and updates the data corresponding to the atomic update request. | 11-24-2011 |
20110320740 | METHOD FOR OPTIMIZING SEQUENTIAL DATA FETCHES IN A COMPUTER SYSTEM - A computer implemented method of optimizing sequential data fetches in a computer system is provided. The method includes fetching a data segment from a main memory, the data segment having a plurality of target data entries; extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number target data entries in the data segment. | 12-29-2011 |
20120079212 | ARCHITECTURE FOR SHARING CACHES AMONG MULTIPLE PROCESSES - Various embodiments of the present invention provide a system for caching information in a multi-process environment. The system includes a processor. A shared memory is communicatively coupled to the processor. The shared memory includes a set of data. A writer process is communicatively coupled to the shared memory. The write process reads and updates the set of data. A plurality of reader processes is communicatively coupled to the shared memory. Each reader process reads at least part of the set of data directly from the shared memory and sends a set of update information to the writer process. The writer process then updates the set of data stored in the shared memory based on the set of update information. | 03-29-2012 |
20120084516 | METHODS AND APPARATUSES FOR DATA RESOURCE PROVISION - Methods and apparatuses are provided for data resource provision. A method may include receiving a request for a first data resource. The request may include an indication of an additional data resource that may be requested in a future request. The method may further include determining the indicated additional data resource. The method may additionally include causing caching of the additional data resource in preparation for a future request for the additional data resource. Corresponding apparatuses are also provided. | 04-05-2012 |
20120131283 | MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks. | 05-24-2012 |
20120137080 | SYSTEM AND METHOD FOR CREATING ORDERING POINTS - A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data. | 05-31-2012 |
20120159086 | Cache Management - Methods, apparatuses, and computer program products are disclosed for cache management. Embodiments include receiving, by a cache controller, a request to insert a new cache line into a cache; determining, by the cache controller, whether the new cache line is associated with a forced injection; in response to determining that the new cache line is associated with a forced injection, accepting, by the cache controller, the insertion of the new cache line into the cache; and in response to determining that the new cache line is not associated with a forced injection, determining, by the cache controller, whether to accept the insertion of the new cache line based on a comparison of an address of the new cache line to a predefined range of addresses. | 06-21-2012 |
20120173824 | MANAGING CACHE DATA AND METADATA - Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache device at which data items are stored. In some embodiments, cache metadata may be stored in a hierarchical data structure comprising a plurality of hierarchy levels. When a reboot of the computer is initiated, only a subset of the plurality of hierarchy levels may be loaded to memory, thereby expediting the process of restoring the cache metadata and thus startup operations. Startup may be further expedited by using cache metadata to perform operations associated with reboot. | 07-05-2012 |
20120260045 | INCONSISTENCY ROBUSTNESS IN SCALABLE OLAP CUBES - A method (and system) includes providing a memory including a plurality of named locations each holding a value and introducing at least one freshener. The at least one freshener chooses one of the plurality of named locations and re-computes its value. | 10-11-2012 |
20120265942 | PREDICTIVE OWNERSHIP CONTROL OF SHARED MEMORY COMPUTING SYSTEM DATA - A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data. | 10-18-2012 |
20120265943 | Configurable Cache and Method to Configure Same - A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line. | 10-18-2012 |
20120303907 | Dynamically Maintaining Coherency Within Live Ranges of Direct Buffers - Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference. | 11-29-2012 |
20130019067 | METHOD AND SYSTEM FOR ENSURING CACHE COHERENCE OF METADATA IN CLUSTERED FILE SYSTEMSAANM VILAYANNUR; MuraliAACI San JoseAAST CAAACO USAAGP VILAYANNUR; Murali San Jose CA USAANM LI; JinyuanAACI BellevueAAST WAAACO USAAGP LI; Jinyuan Bellevue WA USAANM VAGHANI; Satyam B.AACI San JoseAAST CAAACO USAAGP VAGHANI; Satyam B. San Jose CA US - Metadata of a shared file in a clustered file system is changed in a way that ensures cache coherence amongst servers that can simultaneously access the shared file. Before a server changes the metadata of the shared file, it waits until no other server is attempting to access the shared file, and all I/O operations to the shared file are blocked. After writing the metadata changes to the shared file, local caches of the other servers are updated, as needed, and I/O operations to the shared file are unblocked. | 01-17-2013 |
20130024628 | EFFICIENT TRACK DESTAGE IN SECONDARY STORAGE - Exemplary method, system, and computer program product embodiments for efficient track destage in secondary storage in a more effective manner, are provided. In one embodiment, by way of example only, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. Additional system and computer program product embodiments are disclosed and provide related advantages. | 01-24-2013 |
20130042076 | CACHE MEMORY ACCESS METHOD AND CACHE MEMORY APPARATUS - A cache memory access method is to be implemented by a cache memory apparatus that includes a data storage unit which includes a plurality of storage sets each including a plurality of storage elements corresponding respectively to a plurality of access ways. The method includes: receiving from a processer a target address; determining whether the data storage unit stores target data corresponding to the target address; receiving the target data from a main memory if negative; selecting a chosen way from the plurality of access ways according to whether the storage elements of the storage set which corresponds to the target address store valid data and whether the target address corresponds to a predefined lock range in the main memory; and writing the target data in the data storage unit based on the chosen way. | 02-14-2013 |
20130073813 | Mechanism for Saving a Snapshot of Free Space of a File System on Persistent Storage - A mechanism for saving a snapshot of free space of a file system on persistent storage is disclosed. A method of the invention includes determining whether generation numbers stored in each of a free space cache inode of an on-disk free space cache of a block group, a free space cache item, and a free space cache header are valid, determining whether a checksum generated for a first page of the free space cache matches a checksum stored in the file system and associated with the free space cache, and adding entries stored in the on-disk free space cache to an in-memory free space cache for the block group kept in volatile memory of a computing device, wherein the on-disk free space cache is stored in persistent data storage indexed by a file system of the computing device. | 03-21-2013 |
20130103911 | METHOD AND APPARATUS FOR SYNCHRONIZING A CACHE - An approach is provided for segmenting a cache into one or more cache segments and synchronizing the cache segments. An cache platform causes, at least in part, a segmentation of at least one cache into one or more cache segments. The cache platform further determines that at least one cache segment of the one or more cache segments is invalid. The cache platform also causes, at least in part, a synchronization of the at least one cache segment. The approach allows for a dynamic optimization of the synchronization of the cache segments based on one or more characteristics associated with the devices and/or the connection associated with the cache synchronization. | 04-25-2013 |
20130103912 | ARRANGEMENT - An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part includes at least one second cache memory configured to request access to said memory. The first directory is configured to use a first coherency protocol for the at least one first cache memory and a second different coherency protocol for the at least one second memory. | 04-25-2013 |
20130111150 | METHOD FOR PREVENTING DEADLOCK OF NODE CONTROLLER, AND NODE CONTROLLER | 05-02-2013 |
20130138894 | HARDWARE FILTER FOR TRACKING BLOCK PRESENCE IN LARGE CACHES - A system and method for efficiently determining whether a requested memory location is in a large row-based memory of a computing system. A computing system includes a processing unit that generates memory requests on a first chip and a cache (LLC) on a second chip connected to the first chip. The processing unit includes an access filter that determines whether to access the cache. The cache is fabricated on top of the processing unit. The processing unit determines whether to access the access filter for a given memory request. The processing unit accesses the access filter to determine whether given data associated with a given memory request is stored within the cache. In response to determining the access filter indicates the given data is not stored within the cache, the processing unit generates a memory request to send to off-package memory. | 05-30-2013 |
20130151790 | Efficient Storage of Meta-Bits Within a System Memory - Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally. | 06-13-2013 |
20130173864 | SEMICONDUCTOR DEVICE INCLUDING ROW CACHE REGISTER - Disclosed herein is a device that includes a memory cell array having a plurality of pages, a row cache register, and an array control circuit. The array control circuit is configured to: select one of the pages as a selected page to form an electrical path between the selected page and the row cache register in response to a first command with a row address; cut the electrical path between the selected page and the row cache register; and form the electrical path again between the selected page and the row cache register in response to a second command without the row address. | 07-04-2013 |
20130179643 | OBSCURING MEMORY ACCESS PATTERNS IN CONJUNCTION WITH DEADLOCK DETECTION OR AVOIDANCE - Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed. | 07-11-2013 |
20130179644 | PARALLEL PROCESSING PROCESSOR SYSTEM - A parallel processing processor system includes multiple processor elements, a main memory, and a shared memory, whose latency with the processors is less than the latency between the main memory and the processors. Each of the multiple processor elements has a DSP (Digital Signal Processor) and an instruction cache. Firmware executed by the DSPs is transferred from the main memory to the shared memory and is shared by the DSPs. Updating of the instruction caches in the case where a cache miss has occurred is performed by, for example, copying, into the instruction caches, the content of the shared memory corresponding to an address accessed by a DSP. | 07-11-2013 |
20130185520 | Determining Cache Hit/Miss of Aliased Addresses in Virtually-Tagged Cache(s), and Related Systems and Methods - Apparatuses and related systems and methods for determining cache hit/miss of aliased addresses in virtually-tagged cache(s) are disclosed. In one embodiment, virtual aliasing cache hit/miss detector for a VIVT cache is provided. The detector comprises a TLB configured to receive a first virtual address and a second virtual address from the VIVT cache resulting from an indexed read into the VIVT cache based on the first virtual address. The TLB is further configured to generate first and second physical addresses translated from the first and second virtual addresses, respectively, The detector further comprises a comparator configured to receive the first and second physical addresses and effectuate a generation of an aliased cache hit/miss indicator based on a comparison of the first and second physical addresses. In this manner, the virtual aliasing cache hit/miss detector correctly generates cache hits and cache misses, even in the presence of aliased addressing. | 07-18-2013 |
20130219127 | CACHING DATA OBJECTS ON A CLIENT SIDE USING A PROTOTYPE CHAIN - Provided are a computer implemented method, computer program product, and system for caching a data object. A copy of an original data object to a specified depth is obtained. The copy of the original data object to the specified depth is cached with reference to the original data object in a prototype chain. A change to a value of a property of the cached copy is received. A new property entry is created for the changed value of the property under the cached copy. A change flag is set to indicate that there is a changed value for the property. | 08-22-2013 |
20130262782 | CENTRAL PROCESSING UNIT, METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT, AND INFORMATION PROCESSING APPARATUS - A central processing unit, connected to a main memory among a plurality of central processing units each including a cache memory, includes a control unit. The control unit executes a process including: classifying the plurality of central processing units into a smaller number than a total number of the plurality of central processing units, and writing to the main memory presence information indicating whether or not the same data as data stored in the main memory is held in a cache memory included in any of the central processing units that belong to a corresponding central processing unit group, for each central processing unit group of a plurality of central processing unit groups obtained by the classifying. | 10-03-2013 |
20130290643 | USING A CACHE IN A DISAGGREGATED MEMORY ARCHITECTURE - Example caches in a disaggregated memory architecture are disclosed. An example apparatus includes a cache to store a first key in association with a first pointer to a location at a remote memory. The location stores a first value corresponding to the first key. The example apparatus includes a receiver to receive a plurality of key-value pairs from the remote memory based on the first key. The first value specifies the key-value pairs for retrieval from the remote memory. | 10-31-2013 |
20130297889 | STORAGE DEVICE - To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which stores address data corresponding the cache data; and a valid bit which stores valid data indicating whether the cache data stored in the data field is valid or invalid. Whether power is supplied to the tag and the data field in each of the cache lines is determined based on the valid data stored in the valid bit. | 11-07-2013 |
20130326156 | NETWORK CACHE SYSTEM FOR REDUCING REDUNDANT DATA - Embodiments include a local cache management system that is configured to be coupled to a local cache and that includes an index engine configured to store fingerprints of message segments stored in the local cache and a redundancy management engine coupled to the index engine. The redundancy management engine includes an adaptive emitter configured to receive a message segment to be transmitted to a remote device, determine expected latency costs of a plurality of transmission algorithms, and select a transmission algorithm, such as by selecting the lowest expected latency cost. The adaptive emitter is also configured to determine whether the message segment is stored within a remote cache management system associated with the remote device, and transmit the message segment through a network to the remote cache management system using the selected transmission algorithm upon a determination that the message segment is not stored within the remote cache management system. | 12-05-2013 |
20130326157 | CENTRAL PROCESSING UNIT AND DRIVING METHOD THEREOF - A cache memory provided in the central processing unit is configured to include a data field which stores data in a main memory unit, a tag field which stores management information on data stored in the data field, and a valid bit which stores information about whether the data stored in the data field and the management information stored in the tag field are valid or invalid. Nonvolatile memory cells are used as memory cells which are components of the data field, the tag field, and the valid bit. Further, a power controller is provided for the central processing unit, and the power controller is configured to selectively supply power supply voltage to the data field, the tag field, and the valid bit when the cache memory is accessed from an arithmetic unit provided in the central processing unit. | 12-05-2013 |
20130339627 | MONITORING A VALUE IN STORAGE WITHOUT REPEATED STORAGE ACCESS - A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit. | 12-19-2013 |
20130339628 | DETERMINING THE LOGICAL ADDRESS OF A TRANSACTION ABORT - Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application. | 12-19-2013 |
20130339629 | TRACKING TRANSACTIONAL EXECUTION FOOTPRINT - Embodiments relate to tracking a transactional execution footprint. An aspect includes receiving a store instruction which includes store data. It is determined if the store instruction is executing within a transaction that effectively delays committing stores to a shared cache until the transaction has completed. The store data is stored to a cache line in a local cache. The cache line is marked as dirty if the transaction is active. The stored data that was marked as dirty in the local cache is invalidated if the transaction has terminated abnormally. The stored data is un-marked if it is determined that the transaction has successfully ended. | 12-19-2013 |
20130339630 | MONITORING A VALUE IN STORAGE WITHOUT REPEATED STORAGE ACCESS - A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit. | 12-19-2013 |
20140006721 | INFORMATION PROCESSING APPARATUS AND CACHE CONTROLLING METHOD | 01-02-2014 |
20140013059 | SYSTEMS, METHODS AND APPARATUS FOR CACHE TRANSFERS - A virtual machine cache provides for maintaining a working set of the cache during a transfer between virtual machine hosts. In response to a virtual machine transfer, the previous host of the virtual machine is configured to retain cache data of the virtual machine, which may include both cache metadata and data that has been admitted into the cache. The cache data may be transferred to the destination host via a network (or other communication mechanism). The destination host populates a virtual machine cache with the transferred cache data to thereby reconstruct the working state of the cache. | 01-09-2014 |
20140019691 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INVALIDATNG CACHE LINES - A system, method, and computer program product are provided for invalidating cache lines. In use, one or more cache lines that hold data from within a region of a memory address space are invalidated. | 01-16-2014 |
20140019692 | CONCURRENT EXECUTION OF CRITICAL SECTIONS BY ELIDING OWNERSHIP OF LOCKS - Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by multiple threads with elision of the lock acquisition and release. Upon a completion of the speculative execution without actual conflict as may be identified using standard cache protocols, the speculative execution is committed, otherwise the speculative execution is squashed. Speculative execution with elision of the lock acquisition, allows a greater degree of parallel execution in multi-threaded programs with aggressive lock usage. | 01-16-2014 |
20140025901 | TECHNIQUE FOR USING MEMORY ATTRIBUTES - A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner. | 01-23-2014 |
20140032857 | METHODS AND APPARATUS FOR MERGING SHARED CACHE LINE DATA IN A BUS CONTROLLER - Shared cache line data is merged in a bus controller by issuing a snoop request to a plurality of cache controllers with a cache line address for which a bus transaction is performed; collecting snoop responses from the plurality of cache controllers, wherein a snoop response from a given cache controller comprises a cache state of the cache line address in a given cache associated with the given cache controller, and an ownership control signal identifying which portions of the cache line are controlled by the given cache; collecting data responses from the cache controllers, wherein the data response from a given cache controller comprises a data value from the cache line address; merging the data values from the cache controllers based on the ownership control signals to obtain a merged data value; and broadcasting the merged data value to the cache controllers. | 01-30-2014 |
20140047193 | System and Method for Utilizing Non-Volatile Memory in a Cache - In one embodiment, a computing system includes a cache having one or more memories, a cache journal operable to store data associated with one or more portions of the cache, and a configuration manager operable to access the cache and the cache journal. The configuration manager is operable to determine whether the cache journal includes data associated with a first portion of the cache, and to create, in the cache journal, data associated with the first portion of the cache if the cache journal does not yet comprise data associated with the first portion of the cache. The configuration manager is also operable to determine whether the first portion of the cache is valid for use, and to communicate with a memory manager associated with the first portion of the cache regarding whether the first portion of the cache is valid for use. | 02-13-2014 |
20140047194 | PROCESSOR AND CONTROL METHOD THEREOF - A processor has a first core unit which outputs history information and occupancy mode information related to an arithmetic processing, a memory which has a first storage area and a second storage area, and a control circuit which writes the history information outputted by the first core unit into the first storage area of the memory when the occupancy mode information outputted by the first core unit indicates invalidity, and writes the history information outputted by the first core unit into the first storage area and the second storage area of the memory when the occupancy mode information outputted by the first core unit indicates validity. | 02-13-2014 |
20140052932 | METHOD FOR REDUCING THE OVERHEAD ASSOCIATED WITH A VIRTUAL MACHINE EXIT WHEN HANDLING INSTRUCTIONS RELATED TO DESCRIPTOR TABLES - A computerized method for efficient handling of a privileged instruction executed by a virtual machine (VM). The method comprises identifying when the privileged instruction causes a VM executed on a computing hardware to perform a VM exit; replacing a first virtual-to-physical address mapping to a second virtual-to-physical address mapping respective of a virtual pointer associated with the privileged instruction; and invalidating at least a cache entry in a cache memory allocated to the VM, thereby causing a new translation for the virtual pointer to the second virtual-to-physical address, wherein the second virtual-to-physical address provides a pointer to a physical address in a physical memory in the computing hardware allocated to the VM. | 02-20-2014 |
20140068200 | Storage Subsystem And Storage System Architecture Performing Storage Virtualization And Method Thereof - A method for generating a virtual volume (VV) in a storage system architecture. The architecture comprises a host and one or more disk array subsystems. Each subsystem comprises a storage controller. One or more of the subsystems comprises a physical storage device (PSD) array. The method comprises the following steps: mapping the PSD array into a plurality of media extents (MEs), each of the MEs comprises a plurality of sections; providing a virtual pool (VP) to implement a section cross-referencing function, wherein a section index (SI) of each of the sections contained in the VP is defined by the VP to cross-reference VP sections to physical ME locations; providing a conversion method or procedure or function for mapping VP capacity into to a VV; and presenting the VV to the host. A storage subsystem and a storage system architecture performing the method are also provided. | 03-06-2014 |
20140089602 | SYSTEM CACHE WITH PARTIAL WRITE VALID STATES - Methods and apparatuses for processing partial write requests in a system cache within a memory controller. When a write request that updates a portion of a cache line misses in the system cache, the write request writes the data to the system cache without first reading the corresponding cache line from memory. The system cache includes error correction code bits which are redefined as word mask bits when a cache line is in a partial dirty state. When a read request hits on a partial dirty cache line, the partial data is written to memory using a word mask. Then, the corresponding full cache line is retrieved from memory and stored in the system cache. | 03-27-2014 |
20140095804 | Efficient Cache Validation and Content Retrieval in a Content Delivery Network - Some embodiments provide systems and methods for validating cached content based on changes in the content instead of an expiration interval. One method involves caching content and a first checksum in response to a first request for that content. The caching produces a cached instance of the content representative of a form of the content at the time of caching. The first checksum identifies the cached instance. In response to receiving a second request for the content, the method submits a request for a second checksum representing a current instance of the content and a request for the current instance. Upon receiving the second checksum, the method serves the cached instance of the content when the first checksum matches the second checksum and serves the current instance of the content upon completion of the transfer of the current instance when the first checksum does not match the second checksum. | 04-03-2014 |
20140101390 | Computer Cache System Providing Multi-Line Invalidation Messages - A computer cache system delays cache coherence invalidation messages related to cache lines of a common memory region to collect these messages into a combined message that can be transmitted more efficiently. This delay may be coordinated with a detection of whether the processor is executing a data-race free portion of the program so that the delay system may be used for a variety of types of programs which may have data-race and data-race free sections. | 04-10-2014 |
20140101391 | CONDITIONAL WRITE PROCESSING FOR A CACHE STRUCTURE OF A COUPLING FACILITY - A method for managing a cache structure of a coupling facility includes receiving a conditional write command from a computing system and determining whether data associated with the conditional write command is part of a working set of data of the cache structure. If the data associated with the conditional write command is part of the working set of data of the cache structure the conditional write command is processed as an unconditional write command. If the data associated with the conditional write command is not part of the working set of data of the cache structure a conditional write failure notification is transmitted to the computing system. | 04-10-2014 |
20140122810 | PARALLEL PROCESSING OF MULTIPLE BLOCK COHERENCE OPERATIONS - A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream. | 05-01-2014 |
20140122811 | Method And Apparatus For Error Correction In A Cache - A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed. | 05-01-2014 |
20140122812 | TILED CACHE INVALIDATION - One embodiment of the present invention sets forth a graphics subsystem. The graphics subsystem includes a first tiling unit associated with a first set of raster tiles and a crossbar unit. The crossbar unit is configured to transmit a first set of primitives to the first tiling unit and to transmit a first cache invalidate command to the first tiling unit. The first tiling unit is configured to determine that a second bounding box associated with primitives included in the first set of primitives overlaps a first cache tile and that the first bounding box overlaps the first cache tile. The first tiling unit is further configured to transmit the primitives and the first cache invalidate command to a first screen-space pipeline associated with the first tiling unit for processing. The screen-space pipeline processes the cache invalidate command to invalidate cache lines specified by the cache invalidate command. | 05-01-2014 |
20140149685 | MEMORY MANAGEMENT USING DYNAMICALLY ALLOCATED DIRTY MASK SPACE - Systems and methods related to a memory system including a cache memory are disclosed. The cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks. A cache controller is configured to allocate one of the dirty masks to each of the cache memory lines when a write to the respective cache memory line is not a full write to that cache memory line. Each of the dirty masks indicates dirty states of data units in one of the cache memory lines. The cache controller stores an identification (ID) information that associates the dirty masks with the cache memory lines to which the dirty masks are allocated. | 05-29-2014 |
20140156949 | FAULT HANDLING IN ADDRESS TRANSLATION TRANSACTIONS - A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations. | 06-05-2014 |
20140173222 | Validating Cache Coherency Protocol Within a Processor - A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 06-19-2014 |
20140201466 | DATA RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor. | 07-17-2014 |
20140281272 | Rapid Recovery From Downtime Of Mirrored Storage Device - No-loss rapid recovery performs resynchronization efficiently while concurrently allowing availability to mirrored data on the storage device. No-loss rapid recovery has two stages and involves storage devices that have both a non-volatile cache and primary storage and that operate as mirror buddies. The first stage is referred to herein as the buddy-retention stage. During the buddy-retention stage, writes to mirrored data are not performed on the offline mirror buddy but are performed on the online mirror buddy. The mirrored data changed in the online mirrored buddy is retained in the non-volatile cache of the retention buddy. The next stage is referred to herein as the rapid resynchronization stage. In this stage, the changed mirrored data retained by the retention buddy for no-loss rapid recovery is used to resynchronize the offline buddy. The storage device is resynchronized using the changed mirrored data retained in the cache of the mirror buddy. | 09-18-2014 |
20140281273 | Providing Local Cache Coherency in a Shared Storage Environment - Multiple nodes of a cluster have associated non-shared, local caches, used to cache shared storage content. Each local cache is accessible only to the node with which it is associated, whereas the cluster-level shared storage is accessible by any of the nodes. Attempts to access the shared storage by the nodes of the cluster are monitored. Information is tracked concerning the current statuses of the local caches of the nodes of the cluster. Current tracked local cache status information is maintained, and stored such that it is accessible by the multiple nodes of the cluster. The current tracked local cache status information is used in conjunction with the caching functionality to determine whether specific nodes of the cluster are to access their local caches or the shared storage to obtain data corresponding to specific regions of the shared storage. | 09-18-2014 |
20140365734 | OBSERVATION OF DATA IN PERSISTENT MEMORY - Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache. | 12-11-2014 |
20140365735 | COMPUTING APPARATUS, COMPUTING METHOD, AND COMPUTING PROGRAM - A computing apparatus computes a performance value of a program which includes a specific code which is executed multiple times by the processor and an access instruction for instructing the processor to access a memory area. The computing apparatus includes: a determining unit that determines, whether or not a cache memory is available for use at a time of execution of the access instruction in a simulation of an operation in which the processor executes the program; a generating unit that generates, in a case where the first determining unit has determined that the cache memory is not available, a computational code for computing the performance value of the specific code for a case where the processor executes the specific code, based on performance values of individual instructions within the specific code for a case where the cache memory is not used, without depending on an attribute of the memory area. | 12-11-2014 |
20150032973 | System and Method for Detecting False Sharing - In one embodiment, a method for detecting false sharing includes running code on a plurality of cores, where the code includes instrumentation and tracking cache invalidations in the code while running the code to produce tracked invalidations in accordance with the instrumentation, where tracking the cache invalidations includes tracking cache accesses to a plurality of cache lines by a plurality of tasks. The method also includes reporting false sharing in accordance with the tracked invalidations to produce a false sharing report. | 01-29-2015 |
20150089158 | NAVIGATION SYSTEM WITH GEOCACHING MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a navigation system includes: identifying a geocache at a geocache-location; determining an external association for representing the geocache associated with an entity, an event, or a combination thereof; determining an external status for identifying the external status of the entity, the event, or a combination thereof; and generating a cache status based on the external status for displaying on a device. | 03-26-2015 |
20150089159 | MULTI-GRANULAR CACHE MANAGEMENT IN MULTI-PROCESSOR COMPUTING ENVIRONMENTS - Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode. | 03-26-2015 |
20150134917 | REMOTE MATERIALIZATION OF LOW VELOCITY DATA - A system includes reception of a client query identifying data stored by a remote data source, generation of a remote query of the remote data source based on the client query, determination of a cache name based on the remote query, determination of whether the remote data source comprises a cache associated with the cache name and, if it is determined that the remote data source comprises a valid cache associated with the cache name, instruction of the remote data source to read the data of the cache, and reception of the data of the cache from the remote data source. | 05-14-2015 |
20150149733 | SUPPORTING SPECULATIVE MODIFICATION IN A DATA CACHE - Method and system for supporting speculative modification in a data cache are provided and described. In one embodiment, a speculative cache buffer includes a plurality of cache lines and a plurality of state indicators. At least one of the cache lines is operable to receive an evicted cache line from a cache. The at least one of the cache lines is operable to return the evicted cache line to the cache if the cache requests the evicted cache line. Further, the plurality of state indicators is operable to indicate a state of a corresponding cache line of the cache lines. | 05-28-2015 |
20150363322 | SYSTEMS, METHODS, AND COMPUTER PROGRAMS FOR PROVIDING CLIENT-FILTERED CACHE INVALIDATION - A method and system includes generating a cache entry comprising cache line data for a plurality of cache clients and receiving a cache invalidate instruction from a first of the plurality of cache clients. In response to the cache invalidate instruction, the data valid/invalid state is changed for the first cache client to an invalid state without modifying the data valid/invalid state for the other of the plurality of cache clients from the valid state. A read instruction may be received from a second of the plurality of cache clients and in response to the read instruction, a value stored in the cache line data is returned to the second cache client while the data valid/invalid state for the first cache client is in the invalid state and the data valid/invalid state for the second cache client is in the valid state. | 12-17-2015 |
20160092360 | HYBRID CACHE COMPRISING COHERENT AND NON-COHERENT LINES - An electronic system for multiple agents, both coherent and non-coherent, to communicate with a hybrid cache, the hybrid cache to provide functionality associated with a cache for coherent agents in an outer shareable domain, and to provide functionality associated with a cache for non-coherent agents in a system shareable domain, the functionality provided by tag fields in cache lines stored in the hybrid cache. The tag fields are configured to indicate if a cache line of the hybrid cache belongs to at least one of a logical coherent cache or a logical system cache. | 03-31-2016 |
20160098351 | DEVICE AND METHOD FOR INTEGRATED DATA MANAGEMENT FOR NONVOLATILE BUFFER CACHE AND NONVOLATILE STORAGE - An integrated nonvolatile memory control subsystem and method are disclosed. The integrated nonvolatile memory control subsystem includes a nonvolatile buffer cache, a nonvolatile journal area, nonvolatile storage, and an integrated memory control unit. The integrated memory control unit performs a read operation, a write operation, a commit operation and a checkpoint operation on the cache blocks of the nonvolatile buffer cache and the journal blocks of the nonvolatile journal area. The integrated memory control unit sets each of data blocks of the nonvolatile storage as one among valid state, erasable state and invalid state, depending on being cached or not, being journaled or not, and being a clean cache or not, so as to maintain an authentic original up-to-date consistent data within any one of the nonvolatile buffer cache, the nonvolatile journal area and the nonvolatile storage. | 04-07-2016 |
20160124866 | CACHE MEMORY AND METHOD OF MANAGING THE SAME - A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address. | 05-05-2016 |
20160188468 | IMPLEMENTATION OF DATA COHERENCE AMONG DEVICES - Systems and methods may provide coherence between devices that share one or more variables during an execution of applications. State variables may be associated with data in cache, and may take on a Modified, Exclusive, Shared, or Invalid (MESI) value indicative of a state of the corresponding data. The data may be updated across all, or a portion, of the devices to provide data coherence among the devices as needed based on, for example, the state variable. | 06-30-2016 |
20160188478 | MANAGING METADATA FOR CACHING DEVICES DURING SHUTDOWN AND RESTART PROCEDURES - A computer program product, system, and method for managing metadata for caching devices during shutdown and restart procedures. Fragment metadata for each fragment of data from the storage server stored in the cache device is generated. The fragment metadata is written to at least one chunk of storage in the cache device in a metadata directory in the cache device. For each of the at least one chunk in the cache device to which the fragment metadata is written, chunk metadata is generated for the chunk and writing the generated chunk metadata to the metadata directory in the cache device. Header metadata having information on access of the storage server is written to the metadata directory in the cache device. The written header metadata, chunk metadata, and fragment metadata are used to validate the metadata directory and the fragment data in the cache device during a restart operation. | 06-30-2016 |
20160253258 | Memory Controller Supporting Nonvolatile Physical Memory | 09-01-2016 |