Class / Patent application number | Description | Number of patent applications / Date published |
711152000 | Memory access blocking | 83 |
20080222368 | Updating Memory Contents of a Processing Device - A method of updating memory content stored in a memory of a processing device, the memory comprising a plurality of addressable memory blocks, the memory content being protected by a current integrity protection data item stored in the processing device, the method comprising determining a first subset of memory blocks that require an update, and a second subset of memory blocks that remain unchanged by said updating; calculating, as parallel processes, a first and a second integrity protection data item over the memory blocks; wherein the first integrity protection data item is calculated over the current memory contents of the first and second subsets of memory blocks; and wherein the second integrity protection data item is calculated over the current memory contents of the second subset of memory blocks and the updated memory block contents of the first subset of memory blocks. | 09-11-2008 |
20080256306 | NON-INCLUSIVE CACHE SYSTEMS AND METHODS - Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity. | 10-16-2008 |
20080294852 | System and method for achieving reliable WORM storage using WMRM storage - The invention provides a method for ensuring that data stored on rewritable storage is immutable. The method includes initializing selected user-addressable blocks of storage to a writable state. In addition, the method includes accepting data to be stored in specified user-addressable blocks. Also, the method includes determining if the specified block(s) is writable. Also, the method includes storing the accepted data to the rewritable storage. Moreover, the method includes setting the state of the specified block(s) to non-writable. In one embodiment, the writable/non-writable state associated with each block is encoded and stored in the contents of the corresponding block. In another embodiment, the steps of determining whether the specified block(s) is writable, storing the accepted data to the rewritable storage, and setting the state of the specified block(s) to non-writable, are integrated and indivisible. | 11-27-2008 |
20090013134 | MEMORY APPARATUS AND PROTECTING METHOD THEREOF - A memory apparatus and method for protecting the memory apparatus are provided. The memory apparatus includes a memory unit, a memory control unit, a switch and a control circuit. The memory control unit is used for reading from or writing to the memory unit and has a build-in protection unit. The switch has a lock end and a normal end. The control circuit is coupled between the switch and the memory control unit and is used for detecting the position of the switch. Once the switch is switched to the lock end and the memory apparatus receives a working voltage, the protection unit is automatically enabled by the control circuit to inhibit the memory control unit from reading data from or writing data to the memory unit. | 01-08-2009 |
20090094419 | VARYING ACCESS PARAMETERS FOR PROCESSES TO ACCESS MEMORY ADDRESSES IN RESPONSE TO DETECTING A CONDITION RELATED TO A PATTERN OF PROCESSES ACCESS TO MEMORY ADDRESSES - Provided are a method, system, and article of manufacture for varying access parameters for processes to access memory addresses in response to detecting a condition related to a pattern of processes access to memory addresses. A monitored condition is detected during application execution. An instrumentation program is invoked to monitor processes accessing data at addresses in a memory device in response to detecting the monitored condition. Information is logged on processes and the addresses they access in the memory device in response to invoking the instrumentation program. The logged information on the processes and the addresses they access is forwarded to an application analysis system in response to detecting a monitored condition during application execution. | 04-09-2009 |
20090177847 | SYSTEM AND METHOD FOR HANDLING OVERFLOW IN HARDWARE TRANSACTIONAL MEMORY WITH LOCKS - A system, method and computer program product for processing overflow transactions in a transactional memory system. The transactional memory system is provided in a multiprocessing system having one or more processor devices and a shared memory storage system, and implements a best effort hardware transactional memory system. The method includes acquiring, by a requesting processor, lockbits associated with a memory structure of the shared memory storage system to be reserved for an overflowing transaction. The lockbits determine the granularity at which memory reservations for an overflow transaction are recorded. The method includes implementation of control mechanism for controlling concurrency between overflowing and non-overflowing transactions requested by processor devices in the multiprocessing system, the method enabling only one overflowing transaction to execute at a time in the multiprocessing system. | 07-09-2009 |
20090198916 | Method and Apparatus for Supporting Low-Overhead Memory Locks Within a Multiprocessor System - A method for supporting low-overhead memory locks within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is ignored. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed. | 08-06-2009 |
20090198917 | SPECIALIZED MEMORY MOVE BARRIER OPERATIONS - An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC. | 08-06-2009 |
20090292885 | METHOD AND APPARATUS FOR PROVIDING ATOMIC ACCESS TO MEMORY - Apparatus for controlling atomic access to a memory includes an access request evaluator for receiving an atomic access request to an address in the memory from a client and determining whether to allow atomic access to the requested address. An access indicator indicates whether a select address is currently under atomic access in the memory, and an access release indicates whether the atomic access is completed at the select address. The access request evaluator enables the client atomic access to the requested address if the access indicator indicates that the requested address is currently not under atomic access. | 11-26-2009 |
20100023707 | PROCESSOR WITH SUPPORT FOR NESTED SPECULATIVE SECTIONS WITH DIFFERENT TRANSACTIONAL MODES - A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition. | 01-28-2010 |
20100088476 | METHOD FOR ALLOWING EXCLUSIVE ACCESS TO SHARED DATA - A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data. | 04-08-2010 |
20100100690 | SYSTEM TO REDUCE INTERFERENCE IN CONCURRENT PROGRAMS - Locks are used to protect variables. All variables protected by a lock are allocated on a page associated with a lock. When a thread (called the owner) acquires the lock, a local copy of the memory page containing the variable is created, the original memory page is protected, and all access of the variable in the owner thread is directed to the local copy. Upon releasing the lock, the changes from the local copy are carried over to the memory page and the memory page is unprotected. Any concurrent access of the variable by non-owner threads triggers an exception handler (due to the protection mechanism) and delays such an access until after the owner thread has finished accessing the variable. | 04-22-2010 |
20100169584 | SYSTEM AND METHOD FOR ERASING AND WRITING DESKTOP MANAGEMENT INTERFACE DATA UNDER A LINUX SYSTEM - A method for erasing and writing desktop management interface (DMI) data under a Linux system is provided. The method constructs a virtual 8086 mode in the Linux system for executes a PnP calling routine. The method then erase and/or write the DMI data from a management information format database (MIFD) of a basic input/output system (BIOS) in a computer using the PnP calling routine. | 07-01-2010 |
20100174874 | DYNAMIC NEST LEVEL DETERMINATION FOR NESTED TRANSACTIONAL MEMORY ROLLBACK - Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level. | 07-08-2010 |
20100174875 | System and Method for Transactional Locking Using Reader-Lists - In traditional transactional locking systems, such as TLRW, threads may frequently update lock metadata, causing system performance degradation. A system and method for implementing transactional locking using reader-lists (TLRL) may associate a respective reader-list with each stripe of data in a shared memory system. Before reading a given stripe as part of a transaction, a thread may add itself to the stripe's reader-list, if the thread is not already on the reader-list. A thread may leave itself on a reader-list after finishing the transaction. Before a thread modifies a stripe, the modifying thread may acquire a write-lock for the stripe. The writer thread may indicate to each reader thread on the stripe's reader-list that if the reader thread is executing a transaction, the reader thread should abort. The indication may include setting an invalidation flag for the reader. The writer thread may clear the reader-list of a stripe it modified. | 07-08-2010 |
20100250866 | INFORMATION PROCESSING PROGRAM, INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - An apparatus includes: a memory; a management memory for storing first virtual addresses used by the first program, second virtual addresses used by the second program and management information indicative of association between first and second virtual addresses and physical addresses of the memory; and a processor for executing the first, the second and a management programs, the management program including: receiving a request to assign a shared area to be shared by the first and second programs from the second program; determining a physical address of the shared area corresponding to one of the first and one of the second virtual addresses; transmitting a notification of data writing by the first program to the second program; locking the shared area so as to prevent the second program from writing data after the notification; and unlocking the shared area after the second program has read data from the shared area. | 09-30-2010 |
20100250867 | COMPUTER ARCHITECTURES USING SHARED STORAGE - Shared storage architectures and methods are provided. A particular shared storage architecture is a system including shared storage including data and file system metadata separated from the data. The file system metadata includes location data specifying storage location information related to the data. Services are provided from service providers to service consumers through the shared storage. | 09-30-2010 |
20100299487 | Methods and Systems for Partially-Transacted Data Concurrency - Aspects of the present invention comprise systems and methods for protecting multi-threaded access to shared memory. Some aspects provide higher data concurrency than other methods. Some aspects relate to methods and systems that provide access to data for all threads during the first phases of one thread's write operation. Some aspects provide all threads access to a particular data unit until one thread enters the commit phase of the write operation. Some aspects manage a computing data resource such that, when a thread enters the commit phase, all pending read requests are fulfilled, all pending write requests are allowed to proceed to commit phase at which point they are blocked, all new read and write requests are blocked and the commit phase is completed by updating the target data and releasing the blocked requests. | 11-25-2010 |
20100312972 | METHOD, APPARATUS AND SYSTEM FOR ENABLING PROCESSOR TO ACCESS SHARED DATA - A method, an apparatus, and a system for enabling a processor to access shared data are provided to overcome low efficiency of a storage system. The method includes that the processor sends a storage block locking command to the storage system through a hardware thread, where the command instructs the storage system to lock a storage block; the processor judges whether a storage block locking completion message has been received from the storage system in a preset clock period; and, schedules the hardware thread to access shared data in the storage block if the storage block locking completion message has been received from the storage system in the preset clock period, or schedules the hardware thread to keep waiting for the storage block locking completion message from the storage system if no storage block locking completion message has been received from the storage system in the preset clock period. | 12-09-2010 |
20110055493 | TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT - The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores. | 03-03-2011 |
20110138135 | Fast and Efficient Reacquisition of Locks for Transactional Memory Systems - A system and method is disclosed for fast lock acquisition and release in a lock-based software transactional memory system. The method includes determining that a group of shared memory areas are likely to be accessed together in one or more atomic memory transactions executed by one or more threads of a computer program in a transactional memory system. In response to determining this, the system associates the group of memory areas with a single software lock that is usable by the transactional memory system to coordinate concurrent transactional access to the group of memory areas by the threads of the computer program. Subsequently, a thread of the program may gain access to a plurality of the memory areas of the group by acquiring the single software lock. | 06-09-2011 |
20110145516 | USING BUFFERED STORES OR MONITORING TO FILTER REDUNDANT TRANSACTIONAL ACCESSES AND MECHANISMS FOR MAPPING DATA TO BUFFERED METADATA - A method and apparatus for accelerating a Software Transactional Memory (STM) system is herein described. A data object and metadata for the data object may each be associated with a filter, such as a hardware monitor or ephemerally held filter information. The filter is in a first, default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access to the metadata, such as a first read, access barrier operations, such as logging of the metadata; setting a read monitor; or updating ephemeral filter information with an ephemeral/buffered store operation, are performed. Upon a subsequent/redundant access to the metadata, such as a second read, access barrier operations are elided to accelerate the subsequent access based on the filter being set to the second state to indicate a previous access occurred. Additionally, mapping of data objects to ephemeral information may be provided by software, such as through a pointer to the ephemeral information associated with the data object; an offset from a base address of the data object to the ephemeral information included associated with the data object; an index into a segment containing the ephemeral information associated with the data object; mapping the data object to the ephemeral information utilizing address arithmetic; and a hash that maps the data object to ephemeral information. | 06-16-2011 |
20110179231 | SYSTEM AND METHOD FOR CONTROLLING ACCESS TO SHARED STORAGE DEVICE - A system and method for controlling access to a shared storage device in a computing cluster having at least two nodes configured as cluster members provide fencing and quorum features without using the device controller hardware/firmware so fencing can be provided with storage devices that do not support disk reservation operations, such as with non-SCSI compliant disks. A polling thread on each node periodically reads a designated storage space on the shared storage device at a polling interval to determine if its corresponding node registration key is present, and halts the node if the key has been removed. A cluster membership agent removes a corresponding node registration key from the designated storage space of the shared storage device and publishes new membership information indicating that the corresponding node has departed the cluster only after delaying for a time period greater than the polling interval. | 07-21-2011 |
20110302377 | Automatic Reallocation of Structured External Storage Structures - A mechanism for automatic reallocation of shared external storage structures is provided. The shared external storage divides the dynamically allocable storage into fixed sized blocks referred to as allocation units. To create an object of a specific type, the shared external storage uses some number of allocation units. If the object will fit in one allocation unit, then it is placed in one allocation unit. If the object is larger than one allocation unit, then the appropriate number of allocation units is obtained and chained together to contain all of the information of the required object. When an object so allocated is no longer needed, the shared external storage breaks the object down to a set of one or more fixed sized allocation units. The shared external storage then returns the allocation units to the pool of available objects. | 12-08-2011 |
20120036329 | LOCK MECHANISM TO ENABLE ATOMIC UPDATES TO SHARED MEMORY - A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location. | 02-09-2012 |
20120102274 | MEMORY MANAGING APPARATUS, MULTIPROCESSOR SYSTEM, AND METHOD FOR CAUSING MEMORY MANAGING APPARATUS TO MANAGE SHARED MEMORY - A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to each processor based on a request of each processor and registers reference counters corresponding one-to-one to the processors. The updater adds 1 to a value of the reference counter corresponding to the processor managing the memory area when the memory area is allocated to each processor and subtracts 1 from the value of the reference counter corresponding to the processor managing the memory area when the memory area is released from the processor to which the memory area is allocated. The releaser releases the memory area from the processor to which the memory area is allocated when a sum of the values of the reference counters in the memory area updated by the updater is 0. | 04-26-2012 |
20120110273 | TRANSPARENT HYPERVISOR PINNING OF CRITICAL MEMORY AREAS IN A SHARED MEMORY PARTITION DATA PROCESSING SYSTEM - Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical memory area of the logical partition with the hypervisor. Responsive to this hypervisor call, the hypervisor transparently determines whether the logical memory is a critical memory area for access by the hypervisor. If the logical memory area is a critical memory area, then the hypervisor automatically pins the logical memory area to physical memory of the shared memory partition data processing system, thereby ensuring that the memory area will not be paged-out from physical memory to external storage, and thus ensuring availability of the logic memory area to the hypervisor. | 05-03-2012 |
20120144129 | High Performance Real-Time Read-Copy Update - A technique for reducing reader overhead when referencing a shared data element while facilitating realtime-safe detection of a grace period for deferring destruction of the shared data element. The grace period is determined by a condition in which all readers that are capable of referencing the shared data element have reached a quiescent state subsequent to a request for a quiescent state. Common case local quiescent state tracking may be performed using only local per-reader state information for all readers that have not blocked while in a read-side critical section in which the data element is referenced. Uncommon case non-local quiescent state tracking may be performed using non-local multi-reader state information for all readers that have blocked while in their read-side critical section. The common case local quiescent state tracking requires less processing overhead than the uncommon case non-local quiescent state tracking. | 06-07-2012 |
20120151155 | MANAGING SHARED MEMORY - Systems, methods, and computer-readable and executable instructions are provided for managing shared memory. A method for managing shared memory can include statically assigning a first number of locks to the shared memory during compile-time and dynamically assigning a second number of locks to the shared memory during runtime. | 06-14-2012 |
20120185652 | COMPUTER ARCHITECTURES USING SHARED STORAGE - A method providing a persistent common view of data, services, and infrastructure functions accessible via a plurality of shared storage systems of a virtual shared storage system. The method includes applying different governance policies at two or more shared storage systems of the virtual shared storage system. The method includes transferring content from a particular shared storage system to a requesting device without using at least one of a server session, an application-to-server session, and an application session. The content corresponds to at least one of data, a service, and an infrastructure function provided via the particular shared storage system. | 07-19-2012 |
20120185653 | COMPUTER ARCHITECTURES USING SHARED STORAGE - A method includes providing a persistent common view of data, services, and infrastructure functions accessible via one or more shared storage systems of a plurality of shared storage systems of a virtual shared storage system. The method includes applying different governance policies to two or more shared storage systems of the plurality of shared storage systems. The method includes restricting access to first content accessible via a first shared storage system of the plurality of shared storage systems based on a security level associated with a data consumer. The first content corresponds to at least one of first data, a first service, and a first infrastructure function. | 07-19-2012 |
20120210074 | DUAL MODE READER WRITER LOCK - A method for a dual mode reader writer lock is provided. A contention condition is determined in using an original lock. The original lock manages read and write access to a resource by several processes executing in the data processing system. The embodiment creates a set of expanded locks for use in conjunction with the original lock. The original lock and the set of expanded locks forming the dual mode reader writer lock, which operates to manage the read and write access to the resource. Using an index within the original lock, each expanded lock is indexed such that each expanded lock is locatable using the index. The contention condition is resolved by distributing requests for acquiring and releasing the read access and write access to the resource by the several processes across the original lock and the set of expanded locks. | 08-16-2012 |
20120215991 | MEMORY PROTECTION UNIT (MPU) HAVING A SHARED PORTION AND METHOD OF OPERATION - In a disclosed embodiment, a data processing system comprises a memory protection unit (MPU); and a plurality of region descriptors associated with the MPU. Each region descriptor is associated with one of multiple subsets of the region descriptors and includes an address range, protection settings, and attributes for a respective region of memory. The subsets include data-only region descriptors, instruction-only region descriptors, and shared region descriptors. The shared region descriptors are used to access memory regions for data and instruction memory requests. | 08-23-2012 |
20120272014 | DISTRIBUTED SHARED MEMORY - Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost. | 10-25-2012 |
20130042080 | PREVENTION OF RACE CONDITIONS IN LIBRARY CODE THROUGH MEMORY PAGE-FAULT HANDLING MECHANISMS - Protection of shared data in a multi-core processing environment is disclosed. A page-fault handling mechanism is adapted to synchronize access to shared memory. An application of the present invention is for synchronizing access to potentially shared data, where the shared data is opaque in that it does not have a well-defined structure. | 02-14-2013 |
20130046939 | COUPLED LOCK ALLOCATION AND LOOKUP FOR SHARED DATA SYNCHRONIZATION IN SYMMETRIC MULTITHREADING ENVIRONMENTS - In a shared memory process different threads may attempt to access a shared data variable in a shared memory. Locks are provided to synchronize access to shared data variables. Each lock is allocated to have a location in the shared memory relative to the instance of shared data that the lock protects. A lock may be allocated to be adjacent to the data that it protects. Lock resolution is facilitated because the memory location of a lock can be determined from an offset with respect to the data variable that is being protected by the lock. | 02-21-2013 |
20130086333 | SYSTEM AND METHOD FOR SUPPORTING A SELF-TUNING LOCKING MECHANISM IN A TRANSACTIONAL MIDDLEWARE MACHINE ENVIRONMENT - A lock mechanism can be supported in a transactional middleware system to protect transaction data in a shared memory when there are concurrent transactions. The transactional middleware machine environment comprises a semaphore provided by an operating system running on a plurality of processors. The plurality of processors operates to access data in the shared memory. The transactional middleware machine environment also comprises a test-and-set (TAS) assembly component that is associated with one or more processes. Each said process operates to use the TAS assembly component to perform one or more TAS operations in order to obtain a lock for data in the shared memory. Additionally, a process operates to be blocked on the semaphore and waits for a release of a lock on data in the shared memory, after the TAS component has performed a number of TAS operations and failed to obtain the lock. | 04-04-2013 |
20130097392 | PROTECTING MEMORY OF A VIRTUAL GUEST - An apparatus and system for protecting memory of a virtual guest includes initializing a virtual guest on a host computing system. The host computing system includes a virtual machine manager that manages operation of the virtual guest. The virtual guest includes a distinct operating environment executing in a virtual operation platform provided by the virtual machine manager. The method includes receiving an allocation of run-time memory for the virtual guest, the allocation of run-time memory comprising a portion of run-time memory of the host computing system. The method includes setting, by the virtual guest, at least a portion of the allocation of run-time memory to be inaccessible by the virtual machine manager. | 04-18-2013 |
20130117513 | MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH LATENCY MEMORY OPERATIONS - Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations. | 05-09-2013 |
20130173867 | INFORMATION PROCESSING APPARATUS AND UNAUTHORIZED ACCESS PREVENTION METHOD - An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node. | 07-04-2013 |
20130173868 | Generation of Activation List for Memory Translation and Memory Access Protection in Industrial Ethernet Standard - The invention relates to an EtherCAT fieldbus system, a master and a slave for the system and a method. The slave is configured to be coupled to the EtherCAT fieldbus. A first configurable memory of the slave stores a first activation list indicating for consecutive bytes of data of an EtherCAT datagram a corresponding fieldbus memory management information or synchronization management information. | 07-04-2013 |
20130173869 | Increasing Functionality Of A Reader-Writer Lock - In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed. | 07-04-2013 |
20130227224 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes. | 08-29-2013 |
20130262789 | Automatic Mutual Exclusion - An automatic mutual exclusion computer programming system is disclosed which allows a programmer to produce concurrent programming code that is synchronized by default without the need to write any synchronization code. The programmer creates asynchronous methods which are not permitted make changes to shared memory that they cannot reverse, and can execute concurrently with other asynchronous methods. Changes to shared memory are committed if no other thread has accessed shared memory while the asynchronous method executed. Changes are reversed and the asynchronous method is re-executed if another thread has made changes to shared memory. The resulting program executes in a serialized order. A blocking system method is disclosed which causes the asynchronous method to re-execute until the blocking method's predicate results in an appropriate value. A yield system call is disclosed which divides asynchronous methods into atomic fragments. When a yield method call is made, shared memory changes are committed if possible or reversed and the atomic fragment is re-executed. | 10-03-2013 |
20130262790 | METHOD, COMPUTER PROGRAM AND DEVICE FOR MANAGING MEMORY ACCESS IN A MULTIPROCESSOR ARCHITECTURE OF NUMA TYPE - Managing memory access in a non-uniform memory access (NUMA) multiprocessor architecture including two computation units and at least two separate memories is disclosed. Each memory, including at least one logic memory entity, is locally associated with a computation unit. After receiving a control for access to a logic memory entity, the status of an indicator of the status of the logic memory entity (first entity) to which the received command applies is determined. If the indicator is in a first state, the received control is executed. If, on the contrary, the indicator is in a second state, data stored in the first entity is migrated into a second logic memory entity of a memory separate from the memory including the first entity, and the status of the second entity is placed into the first state. | 10-03-2013 |
20130318311 | SYSTEM-ON-CHIP FOR PROVIDING ACCESS TO SHARED MEMORY VIA CHIP-TO-CHIP LINK, OPERATION METHOD OF THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME - An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU. | 11-28-2013 |
20130339633 | CHANGING A SYSTEM CLOCK RATE SYNCHRONOUSLY - A system includes a shared memory and a plurality of processor cores communicatively coupled to the shared memory. The system includes a processor core memory and a clock subsystem for providing a clock signal to the shared memory and the plurality of processor cores. Each of the plurality of processor cores executes instructions stored in the processor core memory for synchronously changing the clock rate provided by the clock subsystem to the plurality of processor cores. | 12-19-2013 |
20140025903 | MULTI-CORE PROCESSOR SYSTEM - A multi-core processor system includes CPUs; memory; and a memory protect controller that is disposed between the plurality of CPUs and the memory, and that accesses a first memory area consequent to an access request of the CPUs upon application execution and further accesses a second memory area established when the system is booted. | 01-23-2014 |
20140040567 | TLB-Walk Controlled Abort Policy for Hardware Transactional Memory - A system and method are disclosed for increasing large region transaction throughput by making informed determinations whether to abort a thread from a first core or a thread from a second core when a conflict is detected between the threads. Such a system and method allow resolution of conflicts between a first thread and a second thread. In certain embodiments, the system and method allow a requester to detect a conflict under specific circumstances and make an intelligent decision whether to abort the first thread, enter a wait state to give the first thread an opportunity to complete execution or, if possible, abort the second thread. | 02-06-2014 |
20140136799 | MEMORY ARRAY WITH ATOMIC TEST AND SET - A system and method of managing the storage of data is described where a plurality of requesting entities can be permitted access to a shared data resource. When a modification to the data is needed, the request may be executed as an atomic operation. To do this the memory region is temporarily locked until the atomic operation is completed so that other operations related to the data are deferred until the atomic operation has completed. The lock is secured by reference to a data array or register of fixed length where the address of the locked data region is represented by a bit, the position of which is determined by computing a hash value of the address modulo the length of the lock register. | 05-15-2014 |
20140156954 | SYSTEM AND METHOD FOR ACHIEVING ENHANCED PERFORMANCE WITH MULTIPLE NETWORKING CENTRAL PROCESSING UNIT (CPU) CORES - The present disclosure discloses a method and network device for achieving enhanced performance with multiple CPU cores in a network device having a symmetric multiprocessing architecture. The disclosed method allows for storing, by each central processing unit (CPU) core, a non-atomic data structure, which is specific to each networking CPU core, in a memory shared by the plurality of CPU cores. Also, the memory is not associated with any locking mechanism. In response to a data packet is received by a particular CPU core, the disclosed system will update a value of the non-atomic data structure corresponding to the particular CPU core. The data structure may be a counter or a fragment table. Further, a dedicated CPU core is allocated to process only data packets received from other CPU cores, and is responsible for dynamically responding to queries receives from a control plane process. | 06-05-2014 |
20140189260 | APPROACH FOR CONTEXT SWITCHING OF LOCK-BIT PROTECTED MEMORY - A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely. | 07-03-2014 |
20140189261 | ACCESS TYPE PROTECTION OF MEMORY RESERVED FOR USE BY PROCESSOR LOGIC - A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access. | 07-03-2014 |
20140208043 | SYNCHRONIZING PARALLEL APPLICATIONS IN AN ASYMMETRIC MULTI-PROCESSING SYSTEM - A method for synchronizing parallel applications in a partitioned asymmetric multi-processing system having multiple independent levels of security is provided. Synchronized access to a shared data memory region is provided for a first application through a first instance of a para-virtualized user library linked against a first application in a first domain having a first security level. Synchronized access is provided to the shared data memory region for a second application in parallel with the first application through a second instance of the para-virtualized user library linked against the second application in the first domain. The second instance of the para-virtualized user library also accesses the synchronization structure. Access is prevented to the shared data memory region and the synchronization structure by other applications in one or more other domains having other levels of security per domain. | 07-24-2014 |
20140258645 | System and Method for Implementing Reader-Writer Locks Using Hardware Transactional Memory - Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource. | 09-11-2014 |
20140281286 | MEMORY SYSTEM - A memory system is provided, which includes a real memory space and a virtual memory space. The memory system includes a memory device having a first memory space which is accessed using a first memory address and a second memory space which is accessed using a second memory address, and a memory controller configured to control access to the memory device; wherein the memory controller is configured to translate the first memory address into the second memory address mapped thereto in response to a request for access to the first memory space, access the second memory space using the translated second memory address, and access the second memory space using the non-translated second memory address, in response to a request for access to the second memory space. | 09-18-2014 |
20140289483 | SHARED MEMORY CONTROL UNIT HAVING LOCK TRANSACTION CONTROLLER - A shared memory controller controls access to a shared memory by a plurality of master devices based on access requests received from the plurality of master devices. The shared memory control unit includes a memory access arbiter that receives a lock reading request to lock a portion of shared memory, a waiting queue that stores the access requests, and a lock transaction controller. The lock transaction controller receives a plurality of access requests after the lock reading request is received by the memory access arbiter. The lock transaction controller stores the access requests in the waiting queue, and receives an unlock writing request to unlock the portion of shared memory. After the portion of shared memory is unlocked, the lock transaction controller releases the access requests from the waiting queue. | 09-25-2014 |
20140297970 | Concurrent Execution of Critical Sections by Eliding Ownership of Locks - Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by multiple threads with elision of the lock acquisition and release. Upon a completion of the speculative execution without actual conflict as may be identified using standard cache protocols, the speculative execution is committed, otherwise the speculative execution is squashed. Speculative execution with elision of the lock acquisition, allows a greater degree of parallel execution in multi-threaded programs with aggressive lock usage. | 10-02-2014 |
20140337585 | PAGE TABLE MANAGEMENT - Page table data for each page within a memory address space includes a write permission flag and a dirty-bit-modifier flag. The write permission flag is initialised to a value indicating that write access is not permitted. When a write access occurs, then the dirty-bit-modifier flag indicates whether or not the action of the write permission flag may be overridden. If the action of the write permission flag may be overridden, then the write access is permitted and the write permission flag is changed to indicate that write access is thereafter permitted. A page for which the write permission flag indicates that writes are permitted is a dirty page. | 11-13-2014 |
20140344529 | SYSTEM AND METHOD FOR SUPPORTING A SELF-TUNING LOCKING MECHANISM IN A TRANSACTIONAL MIDDLEWARE MACHINE ENVIRONMENT - A lock mechanism can be supported in a transactional middleware system to protect transaction data in a shared memory when there are concurrent transactions. The transactional middleware machine environment comprises a semaphore provided by an operating system running on a plurality of processors. The plurality of processors operates to access data in the shared memory. The transactional middleware machine environment also comprises a test-and-set (TAS) assembly component that is associated with one or more processes. Each said process operates to use the TAS assembly component to perform one or more TAS operations in order to obtain a lock for data in the shared memory. Additionally, a process operates to be blocked on the semaphore and waits for a release of a lock on data in the shared memory, after the TAS component has performed a number of TAS operations and failed to obtain the lock. | 11-20-2014 |
20150012715 | DISTRIBUTED SHARED MEMORY - Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost. | 01-08-2015 |
20150032976 | METHOD OF SECURE MANAGEMENT OF A MEMORY SPACE FOR MICROCONTROLLER - A method of managing an electronic microcontroller system, the microcontroller system including: two processors with a first processor configured for execution of a nonsecure application exhibiting a nonguaranteed level of functional security and integrity, and a second processor dedicated to execution of a secure application implementing code and data, and involving a guaranteed level of functional security and integrity, the secure application to implement a security function; and a mechanism to access to a shared memory space. The first processor includes a unit for managing the memory configured to implement a write access control, to manage write access to the shared memory space, that is not modifiable when the secure application implements its security function. | 01-29-2015 |
20150039841 | AUTOMATIC TRANSACTION COARSENING - A processing device comprises an instruction execution unit and track and combing logic to combine a plurality of transactions into a single combined transaction. The track and combine logic comprises a transaction monitoring module to monitor an execution of a plurality of transactions by the instruction execution unit, each of the plurality of transactions comprising a transaction begin instruction, at least one operation instruction and a transaction end instruction. The track and combine logic further comprises a transaction combination module to identify, in view of the monitoring, a subset of the plurality of transactions to combine into a single combined transaction for execution on the processing device and to combine the identified subset of the plurality of transactions into the single combined transaction, the single combined transaction comprising a single transaction begin instruction, a plurality of operation instructions corresponding to the subset of the plurality of transactions and a single transaction end instruction. | 02-05-2015 |
20150067277 | MULTIPROCESSOR SYSTEM FOR RESTRICTING AN ACCESS REQUEST TO A SHARED RESOURCE - A multiprocessor system including a first processor element, and a second processor element that includes a CPU, a shared resource unit shared by the first and second processor elements, a protection setting unit and a guard unit, and the protection setting unit sets an access protection range for the shared resource unit, the guard unit restricts an access request from the first processor element to the shared resource unit based on the access protection range, the guard unit issues an exceptional access notification signal when the access request from the first processor element is within the access protection range, and when the exceptional access notification signal is issued, the CPU extends the access protection range in such a manner that the extended access protection range is wider than the access protection range set before issue of the exceptional access notification signal. | 03-05-2015 |
20150113233 | Automatic Mutual Exclusion - An automatic mutual exclusion computer programming system is disclosed which allows a programmer to produce concurrent programming code that is synchronized by default without the need to write any synchronization code. The programmer creates asynchronous methods which are not permitted make changes to shared memory that they cannot reverse, and can execute concurrently with other asynchronous methods. Changes to shared memory are committed if no other thread has accessed shared memory while the asynchronous method executed. Changes are reversed and the asynchronous method is re-executed if another thread has made changes to shared memory. The resulting program executes in a serialized order. A blocking system method is disclosed which causes the asynchronous method to re-execute until the blocking method's predicate results in an appropriate value. A yield system call is disclosed which divides asynchronous methods into atomic fragments. When a yield method call is made, shared memory changes are committed if possible or reversed and the atomic fragment is re-executed. | 04-23-2015 |
20150127915 | ARRAY OBJECT CONCURRENCY IN STM - A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object. | 05-07-2015 |
20150149737 | METHOD OR SYSTEM FOR ACCESS TO SHARED RESOURCE - Methods and/or systems are provided that may be utilized to read from or write to a resource, such as a shared memory, for example. | 05-28-2015 |
20150347317 | EVENT LOCK STORAGE DEVICE - A system and method are disclosed for an event lock storage device. The storage device includes a user partition and an event partition (which may be associated with an event). The storage device receives data from a host device, and stores the data in the user partition. In response to receiving an indication of an event, the storage device may designate the data as part of the event partition. The event partition may include a set of access rules that is different from the user partition, such as more restrictive rules for modification or deletion of a file containing the data. | 12-03-2015 |
20150347323 | ARRAY OBJECT CONCURRENCY IN STM - A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object. | 12-03-2015 |
20150347324 | System and Method for Shared Memory for FPGA Based Applications - A system for shared memory for field programmable gate array based application which includes a host computer, at least one field program gate array and a physical interface is disclosed. The host computer includes a host computer processor, a host computer memory, a shared memory, a host computer interface and a host computer design bus. The host computer design bus is electrically connected to the host computer processor, the host computer memory, the shared memory, and the host computer interface. The field program gate array includes a field program gate array processor, a field program gate array memory, a field program gate array design bus and a field program gate array interface. The field program gate array design bus is electrically connected to the field program gate array processor, the field program gate array interface and the field program gate array memory. | 12-03-2015 |
20160011990 | System and Method for Conflict-Free Cloud Storage Encryption | 01-14-2016 |
20160012241 | DISTRIBUTED DYNAMIC MEMORY MANAGEMENT UNIT (MMU)-BASED SECURE INTER-PROCESSOR COMMUNICATION | 01-14-2016 |
20160019168 | On-Demand Shareability Conversion In A Heterogeneous Shared Virtual Memory - The aspects include systems and methods of managing virtual memory page shareability. A processor or memory management unit may set in a page table an indication that a virtual memory page is not shareable with an outer domain processor. The processor or memory management unit may monitor for when the outer domain processor attempts or has attempted to access the virtual memory page. In response to the outer domain processor attempting to access the virtual memory page, the processor may perform a virtual memory page operation on the virtual memory page. | 01-21-2016 |
20160048464 | TECHNOLOGIES FOR SECURE INTER-VIRTUAL-MACHINE SHARED MEMORY COMMUNICATION - Technologies for secure inter-virtual-machine shared memory communication include a computing device with hardware virtualization support. A virtual machine monitor (VMM) authenticates a view switch component of a target virtual machine. The VMM adds configures a secure memory view to access a shared memory segment. The shared memory segment may include memory pages of a source virtual machine or the VMM. The view switch component switches to the secure memory view without generating a virtual machine exit event, using the hardware virtualization support. The view switch component may switch to the secure memory view by modifying an extended page table (EPT) pointer. The target virtual machine accesses the shared memory segment via the secure memory view. The target virtual machine and the source virtual machine may coordinate ownership of memory pages using a secure view control structure stored in the shared memory segment. Other embodiments are described and claimed. | 02-18-2016 |
20160070650 | RESETTING MEMORY LOCKS IN A TRANSACTIONAL MEMORY SYSTEM - A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register. | 03-10-2016 |
20160070660 | RESETTING MEMORY LOCKS IN A TRANSACTIONAL MEMORY SYSTEM - A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The system further includes the processor determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register. | 03-10-2016 |
20160188493 | INFORMATION PROCESSING APPARATUS - According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores, and local registers that store configuration information peculiar to the respective cores. The shared resource is provided independently from the plurality of cores. The local registers are provided to the respective cores. This makes it possible to provide an information processing apparatus that can suppress increase in hardware resources even when the number of cores composing a multi-core system increases. | 06-30-2016 |
20160253275 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND EXCLUSIVE CONTROL PROGRAM | 09-01-2016 |
20160378693 | INFORMATION PROCESSING APPARATUS AND PROGRAM EXECUTION METHOD - According to one embodiment, an information processing apparatus includes a processor and a memory. The processor operates in a first state and a second state. The memory includes a first region and a second region. A first program code is written in the second region. The first program code is executed when a call of the function provided by an operation system is invoked. A second program code is written in the first region. The processor executes the second program code to replace a first instruction included in the first program code with a second instruction. The second instruction is for switching the second state and the first state. | 12-29-2016 |
20170235490 | SECURED STORAGE SYSTEM WITH TEMPORARY EXTERNAL ASSIGNABLE MEMORY | 08-17-2017 |
20180024944 | METHODS AND APPARATUS FOR ACCESS CONTROL IN SHARED VIRTUAL MEMORY CONFIGURATIONS | 01-25-2018 |
20180024945 | Context-based protection system | 01-25-2018 |
20190146930 | EVENT LOCK STORAGE DEVICE | 05-16-2019 |