Class / Patent application number | Description | Number of patent applications / Date published |
711157000 | Interleaving | 80 |
20080215831 | Interleaver With Linear Feedback Shift Register - An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output. | 09-04-2008 |
20080222372 | TURBO DECODER - A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are in communication with a memory module that is internally split into non-overlapping memory banks. The turbo decoder includes respective sorter circuits in communication with the output of each BCJR processor/interleaver. A sorter circuit receives a data block from a BCJR processor/interleaver and directs the data block to the memory bank designated by an address assigned to the data block by an interleaver. | 09-11-2008 |
20080229035 | SYSTEMS AND METHODS FOR IMPLEMENTING A STRIDE VALUE FOR ACCESSING MEMORY - Systems and methods for implementing a stride valise for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. The plurality of memory storage units can be defined by a memory range of consecutive addresses. The system also comprises a memory test device configured to access a portion of the plurality of memory storage units in a sequence that repeats according to a programmable stride value. | 09-18-2008 |
20080250212 | METHOD AND APPARATUS FOR ACCESSING MEMORY USING PROGRAMMABLE MEMORY ACCESSING INTERLEAVING RATIO INFORMATION - A method and apparatus stores data representing a non 1:1 memory access interleaving ratio for accessing a plurality of memories. The method and apparatus interleaves memory accesses to at least either a first memory that is accessible via a first (and associated memory) bus having first characteristics or a second memory accessible via a second bus having different characteristics, based on the data representing the non 1:1 interleaving memory access ratio. | 10-09-2008 |
20080270713 | Method and System for Achieving Varying Manners of Memory Access - A method and system for operating a computer system are disclosed. In at least some embodiments, the present invention relates to a method of operating a computer system that includes operating a first cell of the system in accordance with a first memory access configuration, and migrating a first attribute of a first core of the first cell to a second cell of the system. The method additionally includes configuring a portion of the first cell so that the first cell is capable of operating in accordance with a second memory access configuration, and migrating at least one of the first attribute and a second attribute from the second cell back to the first core of the first cell, whereby subsequently the first cell operates in the second mode of operation. In at least some embodiments, the first and second configurations are direct and agent access memory configurations, or vice-versa. | 10-30-2008 |
20080270714 | Block Interleaving with Memory Table of Reduced Size - Interleaving improves noise rejection in digital communication and storage systems. According a known scheme, the interleaving/deinterleaving is achieved by storing symbols in a temporary memory table of R rows×C columns in a row by row order, and reading them in a column by column order, or vice versa, so obtaining a rearranged order. Methods and devices for interleaving and deinterleaving are proposed which accomplish the same interleaving/deinterleaving operation with a reduced size of the temporary memory table. The rearrangement of the symbols according to the rearranged order is accomplished by using a table with a reduced memory size, in combination with the order with which the symbols are fetched from or stored in a further memory. The invention further relates to ICs and apparatuses for interleaving and/or deinterleaving. | 10-30-2008 |
20080301383 | Multiple access for parallel turbo decoder - A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding. | 12-04-2008 |
20080307173 | Efficient Encoding for Detecting Load Dependency on Store with Misalignment - In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation. | 12-11-2008 |
20080320254 | VARIOUS METHODS AND APPARATUS TO SUPPORT TRANSACTIONS WHOSE DATA ADDRESS SEQUENCE WITHIN THAT TRANSACTION CROSSES AN INTERLEAVED CHANNEL ADDRESS BOUNDARY - A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel. | 12-25-2008 |
20080320255 | VARIOUS METHODS AND APPARATUS FOR CONFIGURABLE MAPPING OF ADDRESS REGIONS ONTO ONE OR MORE AGGREGATE TARGETS - An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable. | 12-25-2008 |
20090006790 | High Capacity Memory Subsystem Architecture Storing Interleaved Data for Reduced Bus Speed - A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving | 01-01-2009 |
20090013136 | De-Interleaving and Interleaving for Data Processing - Among others, techniques and apparatus are described for de-interleaving. A data processing apparatus includes a buffer to store interleaved data; an interleaving index producing unit to produce an interleaving index of the interleaved data; and an output control unit to output the data stored in the buffer using the interleaving index. | 01-08-2009 |
20090031094 | Method and device for interleaving data - A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output. | 01-29-2009 |
20090077330 | MODIFIED BRANCH METRIC CALCULATOR TO REDUCE INTERLEAVER MEMORY AND IMPROVE PERFORMANCE IN A FIXED-POINT TURBO DECODER - A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity. | 03-19-2009 |
20090113148 | METHODS FOR RESERVING INDEX MEMORY SPACE IN AVI RECORDING APPARATUS - A method for reserving memory space for storing chunk sizes during Audio Video Interleave (AVI) recording, wherein an AVI file contains a plurality of interleaved audio-video (A/V) chunks, includes: recording the AVI file sizes to the second storage; when the second storage reaches capacity, moving at least a first A/V chunk size to the first storage; and after the recording has finished, reading stored A/V chunks from the first storage to the second storage to create an index chunk. | 04-30-2009 |
20090132773 | APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMORY CONTROLLERS - We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command. | 05-21-2009 |
20090138668 | DATA INTERLEAVING CIRCUIT AND METHOD FOR VECTORIZED TURBO DECODER - A data interleaving circuit and method for interleaving a data block comprising M windows of W values include an index generator for generating an intra-window index w and an inter-window permutation vector | 05-28-2009 |
20090177852 | DATA BLOCK RECEIVER AND METHOD FOR DECODING DATA BLOCK - A data block receiver for decoding a data block. The data block has a block sequence number (BSN). The data block receiver includes two de-interleavers, a memory circuitry, a combiner, a decoder, and an error detector. A first de-interleaver interleaves the data block to obtain a first de-interleaved data block. A stored data block with a BSN same with the data block is retrieved from the memory circuitry when the data block is not the newest data block. The second de-interleaver interleaves the retrieved data block to obtain a second de-interleaved data block. The second and the first de-interleaved data blocks are combined to form a combined data block. The decoder decodes the combined data block. The data block is stored when an error in the decoded data block is detected. | 07-09-2009 |
20090198926 | METHOD AND DEVICE FOR SWITCHING DATA - A method, the method includes providing data; retrieving interleaving command information from a two dimensional array of interleaving command information; wherein the two dimensional array includes multiple interleaving command information rows, each row includes interleaving commands associated with multiple TDM time slots; and determining, in response to the retrieved interleaving command information, whether to provide data from a first data source or from a second data source. | 08-06-2009 |
20090204772 | Memory depth optimization in communications systems with ensemble PHY layer requirements - Memory depth optimization in communications systems with ensemble PHY layer requirements. Memory depth, for one or more modules in a communication device, is managed based on a limited amount of provisioned hardware. For example, each of a number of various modules within a communication device is configurable to operate at various memory depths. Considered together, various sets or profiles of operational parameters (e.g., associated with particular settings for each of the various modules within the communication device), may be employed to configure the communication device to operate in accordance with one of a variety of operational modes. For example, in a first operational mode, latency may be minimized (e.g., using shorted codewords, shorter interleaver depth, etc.), whereas in a second operational mode, a higher latency may be tolerated but with an expectation of much lower error rates (e.g., achieved using more powerful ECC, longer interleaver depth, etc.). | 08-13-2009 |
20090248997 | De-Interleaving using minimal memory - A de-interleaver for receiving data blocks including data units in an interleaved order, each data unit having a de-interleaved location within the data block, placing the data units in a memory buffer, and outputting the data units in a de-interleaved order from the memory buffer, the de-interleaver including an output unit configured to output a data unit from a location in the memory buffer of a next data unit in de-interleaved order, thereby to provide the data block in de-interleaved order, and an input unit configured with the output unit to input an incoming data unit, the incoming data unit being in the interleaved order, into the location in the memory buffer vacated by the next, in de-interleaved order, data unit being output. Related apparatus and methods are also described. | 10-01-2009 |
20090248998 | STORAGE SYSTEM, CONTROL UNIT, IMAGE FORMING APPARATUS, IMAGE FORMING METHOD, AND COMPUTER READABLE MEDIUM - A storage system includes: N pieces of storages that stores electronic information, N being an integral number that is two or more; and a controller that obtains electronic information to be written, wherein the controller, in a case where the electronic information to be written is a first kind of electronic information, divides the electronic information to be written into N pieces, and independently writes the divided electronic information into each of the N pieces of storage, and the controller, in the electronic information to be written is a second kind of electronic information, redundantly writes the electronic information to be written into each of the N pieces of storage. | 10-01-2009 |
20090300299 | Dynamic Interleaving - Methods and apparatus provide for a Dynamic Interleaver to modify the interleaving distribution spanning physical memory modules. Specifically, dynamic interleaving provides the ability to increase the number of interleaved physical memory modules when a current interleaved group of memory locations is experiencing heavy use. By increasing the number of interleaved memory locations, a system can make optimal use of memory by allowing more parallel accesses to physical memory during the period of heavy utilization. However, if the current interleaved group of memory locations experience low use, the Dynamic Interleaver can choose to interleave across fewer physical memory modules and apply power management techniques to those memory locations that are no longer being accessed. Prior to “re-interleaving” interleaved memory locations, the Dynamic Interleaver migrates data out of the current interleaved memory locations. After re-interleaving, the Dynamic Interleaver maps the data back into the re-interleaved memory locations. | 12-03-2009 |
20090300300 | MEMORY SHARING OF TIME AND FREQUENCY DE-INTERLEAVER FOR ISDB-T RECEIVERS - Time and frequency de-interleaving of interleaved data in an Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver includes exactly one random access memory (RAM) buffer in the ISDB-T receiver that performs both time and frequency de-interleaving of the interleaved data and a buffer address calculation module for generating buffer address in the buffer. The system performs memory sharing of the time and frequency de-interleaver for ISDB-T receivers and reduces the memory size required for performing de-interleaving in an ISDB-T receiver and combines the frequency and time de-interleaver buffers into one RAM thereby reducing the memory size. | 12-03-2009 |
20100011176 | Performance of binary bulk IO operations on virtual disks by interleaving - A method and system are provided for executing a binary bulk input/output (IO) operation on a first virtual disk and a second virtual using interleaving. The performance improvement due to the method is expected to increase as more information about the configuration of the virtual disks and their implementation are taken into account. Aspects of a binary bulk IO operation, which distinguish it from a unary bulk IO operation, are collection of information regarding both virtual disks and consideration of performance factors on both virtual disks, individually and jointly. Performance factors considered may include contention among tasks implementing the parallel process, load on the storage system(s) from other processes, performance characteristics of components of the storage system(s), and the virtualization relationships (e.g., mirroring, striping, and concatenation) among physical and virtual storage devices within the virtual configuration. | 01-14-2010 |
20100023711 | Interleaver Memory Allocation Method and Apparatus - According to one embodiment, memory is allocated between an interleaver buffer and a de-interleaver buffer in a communication device based on downstream and upstream memory requirements. The upstream de-interleaver memory requirement is determined based on upstream channel conditions obtained for a communication channel used by the communication device. The memory is allocated between the interleaver and de-interleaver buffers based on the downstream and upstream memory requirements. The downstream interleaver memory requirement may be determined based on one or more predetermined downstream configuration parameters. Alternatively, the downstream interleaver memory requirement may also be determined based on the upstream channel conditions by estimating the downstream capacity of the communication channel based on the upstream channel conditions and determining an interleaver buffer size that satisfies one or more predetermined downstream configuration parameters and the downstream capacity estimate. | 01-28-2010 |
20100030980 | MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD - The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands. | 02-04-2010 |
20100082917 | SOLID STATE STORAGE SYSTEM AND METHOD OF CONTROLLING SOLID STATE STORAGE SYSTEM USING A MULTI-PLANE METHOD AND AN INTERLEAVING METHOD - A solid state storage system includes a memory area configured to include a plurality of chips, and a micro controller unit (MCU) configured to perform a control operation, such that continuous logical block addresses are allocated using a multi-plane method or an interleaving method to different chips, and a read/write operation is performed in the logical block address unit in response to a read/write command. | 04-01-2010 |
20100106922 | Interleaver Memory Allocation Method and Apparatus - A first communication device estimates upstream channel conditions for an upstream channel and determines an upstream memory requirement for a first buffer at a second communication device and a first buffer at the first communication device based on the upstream channel conditions. A downstream memory requirement is received from the second communication device for a second buffer at the first communication device and a second buffer at the second communication device based on downstream channel conditions estimated at the second communication device for a downstream channel. The first communication device determines whether the sum of the upstream and downstream memory requirements exceeds an available amount of memory for implementing the first and second buffers at the first communication device and revises at least one of the memory requirements if the sum of the upstream and downstream memory requirements is different than the available amount of memory. | 04-29-2010 |
20100115214 | BRIDGING DEVICE HAVING A CONFIGURABLE VIRTUAL PAGE SIZE - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks. | 05-06-2010 |
20100146229 | Interleaver and de-interleaver for iterative code systems - In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector. | 06-10-2010 |
20100180089 | MANAGING THERMAL CONDITION OF A MEMORY - A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing. | 07-15-2010 |
20100250876 | System and Method for Memory Architecture Configuration - Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory. | 09-30-2010 |
20100262793 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SKEWING EXPECTED WEAROUT TIMES OF MEMORY DEVICES - A method in one embodiment includes writing first data to a first memory device of a memory array at a first number of writes per unit time; writing second data to a second memory device of the memory array at a second number of writes per unit time; and skewing expected wearout times of the memory devices by making the second number of writes per unit time less than the first number of writes per unit time. A method in another embodiment includes writing first data to a first memory device of a memory array; writing second data to a second memory device of the memory array; and skewing expected wearout times of the memory devices by making a number of available storage units cm the second memory device less than a number of available storage units on the first memory device. | 10-14-2010 |
20100287343 | CONTENTION FREE PARALLEL ACCESS SYSTEM AND A METHOD FOR CONTENTION FREE PARALLEL ACCESS TO A GROUP OF MEMORY BANKS - A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element from an odd memory unit of a pair of memory banks and fetches a second information element from an even memory unit of the pair of memory banks; wherein the first and second information elements are two consecutive interleaved address information elements. | 11-11-2010 |
20100293348 | APPARATUS AND METHOD OF REARRANGING DATA AND NONVOLITILE DATA STORAGE APPARATUS - A storage apparatus includes one or more memory units each having a plurality of memory blocks to store a file having data corresponding to a plurality of clusters, and a controller to store the file in the memory units such that such that the data of at least two sequential addresses of the clusters are stored in the memory blocks of different memory units. | 11-18-2010 |
20100318755 | REDUCED CONTENTION STORAGE FOR CHANNEL CODING - A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation. | 12-16-2010 |
20100325374 | DYNAMICALLY CONFIGURING MEMORY INTERLEAVING FOR LOCALITY AND PERFORMANCE ISOLATION - Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page. | 12-23-2010 |
20100332775 | HYBRID INTERLEAVING IN MEMORY MODULES - A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module. | 12-30-2010 |
20110010511 | INTERLEAVE CONTROL DEVICE, INTERLEAVE CONTROL METHOD, AND MEMORY SYSTEM - According to one embodiment, an interleave control device of a memory system includes a memory divided into sections, and a data bus used, in common, for data transfers for the sections, the device comprises a detector and a start module. The detector is configured to detect a transfer of data of a predetermined size during a transfer of data on the data bus to be written to a certain section of the memory or data read from the section. The start module is configured to start a transfer of interleave control data in place of the data to be written or the read data when the detector detects the transfer of the data of the predetermined size. | 01-13-2011 |
20110087849 | METHOD AND APPARATUS FOR IMPLEMENTING INTERLEAVING AND DE-INTERLEAVING AT SECOND TIME - A method for second interleaving is disclosed. The method comprises: generating an interleaving address preset in an interleaving matrix for each input data, and writing the data into the interleaving matrix according to the interleaving address; initializing the interleaving address and reading out the data from the interleaving matrix according to the interleaving address; judging whether the reading operation on a column of data in the interleaving matrix is completed or not, if completed, then calculating the interleaving address of the next column in the interleaving matrix according to inter-column replacement rules; otherwise, obtaining the interleaving address by adding its own value to the column spacing; judging whether the reading operations on all data are completed or not, if completed, then the second interleaving ending; otherwise, returning to the step of reading out the data from the interleaving matrix according to the interleaving address, and repeating the above operation. A method for second de-interleaving and the corresponding apparatus for second interleaving and de-interleaving are also disclosed. | 04-14-2011 |
20110125975 | INTERLEAVING APPARATUSES AND MEMORY CONTROLLERS HAVING THE SAME - An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data. | 05-26-2011 |
20110179239 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION DATA PROCESSING APPARATUS INCLUDING THE SAME - A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship. | 07-21-2011 |
20110252206 | MEMORY PROGRAMMING USING VARIABLE DATA WIDTH - A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words. | 10-13-2011 |
20110296124 | PARTITIONING MEMORY FOR ACCESS BY MULTIPLE REQUESTERS - An apparatus comprising a plurality of buffers and a channel router circuit. The buffers may be each configured to generate a control signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The channel router circuit may be configured to connect one or more of the buffers to one of a plurality of memory resources. The channel router circuit may be configured to return a data signal to a respective one of the buffers in an order requested by each of the buffers. | 12-01-2011 |
20110307672 | MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATION - A memory system communicates at least partially temporally overlapping write-data sequences associated with independent column write accesses on data links from a memory controller to a memory device via bidirectional links. Each of these write-data sequences may be associated with a different bank set in the memory IC. These bank sets may be micro-threaded so that each bank set is independently addressable and can concurrently perform operations associated with independent commands, including simultaneous column read/write. Furthermore, temporally interleaved data-mask information for the write-data sequences may be communicated from the memory controller to the memory IC via a data-mask link, so that alternate bits in the interleaved data-mask information may correspond to different write sequences. | 12-15-2011 |
20110307673 | RECONFIGURABLE INTERLEAVER HAVING RECONFIGURABLE COUNTERS - A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern. | 12-15-2011 |
20110320751 | Dynamic Interleaving Of Multi-Channel Memory - In a particular embodiment, a dynamic interleaving system changes the number of interleaving channels of a multi-channel memory based on a detected level of bandwidth requests from a plurality of master ports to a plurality of slave ports. At a low level of bandwidth requests, the number of interleaving channels is reduced. | 12-29-2011 |
20120005438 | INPUT/OUTPUT CONTROL APPARATUS AND INFORMATION PROCESSING APPARATUS - An apparatus that enables data to be input to and output from a first processing device that performs an arithmetic operation and outputs first data, a second processing device that performs an arithmetic operation and outputs second data that has a number of bits which is smaller than the first data, a first storage device and a second storage device. The apparatus includes a data dividing unit and a storage control unit. The data dividing unit divides the first data output from the first processing device. The storage control unit causes the divided first data to be stored in the first storage device and the second storage device and causes the second data output from the second processing device to be stored in one of the first and second storage devices. | 01-05-2012 |
20120137090 | Programmable Interleave Select in Memory Controller - In one embodiment, a memory controller may be configured to perform a logic operation, such as a hash function, on selected address bits to produce a bit of channel or bank select. The selected address bits for each select bit may differ, and may be programmable in some embodiments. By combining selected address bits to produce the select bits, the distribution of addresses in a set of regular access patterns may be somewhat randomized to the channels/banks. In one implementation, each select bit may have a corresponding programmable bit vector that specifies the address bits to be included for that select bit. Accordingly, any subset of the address bits may be included in any select bit generation. | 05-31-2012 |
20120173829 | INTERLEAVER AND INTERLEAVING METHOD - An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an address queue among the address queues that is not empty based on status of each address queue; decoding the address from the selected address queue to a read-address and a bit-address; extracting a read-word from data to be interleaved based on the read-address; selecting a write-bit from the read-word based on the bit-address; arbitrating an individual write-bit to one of the write-words based on an address queue ID of the selected address queue; and generating write-addresses for respective write-words. | 07-05-2012 |
20120179883 | System and method for dynamically adjusting memory performance - According to an exemplary embodiment, a method for dynamically adjusting memory performance includes detecting a bandwidth of a data transfer. Detecting the bandwidth can comprise measuring a data stream of the data transfer and determining the bandwidth based on the measuring. The method further includes selecting a subset of a plurality of interleaved memory units based on the bandwidth. A device performing the data transfer can comprise a power supply and the selecting can be based on a power level of the power supply. The selecting can also be based on a temperature of the device performing the data transfer. The method also includes performing a data access for the data transfer using the subset of the plurality of interleaved memory units. | 07-12-2012 |
20120185655 | DISK CONTROLLER CONFIGURED TO PERFORM OUT OF ORDER EXECUTION OF WRITE OPERATIONS - A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor. | 07-19-2012 |
20120317378 | INTERLEAVING DEVICE AND INTERLEAVING METHOD - Disclosed are an interleaving device and an interleaving method which shorten processing time for channel interleaving. A CQI memory writing unit ( | 12-13-2012 |
20130031319 | INTERLEAVING OF MEMORY REPAIR DATA COMPRESSION AND FUSE PROGRAMMING OPERATIONS IN SINGLE FUSEBAY ARCHITECTURE - An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data. | 01-31-2013 |
20130151799 | Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions - Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests. | 06-13-2013 |
20130166860 | MEMORY ACCESS CONTROL DEVICE AND COMPUTER SYSTEM - A memory interleaving device accesses a memory in an interleaved manner for changing the number of ways of interleaving during system operation. During a copy which changes a first configuration before changing the number of ways in the interleaving to a second configuration after changing the number of ways in the interleaving, a memory access control device reads the memory in the first configuration before changing the number of ways of the interleaving for an external read request and writes the memory in both of the first configuration before changing the number of ways in the interleaving and the second configuration after changing the number of ways in the interleaving for an external write request. | 06-27-2013 |
20130173874 | System and Method for Pre-interleaving Sequential Data - A method and system for operating a memory device in programming mode is disclosed. The memory device includes a programming mode and a normal mode. The memory device in programming mode increases the number of physical planes that can be programmed in parallel than can be programmed in normal mode. In this way, the memory device may be programmed more quickly at various times of operation of the memory device (such as during manufacturing). The host system may send rearranged data to the memory device in programming mode with the rearranged data accounting for the increased number of physical planes programmed in parallel. | 07-04-2013 |
20130198464 | EFFICIENT READ AND WRITE OPERATIONS - Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating transferring of fixed size portions of the file data to a first buffer and a second buffer, alternating processing of data blocks of the fixed sized portions in parallel from the first and second buffers by a plurality of processing threads, and outputting the processed data blocks. | 08-01-2013 |
20130227233 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR INTEGRATED SUB-BLOCK INTERLEAVING AND RATE MATCHING - Methods, systems, and computer readable media for fast, reduced memory and integrated sub-block interleaving and rate matching are disclosed. According to one aspect, the subject matter described herein includes a system for integrated sub-block interleaving and rate matching, which includes a buffer memory for storing sub-block data that has been encoded according to a channel encoding algorithm and a rate matching module for reading the sub-block data from the buffer memory using a sequence of addresses according to an interleaving algorithm, such that data is transferred from the buffer memory to the rate matching module in an order that emulates the order that the data would be produced by the interleaving algorithm or in the order that the data would be produced by the interleaving algorithm as modified by a rate matching algorithm. | 08-29-2013 |
20130254499 | INTERLEAVING AND DE-INTERLEAVING METHOD, INTERLEAVER AND DE-INTERLEAVER - The present invention relates to an interleaving and de-interleaving method, an interleaver and a de-interleaver. The interleaving method includes: receiving N×M frames of data, and sequentially storing, with each frame as a unit, the N×M frames of data in storage space indicated by N×M addresses of a first storage unit; transferring the data stored in the storage space indicated by an ((X−1)×M+Y+1) | 09-26-2013 |
20130339640 | MEMORY SYSTEM AND SOC INCLUDING LINEAR ADDRESSS REMAPPING LOGIC - A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address. | 12-19-2013 |
20140025908 | FAST MECHANISM FOR ACCESSING 2n.+-.1 INTERLEAVED MEMORY SYSTEM - A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2 | 01-23-2014 |
20140040571 | DATA INTERLEAVING MODULE - The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register. | 02-06-2014 |
20140082306 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION DATA PROCESSING APPARATUS INCLUDING THE SAME - A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship. | 03-20-2014 |
20140164720 | SYSTEM AND METHOD FOR DYNAMICALLY ALLOCATING MEMORY IN A MEMORY SUBSYSTEM HAVING ASYMMETRIC MEMORY COMPONENTS - Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients. | 06-12-2014 |
20140337589 | PREVENTING A HYBRID MEMORY MODULE FROM BEING MAPPED - A system includes a hybrid memory module. The hybrid memory module includes volatile memory and non-volatile memory. The system further includes a processor coupled to the hybrid memory module. The processor prevents the hybrid memory module from being mapped during a memory initialization routine by misrepresenting a status of the hybrid memory module. | 11-13-2014 |
20140351529 | TECHNIQUES FOR ORGANIZING THREE-DIMENSIONAL ARRAY DATA - Various embodiments are generally directed to storing data of a three-dimensional (3D) array in a tiled manner in which adjacent rows of adjacent planes are interleaved to enable more efficient retrieval in performing 3D stencil calculations. An apparatus to perform a stencil calculation includes a processor component, a storage communicatively coupled to the processor component, and an interleaving component for execution by the processor component to interleave storage of data of cells of adjacent rows of a first plane with data of cells of adjacent rows of an adjacent second plane of a 3D array among contiguous storage locations of the storage. Other embodiments are described and claimed. | 11-27-2014 |
20150026420 | MEMORY ACCESS USING ADDRESS BIT PERMUTATION - An apparatus including a memory having an array of blocks addressable using address bits; and a permutation circuit coupled to the memory and configured to permutate the address bits such that during a memory access blocks of data are rearranged virtually. | 01-22-2015 |
20150081989 | SEMICONDUCTOR DEVICES INCLUDING APPLICATION PROCESSOR CONNECTED TO HIGH-BANDWIDTH MEMORY AND LOW-BANDWIDTH MEMORY, AND CHANNEL INTERLEAVING METHOD THEREOF - A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device. | 03-19-2015 |
20150089168 | NESTED CHANNEL ADDRESS INTERLEAVING - A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits. | 03-26-2015 |
20150095594 | Method and Apparatus for Bit-Interleaving - A manner of processing data for transmission in a data communication network. Node having a main memory and an interleaver is provided. Received data is stored in the main memory and a bandwidth map is prepared. The data is then selectively read out and pre-processing according to the bandwidth map and stored in an interleaver memory. The date is later read out and post-processed before interleaving into a downstream data frame. The pre- and post-processing provide the data in a more efficient form for interleaving. | 04-02-2015 |
20150095595 | CONFIGURABLE SPREADING FUNCTION FOR MEMORY INTERLEAVING - A method of interleaving a memory by mapping address bits of the memory to a number N of memory channels iteratively in successive rounds, wherein in each round except the last round: selecting a unique subset of address bits, determining a maximum number (L) of unique combinations possible based on the selected subset of address bits, mapping combinations to the N memory channels a maximum number of times (F) possible where each of the N memory channels gets mapped to an equal number of combinations, and if and when a number of combinations remain (K, which is less than N) that cannot be mapped, one to each of the N memory channels, entering a next round. In the last round, mapping remaining most significant address bits, not used in the subsets in prior rounds, to each of the N memory channels. | 04-02-2015 |
20150100746 | SYSTEM AND METHOD FOR UNIFORM INTERLEAVING OF DATA ACROSS A MULTIPLE-CHANNEL MEMORY ARCHITECTURE WITH ASYMMETRIC STORAGE CAPACITY - Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space. | 04-09-2015 |
20150106577 | DE-INTERLEAVING ON AN AS-NEEDED BASIS - One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module. | 04-16-2015 |
20150121019 | DATA PROCESSING DEVICE AND METHOD FOR INTERLEAVED STORAGE OF DATA ELEMENTS - A data processing device | 04-30-2015 |
20150301940 | Self-Configurable Device for Interleaving/Deinterleaving Data Frames - A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network. | 10-22-2015 |
20160124849 | MEMORY SYSTEM AND SOC INCLUDING LINEAR ADDRESSS REMAPPING LOGIC - A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address. | 05-05-2016 |
20160124851 | MEMORY SYSTEM AND SoC INCLUDING LINEAR REMAPPER AND ACCESS WINDOW - A system on chip which is connected with a plurality of memory chips includes first and second processors, a first access window, a first linear remapper, and a memory controller. The first and second processors are configured to provide an address for using the plurality of memory chips. The first access window sets an area, accessed only by the first processor, from among address areas of one or more of the plurality of memory chips. The first linear remapper remaps an address received from the first processor. The memory controller performs a partial linear access operation with respect to the plurality of memory chips, based on an area set by the first access window and an address remapped by the first linear remapper. | 05-05-2016 |
20160132248 | HIGH PERFORMANCE SYSTEM FOR SELECTIVE MERGING OFDATAFRAME SEGMENTS - A method of writing data to a range of logical blocks in a storage medium includes: receiving a command including a starting logical block address, a value indicating a range of logical block addresses to be written, and a logical block of data; storing the logical block in a first temporary storage; generating a logical page by duplicating the logical block a plurality of times corresponding to a number of logical blocks in a logical page and transporting the generated logical page to a second temporary storage and storing the generated logical page in the second temporary storage; writing the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address; and performing a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary. | 05-12-2016 |