Class / Patent application number | Description | Number of patent applications / Date published |
711201000 | Slip control, misaligning, boundary alignment | 8 |
20080235484 | Method and System for Host Memory Alignment - Certain aspects of a method and system for host memory alignment may include splitting a received read and/or write I/O request at a first of a plurality of memory cache line boundaries to generate a first portion of the received I/O request. A second portion of the received read and/or write I/O request may be split into a plurality of segments so that each of the plurality of segments is aligned with one or more of the plurality of memory cache line boundaries. A cost of memory bandwidth for accessing host memory may be minimized based on the splitting of the second portion of the received read and/or write I/O request. | 09-25-2008 |
20080288742 | METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING PAGE SIZE IN A VIRTUAL MEMORY RANGE - The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for adjusting a page size for a virtual memory range. The process identifies a set of pages in the virtual memory range that reside on a primary memory to form a page occupancy. Each of the set of pages has a first page size. The process changes the first page size to a second page size in response to a comparison of the page occupancy to a threshold value indicating that the first page size should be adjusted. | 11-20-2008 |
20080294866 | Method And Apparatus For Memory Management - An apparatus and a method for managing a memory are presented. In one example embodiment, the method and the apparatus includes a memory that has one or more partitions. Each of the partitions includes one or more zones. Each of the zones includes one or more memory ranges. In this example embodiment, the method begins by determining occurrence of memory shortage in a first partition of the memory during runtime of the apparatus. Based on the outcome of the determination, during runtime of the apparatus, the memory from the one or more zones of the one or more partitions of the memory is claimed by instantiating invocation of memory claiming process. | 11-27-2008 |
20100049939 | METHOD FOR ADDRESS COMPARISON AND A DEVICE HAVING ADDRESS COMPARISON CAPABILITIES - A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment. | 02-25-2010 |
20100293355 | Fast data access through page manipulation - A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate. | 11-18-2010 |
20110082999 | DATA PROCESSING ENGINE WITH INTEGRATED DATA ENDIANNESS CONTROL MECHANISM - A data processing engine is provided, which includes an endian register, an endian control device, and a byte swapper. The endian register stores a plurality of endian control bits. Each endian control bit indicates the default data endianness of a type of address space accessible to the data processing engine. Each endian control bit is in either a big-endian state or a little-endian state. The endian control device is coupled to the endian register. The endian control device provides an endian signal according to the endian control bits and the instruction executed by the data processing engine. The endian signal is in either the big-endian state or the little-endian state. The byte swapper is coupled to the endian control device. The byte swapper transmits data and changes the byte order of the data when the byte order of the data is inconsistent with the state of the endian signal. | 04-07-2011 |
20130036290 | METHODS OF AND APPARATUS FOR STORING DATA IN MEMORY IN DATA PROCESSING SYSTEMS - A data array | 02-07-2013 |
20140082321 | PROCESS VARIATION TOLERANT BANK COLLISION DETECTION CIRCUIT - A process variation tolerant collision detection apparatus for use in detecting collisions in a multibank memory. The apparatus may receive a plurality of memory commands for execution at the multibank memory. The plurality of memory commands may be compared by an index address comparator and a bank address comparator to generate an index match signal and a bank match signal. The index match signal and the bank match signal may be analyzed by a timing correction module such that errors associated with process variation of the signals used in the system may be eliminated. Accordingly, a corrected index match signal and a corrected bank match signal may be provided to a collision detection circuit to determine whether a collision exits. | 03-20-2014 |