Class / Patent application number | Description | Number of patent applications / Date published |
712236000 | Evaluation of multiple conditions or multiway branching | 8 |
20090070567 | EFFICIENT IMPLEMENTATION OF BRANCH INTENSIVE ALGORITHMS IN VLIW AND SUPERSCALAR PROCESSORS - An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at the guard input. A lookup table is dynamically programmed with logic to implement an upcoming branching portion of program code. Upon evaluation of the branch conditions of the branching portion of code, the lookup table outputs a selection signal for writing the correct results of the branching portion of code based on the evaluation of the branch condition statements and the truth table programmed into the lookup table to the result register. | 03-12-2009 |
20090249047 | METHOD AND SYSTEM FOR RELATIVE MULTIPLE-TARGET BRANCH INSTRUCTION EXECUTION IN A PROCESSOR - A method and system for relative multiple-target branch instruction execution in a processor is provided. One implementation involves receiving an instruction for execution; determining a next instruction to execute based on multiple condition bits or outcomes of a comparison by the current instruction; obtaining a specified instruction offset in the current instruction; and using the offset as the basis for multiple instruction targets based on said outcomes, wherein the number of conditional branches is reduced. | 10-01-2009 |
20120210107 | PREDICATED ISSUE FOR CONDITIONAL BRANCH INSTRUCTIONS - A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between the branch instruction and the target instruction. The method further includes issuing the one or more interceding instructions and the target instruction and determining if the branch instruction follows the first path or the second path. Upon determining that the branch instruction follows the first path, the one or more interceding instructions between the branch instruction and the target instruction are invalidated. | 08-16-2012 |
20120331278 | BRANCH REMOVAL BY DATA SHUFFLING - A system and method for automatically optimizing parallel execution of multiple work units in a processor by reducing a number of branch instructions. A computing system includes a first processor core with a general-purpose micro-architecture and a second processor core with a same instruction multiple data (SIMD) micro-architecture. A compiler detects and evaluates branches within function calls with one or more records of data used to determine one or more outcomes. Multiple compute sub-kernels are generated, each comprising code from the function corresponding to a unique outcome of the branch. Multiple work units are produced by assigning one or more records of data corresponding to a given outcome of the branch to one of the multiple compute sub-kernels associated with the given outcome. The branch is removed. An operating system scheduler schedules each of the one or more compute sub-kernels to the first processor core or to the second processor core. | 12-27-2012 |
20140344557 | METHOD AND SYSTEM TO AUTOMATICALLY ENFORCE A HYBRID BRANCHING STRATEGY - A method and system for automatically enforcing a hybrid branching strategy include receiving a changeset designated for a branch. In response to receiving the changeset, the system may automatically determine whether a merge conflict associated with the changeset exists between the branch and an associated protected branch, and the system may automatically determine whether the changeset is up to date. Upon determining that no merge conflict exists, the system automatically initiates execution of a continuous integration testing pipeline. The continuous integration testing pipeline includes a series of tests applied to the changeset. If the changeset passes the series of tests, the system automatically merges the changeset with the associated protected branch. | 11-20-2014 |
20150058606 | BRANCH TRACE COMPRESSION - Exemplary methods, apparatuses, and systems generate a plurality of possible branch traces for a computer program. Each possible branch trace represents different sequences of branch instructions that may be executed while the computer program is running. Each branch instruction has a corresponding identifier. A branch trace value is generated for at least one of the plurality of possible branch traces. Generating the branch trace value includes performing a mathematical or logical operation between a first identifier and each subsequent identifier of the possible branch trace to obtain the branch trace value. An output including a branch trace is generated based upon a match between a run-time branch trace value and the at least one generated branch trace value. | 02-26-2015 |
20150121049 | SAFE CONDITIONAL-LOAD AND CONDITIONAL-STORE OPERATIONS - One embodiment is a computer-implemented method for safe conditional operation when storage access cannot be proven safe. The method includes receiving a portion of source code for a transaction by an enhanced compiler and. The portion of source code received is analyzed, by the enhanced compiler, to determine whether the portion of source code is a candidate for transformation. Responsive to a determination that the portion of source code analyzed by the enhanced compiler is a candidate for transformation, the portion of the source code analyzed is transformed, by a computer processor, to use a conditional operation in a first portion of the transformed code. The conditional operation uses hardware transaction memory to invoke retry operations within hardware. A branch is added, directed to an original code portion, in a second portion of transformed code, where the branch is a recovery portion containing the original code portion. | 04-30-2015 |
20160188339 | VARIABLE UPDATES OF BRANCH PREDICTION STATES - Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit. | 06-30-2016 |