Class / Patent application number | Description | Number of patent applications / Date published |
713375000 | SYNCHRONIZATION OF PLURAL PROCESSORS | 47 |
20080229134 | RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM - In processors having buffers to manage instruction flow referred to as a ReOrder Buffer (ROB) it is shown that these buffers are of the same approximate size of a checkpoint array for architected state. In a particular “morphing mode” in which a pair of processors can be configured to provide different functionalities on demand, a new “High-Reliability” (HR) mode is provided in which the ROB of one of the processors is used for a checkpoint array, and the pair of processors is made to run in lockstep on a single instruction stream under the control of the remaining ROB so as to provide redundant, hence highly-reliable computing. | 09-18-2008 |
20080263379 | WATCHDOG TIMER DEVICE AND METHODS THEREOF - To detect a non-responsive condition at a processor, a counter is associated with an operation at a first stage of an instruction pipeline. A value stored in the counter is periodically adjusted towards a threshold value. An error indicator is provided in response to the value stored in the counter reaching the threshold value thereby indicating that a defined amount of time expired before a subsequent stage has completed processing of the operation. However, if the subsequent stage completes processing of the operation prior to the value stored in the counter reaching the threshold, the counter is automatically disassociated with the operation and can, therefore, be associated with another operation at the first stage of the pipeline. Accordingly, the counter does not use an explicit instruction that is responsible for resetting its value. | 10-23-2008 |
20080294925 | SERIAL COMMUNICATION SYSTEM AND SERIAL COMMUNICATION METHOD - In a serial communication system in which data is transmitted from a first unit to a second unit in synchronization with a clock signal, the mode of communication between the first and second units is switched between a first communication mode in which data is transmitted from the second unit to the first unit in synchronization with the clock signal, and a second communication mode in which a signal asynchronous to the clock signal is transmitted from the first unit to the second unit. | 11-27-2008 |
20080313484 | Parallel Processing of Multi-Dimensional Data With Causal Neighborhood Dependencies - A method (which can be computer implemented) for processing a plurality of adjacent rows of data units, using a plurality of parallel processors, given (i) a predetermined processing order, and (ii) a specified inter-row dependency structure, includes the steps of determining starting times for each individual one of the processors, and maintaining synchronization across the processors, while ensuring that the dependency structure is not violated. Not all the starting times are the same, and a sum of absolute differences between (i) starting times of any given processor, and (ii) that one of the processors having an earliest starting time, is minimized. | 12-18-2008 |
20090006879 | Session Redundancy Using a Replay Model - A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to synchronize the state of the components and the time and resources required to perform the synchronization, the state-related information transmitted from the first routing engine to the second routing engine is limited to information used to build states of a subset of the components associated with the first routing engine. That subset of components is limited to those components that receive stimuli (e.g., data streams or data packets) from sources external to the routing engine. Other components on the second routing engine synchronize state by receiving information from those components on the second routing engine that received the external stimuli information. | 01-01-2009 |
20090049323 | SYNCHRONIZATION OF PROCESSORS IN A MULTIPROCESSOR SYSTEM - A method for synchronizing a first processor and multiple second processors is presented. In the method, each of the second processors waits at a second synchronization point after reaching a first synchronization point. The last of the second processors to reach the first synchronization point sends a signal to the first processor. The first processor waits at the first synchronization point until it receives the signal. After receiving the signal, the first processor initiates a launch of the second processors by launching at least one of the second processors. At least one of the second processors launched by the first processor launches another of the second processors in response to being launched by the first processor. Each of the second processors continues execution from the second synchronization point in response to being launched. | 02-19-2009 |
20090055674 | Method and device for a switchover and for a data comparison in a computer system having at least two processing units - A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data. | 02-26-2009 |
20090063885 | System and Computer Program Product for Modifying an Operation of One or More Processors Executing Message Passing Interface Tasks - A system and computer program product for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors. | 03-05-2009 |
20090100283 | Method for switching between two redundant oscillator signals within an alignment element - A method for switching between two oscillator signals within an alignment element, wherein one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. Said method comprises the steps of:
| 04-16-2009 |
20090158075 | SYNCHRONIZATION OF INDEPENDENT CLOCKS - A system and method to synchronize independent local clocks in multi-core processing system are disclosed. A shared counter or a shared memory/file is provided to establish a partial happened-before relationship (e | 06-18-2009 |
20090164826 | Method and device for synchronizing in a multiprocessor system - A method and a device for synchronization in a multiprocessor system having at least two processors, switchover means being provided which make it possible to switch between at least two operating modes, the device being designed in such a way that a synchronization is performed using a stop signal which stops a processor running ahead in order to synchronize it with the at least [one] second processor. | 06-25-2009 |
20090193279 | METHOD FOR ENABLING MULTI-PROCESSOR SYNCHRONIZATION - A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value. | 07-30-2009 |
20090222683 | Synchronization of Processor Time Stamp Counters to Master Counter - In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing. | 09-03-2009 |
20090300401 | PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYCHRONIZING TOD CLOCKS - A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function. | 12-03-2009 |
20090327788 | CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS - Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed. | 12-31-2009 |
20100023791 | Process for digital, bidirectional data transmission - The invention relates to a process for digital, bidirectional data transmission between a processing unit and a position encoder, as based on the transmission of frames of a predetermined bit length, such that each frame is provided with at least an initial bit length for the transmission of data from the processing unit to the position encoder and at least a second bit length for the transmission of data from the position encoder to the processing unit; and such that the frame is provided with a time slot in which data is neither transmitted from the processing unit to the position encoder nor from the position encoder to the processing unit. In the time slot a triggering signal (external sync signal) is transmitted from the processing unit to the position encoder and this triggers the acquisition of position data. In the first bit length, a clock signal for synchronizing the processing unit and the position encoder is transmitted from the processing unit to the position encoder, and after the acquisition of position data triggered by the external sync signal, the acquired position data is transmitted from the position encoder to the processing unit. Between the transmission of two successive external sync signals at least one additional position-data request signal (internal sync signal) is transmitted from the processing unit to the position encoder, and this signal triggers another acquisition of position data, which is followed by the transmission of the acquired position data from the position encoder to the processing unit. | 01-28-2010 |
20100058095 | Method and Apparatus for Synchronizing Central Processing Units in a Multiprocessor Apparatus - Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU | 03-04-2010 |
20100077246 | Microprocessor system having a plurality of microprocessors which are connected to one another by signaling technology - A microprocessor system includes a plurality of microprocessors which are connected to one another by signaling technology. In order to temporally synchronize the microprocessors in a relatively simple manner, it is proposed in at least one embodiment that provision be made of a central clock generator which outputs a clock signal in the form of temporally successive pulses to all microprocessors in a parallel manner, that provision be made of a master which can switch the output of the clock signal on and off, that all microprocessors sum the clock signal from the central clock generator in the form of a counter reading in each case, that the master be able to reset the counter readings of all microprocessors. In at least one embodiment, in order to synchronize all microprocessors, the master first of all interrupt the output of the clock signal, then set all counter readings to a defined value, and then cancel the interruption of the output of the clock signal again. | 03-25-2010 |
20100088535 | SYNCHRONIZATION CONTROL APPARATUS, INFORMATION PROCESSING APPARATUS, AND SYNCHRONIZATION MANAGEMENT METHOD - A synchronization control apparatus includes a counter that carries out a counting and outputs resulting count information, a timeout time holder that holds a predetermined timeout time and outputs the timeout time, a comparator that compares the count information output from the counter and the timeout time output from the timeout time holder, a synchronization controller that monitors a synchronization between a first processor and a second processor by comparing an output from the first processor and an output from the second processor and starts a counting, when a mis-match of the outputs from the first processor and the second processor is detected and wherein the comparator detects that the count information and the timeout time match, the comparator stops either the first processor or second processor in which a synchronization delay has occurred. | 04-08-2010 |
20100115322 | SYNCHRONOUS OPERATION OF A SYSTEM WITH ASYNCHRONOUS CLOCK DOMAINS - A system may be employed for allowing the synchronous operation of an asynchronous system. The system may be a system that may include multiple clusters. The clusters may include asynchronous clock domains and may also receive a global clock signal through a global clock grid that may overlay the system. Furthermore, a method may be employed for synchronizing asynchronous clock domains within a cluster. The method of synchronizing may include providing a global clock that corresponds to a global clock grid to each cluster. Additionally, the method of synchronizing may include accounting for the mismatch between the asynchronous clock domains by employing logic in a block. | 05-06-2010 |
20100169693 | STATE HISTORY STORAGE FOR SYNCHRONIZING REDUNDANT PROCESSORS - Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage. | 07-01-2010 |
20100180140 | DATA PROCESSING SYSTEM AND IMAGE PROCESSING SYSTEM - A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside. | 07-15-2010 |
20100299550 | Two Global Precise Times For Synchronization - Method of controlling a wind power system comprising a plurality of system elements, the wind power system including a plurality of data processors distributed in the system elements, the method includes the steps of: synchronizing at least a part of the data processors to at least one reference signal distributed to the data processors from a time synchronization arrangement, associating the data processors with local clock generation circuitries, wherein the local clock generation circuitries associated with data processors of a first subset of the data processors have a peak-to-peak tracking jitter higher than or equal to a predetermined threshold value and wherein a second subset of the data processors have a peak-to-peak tracking jitter less than the predetermined threshold value, controlling at least one of said system elements at least partly by mechanism of a data processor from said first or second subset of data processors. | 11-25-2010 |
20100318830 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings. | 12-16-2010 |
20110113277 | PROCESSING UNIT, PROCESS CONTROL SYSTEM AND CONTROL METHOD - A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication. | 05-12-2011 |
20110185214 | TIME FORMAT CONVERSION METHOD, DEVICE AND SYSTEM - A method and device for converting between different time domains at a local unit utilizing an processor is disclosed. Time counters to count time in at least two different formats are located locally at each unit. Once a time conversion is initiated, a time stamp is received by the processor and the time counter in the new time domain commences calculating an adjustment count. Once the converted time is received from the processor, the received time plus the adjustment count are summed to provide a time base for the new time domain. The time counters continue counting in their respective time domains after conversion. | 07-28-2011 |
20110231691 | Synchronization in data processing layers - A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy. | 09-22-2011 |
20110252262 | STORAGE SYSTEM HAVING PLURAL MICROPROCESSORS, AND PROCESSING ALLOTMENT METHOD FOR STORAGE SYSTEM HAVING PLURAL MICROPROCESSORS - In a storage system which includes a plurality of microprocessors, it is desired to prevent delay in I/O responses due to synchronous' processing waiting for asynchronous processing, while still ensuring the throughput of asynchronous processing. In a plurality of microprocessors possessed by a controller, synchronous processors and asynchronous processors are mixed together. The synchronous processors are microprocessors whose duty is to perform synchronous processing and not to perform asynchronous processing. And the asynchronous processors are microprocessors whose duty is to perform asynchronous processing and not to perform synchronous processing. | 10-13-2011 |
20110314321 | HIGH SPEED DIGITAL BIT STREAM AUTOMATIC RATE SENSE DETECTION - As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are support, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits present used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust. | 12-22-2011 |
20120005516 | SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM - A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock. | 01-05-2012 |
20120072757 | Session Redundancy Using a Replay Model - A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to synchronize the state of the components and the time and resources required to perform the synchronization, the state-related information transmitted from the first routing engine to the second routing engine is limited to information used to build states of a subset of the components associated with the first routing engine. That subset of components is limited to those components that receive stimuli (e.g., data streams or data packets) from sources external to the routing engine. Other components on the second routing engine synchronize state by receiving information from those components on the second routing engine that received the external stimuli information. | 03-22-2012 |
20120096300 | COMMUNICATION CIRCUIT AND COMMUNICATION METHOD - Provided is a communication circuit ( | 04-19-2012 |
20120173913 | SYSTEM AND METHOD TO AVOID RESYNCHRONIZATION WHEN PROTECTING MULTIPLE SERVERS - In a computer system, a standby master processor is configured to serve as a backup processor for an active master processor. A third party replica processor is configured to monitor and record changes on the active master processor when the active master processor is executing, and is further configured to synchronize itself with the standby master processor when the standby master processor takes over execution from the active master processor. Logs of changes are maintained. A negotiation occurs between the standby master processor and the third party replica processor to determine the status of the logs of the standby master processor and the third party replica processor, and logs are applied or paused relating to one or more of the standby master processor and the third party replica processor to synchronize the standby master processor and the third party replica processor. | 07-05-2012 |
20120233486 | LOAD BALANCING ON HETEROGENEOUS PROCESSING CLUSTERS IMPLEMENTING PARALLEL EXECUTION - Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment. | 09-13-2012 |
20130227328 | MASSIVELY PARALLEL COMPUTER, AND METHOD AND PROGRAM FOR SYNCHRONIZATION THEREOF - The a massively parallel computer including a plurality of CPUs to implement barrier synchronization by using a global barrier synchronous counter, wherein the CPUs each comprises a computation core including a GBF cache which caches a part of a plurality of global barrier synchronous flags for controlling synchronization between the CPUs, and a communication control unit including the global barrier synchronous flag, when making a request for reference to the global barrier synchronous flag, the computation core first referring to the GBF cache and only when the reference has a cache miss, making a request to the communication control unit to refer to the global barrier synchronous flag. | 08-29-2013 |
20130246830 | SYNCHRONIZING A DEVICE THAT HAS BEEN POWER CYCLED TO AN ALREADY OPERATIONAL SYSTEM - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device. | 09-19-2013 |
20130254582 | SYNCHRONIZATION APPARATUS AND FIELD DEVICE - A synchronization apparatus synchronizing an operation of a first processing unit pre-processing an input signal and an operation of a second processing unit post-processing on signal from the first processing unit, may include: a counting unit that operates with a period sufficiently shorter than a period of a first reference signal governing timing of pre-processing in the first processing unit, and outputting, when counting a set target count value, a second reference signal governing timing of post-processing in the second processing unit; a phase control unit that generates a control value controlling a phase difference of the second reference signal with respect to the first reference signal in accordance with a count value when the first reference signal is input; and a filter unit that filters the generated control value so as to determine the target count value to be set in the counting unit. | 09-26-2013 |
20130318390 | INFORMATION PROCESSING APPARATUS, METHOD OF MEASURING DELAY DIFFERENCE, AND COMPUTER READABLE RECORDING MEDIUM RECORDED WITH DELAY DIFFERENCE MEASURING PROGRAM - Each of the plurality of second processing units includes: a counter that counts a count value in synchronization with such a counter included in each remaining second processing unit; a register that holds the count value of the counter; and a control unit that stores the count value, which is counted by the counter when receiving a measurement instruction from the first processing unit, as a receipt-timing count value into the register and notifies the first processing unit of the held receipt-timing count value, and the first processing unit calculates one or more differences between a plurality of the receipt-timing count values notified from the second processing units as a transmitting delay difference from the first processing unit to each of the plurality of second processing units. | 11-28-2013 |
20130326256 | GENERATING MONOTONICALLY INCREASING TOD VALUES IN A MULTIPROCESSOR SYSTEM - Generating monotonically increasing time-of-day values in a multiprocessor system is provided. Synchronization impulses are received by a processor of the multiprocessor system, and an execution of a read instruction of a time-of-day value within a processor of the processors is refused, if the execution of the read instruction of the time-of-day value is requested after a predefined time after a synchronization impulse of the synchronization impulses, and if a trigger signal, indicative of new data received by a related memory system, has been received after the predefined time, wherein the memory system is external to the processor. | 12-05-2013 |
20140013148 | BARRIER SYNCHRONIZATION METHOD, BARRIER SYNCHRONIZATION APPARATUS AND ARITHMETIC PROCESSING UNIT - A plurality of barrier blades, a barrier blade identification information storage unit, and a barrier blade identification information selection unit are provided. The plurality of barrier blades synchronize, using a synchronization address set for a plurality of arithmetic processing units, the plurality of arithmetic processing units. The barrier blade identification information storage unit holds barrier blade identification information to identify the barrier blade corresponding to synchronization address identification information to identify the synchronization address, for each of the plurality of arithmetic processing units. When synchronization address identification information is input, the barrier blade identification information selection unit selects and outputs barrier blade identification information corresponding to the input synchronization address identification information, among barrier blade identification information held by the barrier blade identification information storage unit. | 01-09-2014 |
20140173320 | MAINTAINING SYNCHRONIZATION DURING VERTICAL BLANKING - Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor. | 06-19-2014 |
20140245057 | MULTI-PROCESSOR SYNCHRONIZATION USING TIME BASE COUNTERS - A multi-processor system includes a first processor that includes a first time base counter that outputs a first time base count, a second processor that includes a second time base counter that outputs a second time base count, and a communication bus. The first and second processors exchange the first and second time base counts on the communication bus. The first and second processors determine a skew based upon a difference between the first and second time base counts, and the first and second processors synchronize with each other based upon the skew. | 08-28-2014 |
20140298070 | PROCESSOR TIME SYNCHRONIZATION APPARATUS AND METHOD IN DATA COMMUNICATION SYSTEM WITH MULTIPLE PROCESSORS AND LINE INTERFACES - A processor time synchronization apparatus and method in a data communication system which includes a plurality of processors and line interfaces. The processor time synchronization apparatus includes a first local processor configured to recognize a time difference between an external device and the system based on a time message exchanged with the external device, and synchronize time between the external device and the system, and a second local processor configured to receive time information from the first local processor that has been time-synchronized with the external device, the time information containing the time difference between the external device and the system, and synchronize the first local processor with a system's internal time using the received time information. | 10-02-2014 |
20140365808 | TEMPORARY FREQUENCY ADJUSTMENT OF MOBILE DEVICE PROCESSORS BASED ON TASK MIGRATION - Systems and methods for temporarily adjusting the frequency of processors are disclosed. A computing device may include a plurality of processors that are each configured to execute one or more tasks at a corresponding one of a plurality of frequencies. A scheduling component migrates tasks between the processors to balance a load that is processed by the plurality of processors. A governor component includes a frequency adjustment component to control a frequency of each of the processors and a frequency synchronization component that detects when the scheduling component is migrating one of the tasks from a source processor to a destination processor. The synchronization component increases, based upon a frequency of the source processor, a frequency of the destination processor. | 12-11-2014 |
20140372784 | ENERGY-EFFICIENT PIPELINE CIRCUIT TEMPLATES FOR HIGH-PERFORMANCE ASYNCHRONOUS CIRCUITS - Asynchronous circuits and techniques are described for asynchronous processing without synchronization to a common clock. Two specific energy-efficient pipeline templates for high throughput asynchronous circuits are provided as examples based on single-track handshake protocol. Each pipeline contains multiple stages of logic. The handshake overhead is minimized by eliminating validity and neutrality detection logic gates for all input tokens as well as for all intermediate logic nodes. Both of these templates can pack significant amount of logic within each pipeline block, while still maintaining a fast cycle time. | 12-18-2014 |
20150058655 | INTERFACE CIRCUIT AND SYSTEM - According to one embodiment, there is provided an interface circuit including a plurality of units. Each of the plurality of units includes a clock interface, a data interface, and a selector. The clock interface receives a clock and transfers the clock. The data interface receives data and transfers the data. The selector selects a clock and supplies the selected clock to the data interface such that the data interface transfers the data in synchronization with the selected clock. | 02-26-2015 |
20160253285 | Method And System of Synchronizing Processors To The Same Computational Point | 09-01-2016 |