Class / Patent application number | Description | Number of patent applications / Date published |
713601000 | Inhibiting timing generator or component | 34 |
20080244305 | DELAYED LOCK-STEP CPU COMPARE - The present invention relates to an electronic device comprising a first CPU, a second CPU, a first delay stage and a second delay stage for delaying data propagating on a bus, a CPU compare unit, and wherein the first delay stage is coupled to an output of the first CPU and a first input of the CPU compare unit, an input of the first CPU is coupled to a system input bus, the second delay stage is coupled to the system input bus and to an input of the second CPU, an output of the second CPU (CPU | 10-02-2008 |
20080294930 | IC CARD WITH LOW PRECISION CLOCK - An IC Card may include electronic components to receive a power supply and a main clock signal by a reader device. The power supply may be provided to a subset of the electronic components during a main clock stop status wherein the main clock signal is suspended for avoiding a maximum power consumption threshold. The IC Card may also include a low precision clock included in the subset of electronic components for measuring time in the main clock stop status. | 11-27-2008 |
20080313487 | PROCESSING DEVICE AND CLOCK CONTROL METHOD - A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation. | 12-18-2008 |
20090063890 | MEMORY CONTROLLER WITH MULTIPLE DELAYED TIMING SIGNALS - A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path. | 03-05-2009 |
20090077411 | MEMORY CONTROL CIRCUIT, DELAY TIME CONTROL DEVICE, AND DELAY TIME CONTROL METHOD - A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the plurality of memories, a first variable delay unit delays, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function and a second variable delay unit delays, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time. | 03-19-2009 |
20090083571 | SYSTEM ON CHIP WITH LOW POWER MODE AND METHOD OF DRIVING THE SAME - There are provided a system on chip (SoC) with a low power mode and a method of driving the SoC, the SoC including: a power part supplying a main clock signal and controlling analog and digital power supply at a normal mode and supplying a sub clock signal and turning analog power off at a low power mode; a radio frequency (RF) part generating the main clock signal at the normal mode and stopping operation at the low power mode, under the control of the power part; and a control part operating according to the main clock signal at the normal mode and operating according to the sub clock signal, under to the control of the power part. | 03-26-2009 |
20090164831 | Controlled Default OTP Settings for ASICs - An OTP and Reset Assert Counter and a method for protecting one-time programmable memory settings during read-out from an OTP memory block. The OTP memory block is set at ground and in a reset mode with a clock driven External Reset (RSTB) signal set at ground true active. A Delay Counter is programmed with a time delay to correspond with the time that is inherently needed by the OTP Memory block to complete a read-out process that begins with the External Reset (RSTB) signal being set to HIGH; and an input Clock signal is delayed by the Delay Counter for a duration of the time delay that begins with the External Reset (RSTB) signal being set to HIGH. | 06-25-2009 |
20090172459 | MEMORY INTERFACE - A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium. | 07-02-2009 |
20090249110 | MEMORY CONTROLLER DEVICE, CONTROL METHOD FOR MEMORY CONTROLLER DEVICE AND DATA RECEPTION DEVICE - A memory controller device coupled to a memory device equipment including a plurality of memory devices, includes a memory controller configured to instruct read-out of data in the memory device and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller and excludes a part of a delay time from the read-out instruction until the data read-out of at least one other memory device. | 10-01-2009 |
20090292940 | Memory controller, system including the controller, and memory delay amount control method - A memory controller transmits and receives data to and from a memory. The memory controller includes a delay control section deciding a set value indicative of a determined delay amount in response to a result of a comparison between a test data transmitted to the memory and test data received from the memory, and transmitting the decided set value to the memory, a taking-in section receiving the set value stored in the memory, and a delay adjustment section receiving data from the memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section. | 11-26-2009 |
20090307521 | DDR memory controller - A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. | 12-10-2009 |
20090319821 | Glitch-free clock suspend and resume circuit - Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid. | 12-24-2009 |
20100023796 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 01-28-2010 |
20100083026 | INTER-PROCESSOR COMMUNICATION CHANNEL INCLUDING POWER-DOWN FUNCTIONALITY - Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel. | 04-01-2010 |
20100083027 | SERIAL-CONNECTED MEMORY SYSTEM WITH OUTPUT DELAY ADJUSTMENT - Systems and methods for performing output delay adjustment are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if an output delay adjustment is needed. If so, the master device generates and outputs commands for the slave devices to perform output delay adjustment. The slave devices apply the output delay to the clock signal, but may also apply the delay to other output signals. Each of the slave devices has a circuit for performing output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller. | 04-01-2010 |
20100083028 | SERIAL-CONNECTED MEMORY SYSTEM WITH DUTY CYCLE CORRECTION - Systems and methods for correcting clock duty cycle are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if a duty cycle correction is needed. If so, the master device generates and outputs commands for the slave devices to perform duty cycle adjustment. Each of the slave devices has a circuit for performing duty cycle adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller. | 04-01-2010 |
20100138684 | MEMORY SYSTEM WITH DYNAMIC SUPPLY VOLTAGE SCALING - A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock. | 06-03-2010 |
20100218029 | System and Method for Managing the Power-Performance Range of an Application - Semiconductor device circuits and methods are provided for adjusting core processor performance based on usage metrics. Metric detection and adjustment are performed in digital logic hardware guided by registers providing maximum and minimum frequency settings, without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Power-performance drivers provide applications or the operating system ability to specify maximum and minimum frequency requirements. | 08-26-2010 |
20100229021 | MICROPROCESSOR PERFORMANCE AND POWER OPTIMIZATION THROUGH INDUCTIVE VOLTAGE DROOP MONITORING AND CORRECTION - A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops. | 09-09-2010 |
20110035615 | MEMORY CARD HAVING MEMORY DEVICE AND HOST APPARATUS ACCESSING MEMORY CARD - A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatus in a write timing adjustment mode. The data I/O circuit transmits and receives data to and from the host apparatus in a data transfer mode. In the write timing adjustment mode, the delay element adjusts a phase of the second clock in accordance with the first clock so as to receive the data received in the data transfer mode in response to the first clock. The adjustment value holding circuit holds an adjustment value for the phase of the second clock adjusted. In the data transfer mode, the delay element adjusts a phase of the data in accordance with the adjustment value. | 02-10-2011 |
20110083030 | CACHE MEMORY CONTROL DEVICE, CACHE MEMORY DEVICE, PROCESSOR, AND CONTROLLING METHOD FOR STORAGE DEVICE - A cache memory control device for controlling includes: a clock control unit that controls a clock supply unit among a plurality of clock supply units for supplying clocks to the plurality of cache memories to disable supplying of a clock to cache memories other than a first cache memory when an instruction control unit requests second data stored continuously with first data in the first cache memory. | 04-07-2011 |
20110161720 | IMAGE PROCESSING APPARATUS AND METHOD OF TRANSMITTING REFERENCE CLOCK - An engine unit and a control unit are connected via an interface. A power source supplies electric power to the interface. The engine unit is controlled based on a reference clock generated in the control unit and transmitted to the engine unit via the interface. Only when a voltage output from the power source to the interface is in the operating-voltage range, the clock generator sends the reference clock to the engine unit via the interface. | 06-30-2011 |
20120017109 | PREVENTING CIRCUMVENTION OF FUNCTION DISABLEMENT IN AN INFORMATION HANDLING SYSTEM - For disabling a first function in an information handling system, a dynamic signal is disabled. The first function is inoperable in response to the dynamic signal being disabled. At least a second function in the information handling system is operable irrespective of whether the dynamic signal is disabled. | 01-19-2012 |
20120110367 | Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses - A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions. | 05-03-2012 |
20120110368 | DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA - Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal. | 05-03-2012 |
20130311819 | CONTROLLER - This controller is used in a system in which initiators and targets are connected via distributed buses to control transmission timing of an access request received from the initiators. The controller stores intermittent information including information about an intermittent period in which interference between packets can be restricted and bus operating frequency information indicating a bus operating frequency at which real-time performance is guaranteed for each initiator and which has been generated based on system configuration information and flow configuration information indicating, on a flow basis, a specification required for each initiator to access the target. The controller includes a clock generator; communications circuitry; and transmission interval setting circuitry which sets a time to send transmission permission responsive to a transmission request based on the intermittent period, a time when the transmission request is detected, and a previous transmission time. | 11-21-2013 |
20140068316 | DETERMINATION SUPPORT APPARATUS, DETERMINING APPARATUS, MEMORY CONTROLLER, SYSTEM, AND DETERMINATION METHOD - A determination support apparatus includes a detecting unit that detects a phase difference between a first clock signal and a second clock signal that is identical in frequency to the first clock signal; a control unit that controls delay of at least one among the first clock signal and the second clock signal such that the detected phase difference becomes less than a given amount; and an acquiring unit that acquires values of a given clock signal among the first clock signal and the second clock signal, among which at least one has been subject to delay control by the control unit, wherein the acquiring unit acquires the values of the given clock signal at a timing that is based on a clock signal that is other than the given clock signal and among the first clock signal and the second clock signal. | 03-06-2014 |
20140129870 | Application Memory Preservation for Dynamic Calibration of Memory Interfaces - A calibrating memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface. | 05-08-2014 |
20140173325 | METHOD OF OPERATING SYSTEM ON CHIP AND APPARATUSES INCLUDING THE SAME - A method of operating a system on chip (SoC), an integrated circuit including the SoC, and a system including the same are provided. The method includes: delaying a data strobe signal; obtaining a setup margin and a hold margin by adjusting a delay of the delayed data strobe signal; and determining a data valid window using the obtained setup margin and the obtained hold margin. | 06-19-2014 |
20140325253 | TIMING CONTROL CIRCUIT - A timing control circuit includes: a first variable delay circuit configured to receive first data having a first communication speed, and to give a variable delay to the first data; a first multiplexer configured to receive output of the first variable delay circuit, and to convert into second data having a second communication speed different from the first communication speed in accordance with first control signal; a second variable delay circuit configured to receive third data having the first communication speed, and to give a delay corresponding to the delay of the first variable delay circuit to the third data; a decision circuit configured to compare timings of output of the second variable delay circuit and the first control signal; and a control circuit configured to control the delays of the first variable delay circuit and the second variable delay circuit in accordance with output of the decision circuit. | 10-30-2014 |
20140365810 | POWER SAVING DEVICE AND POWER SAVING METHOD THEREOF - The power saving device and method are provided. The power saving device which applies to a network apparatus includes a Phase-Locked Loop circuit, a computing module and a clock-selecting register, the Phase-Locked Loop circuit is configured to receive a reference clock frequency and generate a clock frequency-increasing signal according to the reference clock frequency; the computing unit is configured to calculate a setting parameter and the clock-selecting register is configured to generate an operating clock signal according to the clock frequency-increasing signal and setting parameter and send the operating clock signal to the network apparatus, wherein the network apparatus adjusts the clock frequency rate according to the operating clock signal. | 12-11-2014 |
20140372787 | METHODS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY SWEEP SAMPLING WITH AUTOMATIC JITTER AVOIDANCE - A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter. | 12-18-2014 |
20150052380 | METASTABILITY PREDICTION AND AVOIDANCE IN MEMORY ARBITRATION CIRCUITRY - An integrated circuit with hazard prediction and prevention circuitry is provided. The hazard prediction circuitry may predict a future hazard condition between two periodic signals, and the hazard prevention circuitry may selectively delay at least one of the two periodic signals to avoid the predicted hazard condition. Single-port memory cells may provide multiport memory functionality using an arbitration circuit that includes the hazard prediction and prevention circuitry and receives memory access requests from at least two request generators. The arbitration circuit may operate in synchronous mode and perform port selection based on a predetermined logic table. The arbitration circuit may also operate in asynchronous mode and execute a memory access request as soon as it is received by the arbitration circuit. Metastability caused by receiving memory access requests at the same time from at least two request generators may be avoided with the hazard prediction and prevention circuitry. | 02-19-2015 |
20150121120 | DATA TRANSMISSION APPARATUS HAVING FREQUENCY SYNTHESIZER WITH INTEGER DIVISION FACTOR, CORRESPONDING METHOD, AND DATA TRANSMISSION SYSTEM - A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor. | 04-30-2015 |