Class / Patent application number | Description | Number of patent applications / Date published |
324762030 | Integrated circuit die | 70 |
20110037494 | Method for Wafer-Level Testing of Integrated Circuits - A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal. | 02-17-2011 |
20110102010 | METHOD AND APPARATUS FOR RECONFIGURABLE AT-SPEED TEST CLOCK GENERATOR - A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured. | 05-05-2011 |
20110102011 | METHOD AND DEVICE FOR TESTING TSVS IN A 3D CHIP STACK - A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry. | 05-05-2011 |
20110140730 | DETECTION CIRCUITRY FOR DETECTING BONDING CONDITIONS ON BOND PADS - The present invention relates to a detection circuitry for detecting bonding conditions on segmented bond pads of a semiconductor device, the bonding conditions representing good or bad contacts on the bond pads. The detection circuitry comprises a segmented bond pad ( | 06-16-2011 |
20110234253 | INTEGRATED CIRCUIT DIE TESTING APPARATUS AND METHODS - A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines. When on the wafer, the dies in a pipeline are interconnected with pipeline die test interconnection paths that provide pipeline test information interconnection among the plurality of dies in the pipeline. | 09-29-2011 |
20110267093 | TESTABLE INTEGRATED CIRCUIT, SYSTEM IN PACKAGE AND TEST INSTRUCTION SET - An integrated circuit die includes a plurality of interconnects including a first test data input, a second test data input and a test dat | 11-03-2011 |
20110285419 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference dock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units. | 11-24-2011 |
20120019280 | INTEGRATED CIRCUIT HAVING ELECTRICALLY ISOLATABLE TEST CIRCUITRY - Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power. | 01-26-2012 |
20120025863 | SOLDER JOINT INSPECTION - An integrated circuit includes an electronic circuit in a housing and a first contacting device for soldering the circuit to a corresponding second contacting device of a circuit board. The first and second contacting devices are each divided into a first section and a second section, the sections of one of the contacting devices being fixedly electrically connected to each other, and the sections of the other contacting device being selectively connectable to a device for resistance determination. | 02-02-2012 |
20120056639 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprising: a circuit block formed on a semiconductor substrate; an electrically conductive pattern formed in an upper layer of a portion to be protected of the circuit block; an oscillation circuit connected to the electrically conductive pattern, and configured to oscillate at an oscillation frequency determined by a circuit constant of the electrically conductive pattern; and a detection circuit configured to determine whether a preset range includes the oscillation frequency of the oscillation circuit is provided. | 03-08-2012 |
20120056640 | COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR TESTER INTERFACE - A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry. | 03-08-2012 |
20120068730 | System and Method for Evaluating the Electromagnetic Compatibility of Integrated Circuits in an In-Situ Environment - A device is configured to evaluate electromagnetic characteristics of an integrated circuit. The device includes a fluid chamber, a first impeller, a second impeller, and a radio frequency measurement antenna. The fluid chamber is configured to receive the integrated circuit and to cool the integrated circuit. The first impeller is disposed within the fluid chamber and configured to distribute a first electromagnetic field produced by the integrated circuit within the fluid chamber along a first axis. The second impeller is within the fluid chamber and configured to distribute the first electromagnetic field produced by the integrated circuit within the fluid chamber along a second axis. The radio frequency measurement antenna is disposed proximate the fluid chamber and configured to measure an electric field and a magnetic field of the first electromagnetic field. | 03-22-2012 |
20120092038 | INSPECTION DEVICE AND INSPECTION METHOD - The present invention provides semiconductor integrated circuit, inspection device and inspection method for inspecting whether inspection target is functioning normally regardless to start-up period of a power supply voltage. The inspection device includes a reset control circuit and a tester. When a reset signal is inputted from a power-on reset circuit to a first terminal, the reset control circuit starts output of a reset execution signal having the same level as the reset signal. When a trigger signal is inputted from a control device to the second input terminal, the reset control circuit finishes the output of the reset execution signal and starts output of a release execution signal that has the same level as a reset release signal from the output terminal. The tester determines whether the power-on reset circuit is functioning normally by determining whether signals outputted from the reset control circuit are at predetermined levels. | 04-19-2012 |
20120112784 | DIFFERENTIAL SIGNAL TRANSMISSION LINE, IC PACKAGE, AND METHOD FOR TESTING SAID DIFFERENTIAL SIGNAL TRANSMISSION LINE AND IC PACKAGE - An IC package includes an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, a first signal terminal for transmitting the signal having positive polarity, a second signal terminal for transmitting the signal having negative polarity, and a third terminal arranged between the first signal terminal and the second signal terminal. The first and second terminals are electrically connected to the integrated circuit, and the third terminal is not electrically connected to the integrated circuit. | 05-10-2012 |
20120126846 | METHOD FOR TESTING A PARTIALLY ASSEMBLED MULTI-DIE DEVICE, INTEGRATED CIRCUIT DIE AND MULTI-DIE DEVICE - The present invention discloses a method of testing a partially assembled multi-die device ( | 05-24-2012 |
20120139575 | Method and apparatus for multi-planar edge-extended wafer translator - An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs. | 06-07-2012 |
20120161808 | Methods and Systems to Measure a Signal on an Integrated Circuit Die - Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit. | 06-28-2012 |
20120249178 | MONITORING METHOD FOR THREE-DIMENSIONAL INTERGRATED CIRCUIT (3D IC) AND APPARATUS USING THE SAME - A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same. | 10-04-2012 |
20120280708 | INTEGRATED CIRCUIT CHIP AND TESTING METHOD THEREOF - An integrated circuit chip is provided. The integrated circuit chip includes a pad, a first resistor, a second resistor, a first switch, a second switch and a controller. The first resistor and the first switch are serially connected between the pad and a first reference voltage terminal. The second resistor and the second switch are serially connected between the pad and a second reference voltage terminal. The controller selectively turns on and off the first and second switches according to an error determining mechanism. The error determining mechanism determines whether an error condition associated with the pad is present. | 11-08-2012 |
20120293197 | On-Chip Leakage Current Modeling and Measurement Circuit - At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit. | 11-22-2012 |
20130043897 | TESTING STACKED DIE - An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die. | 02-21-2013 |
20130049793 | ANALYZING EM PERFORMANCE DURING IC MANUFACTURING - A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure. | 02-28-2013 |
20130076387 | SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE, AND METHOD OF MEASURING THE SAME - In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected. | 03-28-2013 |
20130093455 | TSV TESTING METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for testing TSVs in a single die or TSV connections in a stack of die. | 04-18-2013 |
20130099816 | ACTIVE MATRIX SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR TESTING THE ACTIVE MATRIX SUBSTRATE OR THE DISPLAY DEVICE - An active matrix substrate includes a plurality of bus lines ( | 04-25-2013 |
20130135004 | THREE-DIMENSIONAL INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME - Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested. | 05-30-2013 |
20130147510 | MONITORING TESTKEY USED IN SEMICONDUCTOR FABRICATION - A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer. | 06-13-2013 |
20130169308 | LCR TEST CIRCUIT STRUCTURE FOR DETECTING METAL GATE DEFECT CONDITIONS - A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode. | 07-04-2013 |
20130193997 | SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER - System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit. | 08-01-2013 |
20130207686 | DEFECT DETECTION IN INTEGRATED CIRCUIT DEVICES - In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data. | 08-15-2013 |
20130234749 | APPARATUS FOR TESTING IMMUNITY OF ELECTRONIC EQUIPMENT AGAINST FLUCTUATING ELECTRIC FIELD AND METHOD FOR TESTING IMMUNITY OF ELECTRONIC EQUIPMENT AGAINST FLUCTUATING ELECTRIC FIELD - In a testing apparatus, an electronic equipment to be an equipment under test; EUT is exposed to an electric field by unit of an emission electrode, and an intensity of the electric field applied to the electronic equipment during a test is fluctuated by electric field fluctuating unit. Operating characteristics of the electronic equipment are tested by generating induction charging inside the electronic equipment by the fluctuation electric field during the test. As a result, it becomes possible to test malfunction caused by a discharge phenomenon generated inside the electronic equipment, which cannot be tested with a conventional ESD testing apparatus. | 09-12-2013 |
20130314120 | WAFER LEVEL PACKAGE RESISTANCE MONITOR SCHEME - An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold. | 11-28-2013 |
20140002128 | Die Attach Pick Error Detection | 01-02-2014 |
20140015562 | PERFORMANCE CHARACTERISTIC MONITORING CIRCUIT AND METHOD - A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay. | 01-16-2014 |
20140062522 | Space Transformation Methods - A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package. | 03-06-2014 |
20140070838 | CHARGE SHARING TESTING OF THROUGH-BODY-VIAS - In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described. | 03-13-2014 |
20140118021 | SYSTEM AND METHOD FOR SELECTING A DERATING FACTOR TO BALANCE USE OF COMPONENTS HAVING DISPARATE ELECTRICAL CHARACTERISTICS - A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process. | 05-01-2014 |
20140145748 | Method and Device for Controlling the Latency of Electronic Circuits - A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open. | 05-29-2014 |
20140167808 | INTERCONNECT SOLDER BUMPS FOR DIE TESTING - A semiconductor chip may include a die having one or more circuits. The semiconductor chip may include a plurality of die bumps, each having a first geometry, a first vertical profile, and a first volume. The die bumps may be coupled to the die and in electrical communication with the one or more circuits. The semiconductor device may include a plurality of test bumps each having a second geometry, a second vertical profile, and the first volume. The test bumps may be coupled to the die and in electrical communication with the one or more circuits. The first geometry and the second geometry may be adapted for the plurality of test bumps to make connection with a wafer probe to the test bumps without making a connection to any of the die bumps during a die test. | 06-19-2014 |
20140184263 | SENSOR SYSTEM AND COVER DEVICE FOR A SENSOR SYSTEM - A sensor system includes a sensor device and a cover device. The sensor device includes an external surface on which at least one electrical test contact is arranged. The cover device includes at least partially an electrically insulating material and is mechanically connected to the sensor device. The cover device is configured to cover the at least one electrical test contact of the sensor device so as to prevent contact from being made to the at least one electrical test contact from outside the sensor system. | 07-03-2014 |
20140191779 | CROSSTALK SUPPRESSION IN WIRELESS TESTING OF SEMICONDUCTOR DEVICES - An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die. | 07-10-2014 |
20140203837 | OPTICAL TRANSMISSION OF TEST DATA FOR TESTING INTEGRATED CIRCUITS - In accordance with one aspect of the present description, integrated circuits may tested by optically transmitting test data over a light beam in addition to or instead of transmitting the test data using mechanical probes. Optically transmitted test data is detected by a photon detector on board the die to be tested. Individual circuit portions of the die may be tested using test data associated with each individual circuit portion. Other aspects are described. | 07-24-2014 |
20140306732 | DETECTION OF DEFECTIVE ELECTRICAL CONNECTIONS - An embodiment relates to an integrated circuit comprising at least two electrical connections and at least one coil arranged adjacent to at least one of the electrical connection, wherein the at least one coil each comprises at least one winding and wherein the at least one coil is arranged on or in the integrated circuit. | 10-16-2014 |
20140320160 | INTEGRATED CIRCUIT FOR SWITCHING LOADS, CIRCUIT ARRANGEMENT COMPRISING AN INTEGRATED CIRCUIT AND A CONNECTED LOAD, AND METHOD FOR OPERATING SUCH A CIRCUIT ARRANGEMENT - An integrated circuit has a controllable switching element, the load path of which is arranged between an output of the integrated circuit and a supply potential. A test unit is connected to the connections of the switching element in order to carry out tests. A control unit is connected to the test unit via at least one control line. The sequence of tests is carried out dependent on signals on the control line(s). A memory is connected to the control unit the content and the type of which determines the time of the tests. The memory is connected to an input of the integrated circuit in order to enter the content. | 10-30-2014 |
20140327465 | STRUCTURES AND METHODS FOR TESTING INTEGRATED CIRCUITS AND VIA CHAINS THEREIN - An exemplary structure for testing an integrated circuit includes a semiconductor substrate and first and second via chains disposed over the substrate. The via chains include a substantially same sequence of segments interconnected at N via regions by a respective first and second via arrangement. The first via arrangement includes M | 11-06-2014 |
20140333342 | ELECTRIC CURRENT APPLICATION METHOD AND ELECTRIC CURRENT APPLYING DEVICE - An electric current application method for applying electric current to a power semiconductor | 11-13-2014 |
20140375350 | TESTING OF INTEGRATED CIRCUITS WITH EXTERNAL CLEARANCE REQUIREMENTS - A method of testing an integrated circuit clearance distance device (“ICCDD”) having a predetermined clearance distance in air requirement and a predetermined isolation voltage limit including calculating a value of the breakdown voltage at the predetermined clearance distance for at least one gas; and selecting a gas in which the ICCDD has a breakdown voltage that is less than the predetermined isolation voltage. | 12-25-2014 |
20150008954 | MONOLITHIC INTEGRATED CIRCUIT DIE HAVING MODULAR DIE REGIONS STITCHED TOGETHER - An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines. | 01-08-2015 |
20150035556 | Crack Sensors for Semiconductor Devices - Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure. | 02-05-2015 |
20150042373 | SEMICONDUCTOR DEVICE - A semiconductor device capable of simplifying wiring work is provided. A semiconductor device includes a semiconductor element (insulated gate bipolar transistor IGBT) provided with an emitter main electrode and an emitter sense electrode, an integrated circuit having a detection terminal and a mold resin body that seals the semiconductor element and the integrated circuit, and a lead. The lead is provided with an inner lead part sealed in the mold resin body and electrically connected to the emitter sense electrode, an inner lead part sealed in the mold resin body and electrically connected to the emitter main electrode, and an outer lead part connected to the lead part on one side, connected to the inner lead part on the other side and exposed outside the mold resin body. | 02-12-2015 |
20150042374 | Leakage Current Detection Method and Apparatus - A leakage current detection method and apparatus are provided. The method is applied to leakage current detection for a board-mounted component on a printed circuit board assembly (PCBA) board, and includes: providing a fixed voltage for a leakage current input end of a board-mounted component under detection, and connecting a leakage current output end to an inverting input end of an operational amplifier of a resistance testing module, where the resistance testing module includes the operational amplifier and a reference resistor that is connected between the inverting input end of the operational amplifier and the leakage current output end; detecting an output voltage of the resistance testing module; and calculating, based on Ohm's law and according to the output voltage and the reference resistor, a leakage current flowing through the board-mounted component under detection. | 02-12-2015 |
20150084666 | MOTHER SUBSTRATE, ARRAY TEST METHOD THEREOF AND DISPLAY SUBSTRATE - A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part. | 03-26-2015 |
20150084667 | METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE - A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing. | 03-26-2015 |
20150097593 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 04-09-2015 |
20150115993 | STRUCTURE AND METHOD FOR TESTING STACKED CMOS STRUCTURE - A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus. | 04-30-2015 |
20150123698 | TEST CIRCUIT AND METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal. | 05-07-2015 |
20150123699 | SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs - A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance. | 05-07-2015 |
20150301107 | AGING DETECTION CIRCUIT AND METHOD THEREOF - An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit. | 10-22-2015 |
20150346274 | INPUT/OUTPUT CELL, INTEGRATED CIRCUIT DEVICE AND METHODS OF PROVIDING ON-CHIP TEST FUNCTIONALITY - An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages. | 12-03-2015 |
20150369860 | ARRANGEMENT FOR TESTING INTEGRATED CIRCUITS - An arrangement for testing integrated circuits includes an integrated test circuit and a cluster which has at least one integrated circuit and a second integrated circuit. The first integrated circuit is provided in a first component region of a wafer, and the second integrated circuit in a second component region. The first component region and the second component region are spaced a distance apart by a scribe line of the wafer. The integrated test circuit is connected to the first integrated circuit via a first test line section, and the second integrated circuit is connected to the first test line section via a first connecting line that has a first well in the semiconductor material, the first well extending continuously in the wafer from the first component region over the scribe line to the second component region, the first well being electrically insulated from a substrate of the wafer. | 12-24-2015 |
20160033576 | HIGH SENSITIVITY DIGITAL VOLTAGE DROOP MONITOR FOR INTEGRATED CIRCUITS - Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage. | 02-04-2016 |
20160054382 | METHOD FOR CHECKING RESULT OF CHIP PROBING TEST AND CHIP THEREOF - A chip having information of a result of a chip probing test and a method for checking the results of the chip probing test are disclosed. The chip includes a chip substrate and a record module located on the chip substrate. The record module is configured to record a status code indicating whether the chip passes the chip probing test. The method includes following steps: executing the chip probing test for the chip; and recording the status code in the record module of the chip, the status code indicating whether the chip passes the chip probing test. | 02-25-2016 |
20160091532 | FLEXIBLE FILM ELECTRICAL-TEST SUBSTRATES WITH CONDUCTIVE COUPLING POST(S) FOR INTEGRATED CIRCUIT (IC) BUMP(S) ELECTRICAL TESTING, AND RELATED METHODS AND TESTING APPARATUSES - Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (μm) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC. | 03-31-2016 |
20160116526 | METHOD AND APPARATUS FOR QUANTIFYING DEFECTS DUE TO THROUGH SILICON VIAs IN INTEGRATED CIRCUITS - A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system. | 04-28-2016 |
20160131711 | MIXING OF LOW SPEED AND HIGH SPEED CLOCKS TO IMPROVE TEST PRECISION OF A DIGITAL INTEGRATED CIRCUIT - Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal. | 05-12-2016 |
20160146883 | DEVICE AND METHOD OF DETECTING SIGNAL DELAY - The present disclosure discloses a device for, and a method of, detecting a signal delay. The method of detecting a signal delay includes inputting a first signal and a second signal to a logic circuit to obtain an output signal; measuring an average voltage of the output signal; and determining a delay time of the second signal relative to the first signal based on a difference between the average voltage of the output signal and a reference voltage. The device for detecting a signal delay includes a clock output of a clock generator connected to a first logic input of a logic circuit and to a connection area for receiving a circuit to be tested. A second logic input of the logic circuit is also connected to the connection area. The voltage measurement device is connected to a logic output of the logic circuit. | 05-26-2016 |
20160154055 | ON-DIE SYSTEM FOR MONITORING AND PREDICTING PERFORMANCE | 06-02-2016 |
20160163609 | METHODS AND APPARATUS FOR TESTING AUXILIARY COMPONENTS IN A MULTICHIP PACKAGE - Ways for testing a multichip package while reducing the required test pin count are provided. The multichip package may include a main die coupled to multiple daughter components. During testing, one of the daughter components may be selected for testing while other daughter components sit idle. The daughter components may receive test signals via a shared path. Dedicated select pins may be used to activate the selected daughter component while placing the unselected components in tristate mode. The selection of daughter components during testing can also be controlled directly using the main die. If desired, general-purpose input-output (GPIO) pins of the main die may be borrowed from the main die to convey the test signals to the selected daughter component during testing. If desired, multiplexing circuitry may also be used to selectively route signals to the daughter components during testing. | 06-09-2016 |
20160178694 | ELECTRICAL CIRCUIT ODOMETER SENSOR ARRAY | 06-23-2016 |
20190146030 | INTEGRATED CIRCUIT AND TEST METHOD FOR INTEGRATED CIRCUIT | 05-16-2019 |