Entries |
Document | Title | Date |
20100275175 | Method for Time-Evolving Rectilinear Contours Representing Photo Masks - Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to rectilinear patterns), robustness against process variations, as well as restrictions imposed relating to practical and economic manufacturability of photomasks. | 10-28-2010 |
20100293517 | Method, system, and computer product for forming a graph structure that describes free and occupied areas - A graph structure is generated to describe an area with a free area and an occupied area. In this case a topological graph structure for the free area is determined. A point of the topological graph structure is selected and for this a nearest adjacent occupied area point is determined. For this nearest adjacent occupied area point location information is determined. The graph structure is formed from at least the selected point of the topological graph structure and from the associated location information of the nearest adjacent occupied area point. | 11-18-2010 |
20110047518 | PATTERN DETERMINING METHOD - According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area. | 02-24-2011 |
20110061031 | METHOD FOR PRODUCING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT WITH RADIO FREQUENCY DEVICES - A method for producing a layout of a device in an integrated circuit before actually fabricated is provided. The method includes inputting at least one fixed parameter for the device for fabrication. And then, a first part of a set of variable parameters of a layout of the device is input. The complete set of the variable parameters is generated. It is checked whether or not the layout with the parameters is satisfying a requirement, wherein an end step is reached if the layout is accepted by the requirement, and a new part of the set of variable parameters as the first part being looping in the foregoing steps if the layout is not accepted by the requirement. | 03-10-2011 |
20110088004 | TOOL IDENTIFYING METHOD AND APPARATUS - A method includes generating A | 04-14-2011 |
20110107278 | Method for Improving Yield Rate Using Redundant Wire Insertion - A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero. | 05-05-2011 |
20110239168 | INTELLIGENT PATTERN SIGNATURE BASED ON LITHOGRAPHY EFFECTS - The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective. | 09-29-2011 |
20120047471 | DYNAMIC PROVISIONAL DECOMPOSITION OF LITHOGRAPHIC PATTERNS HAVING DIFFERENT INTERACTION RANGES - A method for obtaining mask and source patterns for printing integrated circuit patterns includes providing initial representations of a plurality of mask and source patterns. The method identifies long-range and short-range factors in the representations of the plurality of mask and source patterns, and provides a plurality of clips including a specified number of mask patterns. Short-range factors having overlapping ranges for each of the clips are specified. The method includes determining an initial processing priority for the plurality of clips, and determining a patterning relationship between integrated circuit patterns and the mask and source patterns. A primary objective is determined which expresses the printability of the integrated circuit patterns in terms of the patterning relationship. The method defines and iteratively solves a master problem employing the primary objective to generate values for the long-range factors, and solves subproblems employing a second objective for generating values for the short-range factors. | 02-23-2012 |
20120089953 | MASK LAYOUT FORMATION - A method for mask layout formation including forming a plurality of phase shapes on either side of a critical feature of a design layout of an integrated circuit chip having a plurality of critical features, wherein each phase shape has an edge; identifying a plurality of transition edges from the edges, wherein each transition edge is parallel to a critical feature; identifying a transition space defined by one of a group including two transition edges, wherein the space is external to all phase shapes, and one transition edge, wherein the space is external to all phase shapes; forming a transition polygon by closing each transition space with at least one closing edge, wherein each closing edge is perpendicular to the plurality of transition edges; transforming each transition polygon into a printing assist feature; and forming a first mask layout or a second mask layout from the printing assist features and the critical features. | 04-12-2012 |
20120167019 | MASK REVISION RECORDING CIRCUIT FOR A MEMORY CIRCUIT - A mask revision recording circuit for a memory circuit includes a mask recording module and a reading unit. The mask recording module includes a plurality of mask recording units, and a layout of each mask recording unit corresponds to all masks of a layout of the memory circuit. The reading unit is coupled to the mask recording module for reading information of the mask recording module corresponding to a mask revision of the memory circuit according to a clock and an enable signal. | 06-28-2012 |
20120198393 | LITHOGRAPHY VERIFICATION APPARATUS AND LITHOGRAPHY SIMULATION PROGRAM - The present invention provides a lithography verification apparatus which executes high-precision lithography verification in consideration of the effects of individual errors integrated. Various information (simulation result, error standard, etc.) are input. A variation distribution value is calculated. The variation distribution value and a variation distribution error standard are compared to determine whether the variation distribution value is smaller than the error standard. The variation distribution error standard is a standard for a value or the like related to a standard deviation or the like for a dimensional displacement. When it is determined that the variation distribution value is smaller than the error standard, an error is determined not to exist, and the processing is ended. When it is determined that the variation distribution value is not smaller than the error standard, an error is determined to exist, and an error list and a variation distribution value are outputted. | 08-02-2012 |
20120227013 | SYSTEMS AND METHODS FOR IMPLEMENTING AND MANUFACTURING RETICLES FOR USE IN PHOTOLITHOGRAPHY TOOLS - Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments include obtaining qualitative data from within the pattern area of a reticle indicative of the physical characteristics of the pattern area. Additional embodiments include obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. In further embodiments qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. Several embodiments provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements. This is expected to provide accurate data for correcting the photolithography tool to compensate for variances in the pattern area, and to increase throughput because the photolithography tool is not used to measure the reticle. | 09-06-2012 |
20120233574 | NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, DECISION METHOD AND COMPUTER - The present invention provides a non-transitory computer-readable storage medium storing a program that causes a computer to decide an exposure condition in an exposure apparatus, the program causing the computer to execute a step of selecting an evaluation item of interest from a plurality of evaluation items to be used to evaluate an image formed on an image plane of a projection optical system in correspondence with the exposure condition, a step of selecting, as an auxiliary evaluation item, an evaluation item which is different from the evaluation item of interest and changes a value in the same direction as that of a change in a value of the evaluation item of interest upon changing parameter values included in the exposure condition, and a step of setting an evaluation function including the evaluation item of interest and the auxiliary evaluation item as values. | 09-13-2012 |
20120260221 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-11-2012 |
20120311510 | Spatial Correlation-Based Estimation of Yield of Integrated Circuits - A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows. | 12-06-2012 |
20130014065 | Methods and Systems for Pattern Design with Tailored Response to Wavefront Aberration - The present invention relates to methods and systems for designing gauge patterns that are extremely sensitive to parameter variation, and thus robust against random and repetitive measurement errors in calibration of a lithographic process utilized to image a target design having a plurality of features. The method may include identifying most sensitive line width/pitch combination with optimal assist feature placement which leads to most sensitive CD (or other lithography response parameter) changes against lithography process parameter variations, such as wavefront aberration parameter variation. The method may also include designing gauges which have more than one test patterns, such that a combined response of the gauge can be tailored to generate a certain response to wavefront-related or other lithographic process parameters. The sensitivity against parameter variation leads to robust performance against random measurement error and/or any other measurement error. | 01-10-2013 |
20130086535 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system. | 04-04-2013 |
20130111416 | DESIGN DATA OPTIMIZATION METHOD, STORAGE MEDIUM INCLUDING PROGRAM FOR DESIGN DATA OPTIMIZATION METHOD AND PHOTOMASK MANUFACTURING METHOD | 05-02-2013 |
20130111417 | Database-Driven Cell-to-Cell Reticle Inspection | 05-02-2013 |
20130132913 | RECOGNITION OF TEMPLATE PATTERNS WITH MASK INFORMATION - Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons. | 05-23-2013 |
20130139116 | LITHOGRAPHICALLY ENHANCED EDGE DETERMINATION - During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path. | 05-30-2013 |
20130152025 | METHOD AND SYSTEM FOR COMPUTING FOURIER SERIES COEFFICIENTS FOR MASK LAYOUTS USING FFT - A method and system for computing Fourier coefficients for a Fourier representation of a mask transmission function for a lithography mask. The method includes: sampling a polygon of a mask pattern of the lithography mask to obtain an indicator function which defines the polygon, performing a Fourier Transform on the indicator function to obtain preliminary Fourier coefficients, and scaling the Fourier coefficients for the Fourier representation of the mask transmission function, where at least one of the steps is carried out using a computer device. | 06-13-2013 |
20130179846 | PHOTOMASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value. | 07-11-2013 |
20130185681 | CORRECTION FOR FLARE EFFECTS IN LITHOGRAPHY SYSTEM - A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields. | 07-18-2013 |
20130198696 | METHODS FOR QUANTITATIVELY EVALUATING THE QUALITY OF DOUBLE PATTERNING TECHNOLOGY-COMPLIANT LAYOUTS - A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate. | 08-01-2013 |
20130198697 | RETICLE DEFECT CORRECTION BY SECOND EXPOSURE - Correction of reticle defects, including reticle weak spots or shortcomings, is accomplished with a second exposure. Embodiments include obtaining a reticle with a pattern corresponding to a wafer pattern design, exposing a wafer with the reticle, modifying the design, designating variations between the design and the modified design as reticle defects, and exposing the wafer with correction patterns containing structure corresponding to the modified design at defect positions. Other embodiments include modifying, eliminating, and/or shifting the pattern near a reticle blank defect position, and exposing a wafer with the reticle and with a correction pattern containing structure corresponding to the design at a defect position; modifying a patterned reticle surface layer near a defect forming an expanded defect, exposing a wafer with the modified reticle and with an expanded defect correction pattern; and exposing a wafer with a reticle and with a correction pattern larger than a detected reticle defect. | 08-01-2013 |
20130246980 | EFFICIENT DECOMPOSITION OF LAYOUTS - Described herein are methods and systems for efficiently preparing a wafer layout for processing into a photomask. Portions of layouts containing semiconductor features and designs that are frequently used can be stored in a database. These portions can be post-decomposition, with all treatment and error checking already performed upon them. When a wafer layout is received for processing into a photomask, the processing and decomposition time can be reduced by analyzing the layout, and replacing sections of the layout with the portions from the database that have already been decomposed and processed. As these sections no longer need to be decomposed, error checked, and treated, the processing time is greatly reduced, and photomasks can be made quicker and more efficiently. | 09-19-2013 |
20130298087 | DOSE-DATA GENERATING APPARATUS - According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included. | 11-07-2013 |
20140007023 | METHOD FOR PROXIMITY CORRECTION | 01-02-2014 |
20140075395 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND STORAGE MEDIUM - According to an embodiment, in a semiconductor integrated circuit design apparatus for assigning a plurality of wires placed at one wiring layer to a plurality of photomasks, an operation-timing-critical wire is identified from among the plurality of wires placed at a same wiring layer, an adjacent wire which is placed adjacent to the critical wire is extracted, the critical wire and the adjacent wire are laid out such that an interval between the critical wire and the adjacent wire is at least a predetermined distance, and layout patterns of the critical wire and the adjacent wire is assigned to the same photomask. | 03-13-2014 |
20140075396 | METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY - A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error. | 03-13-2014 |
20140129996 | METHOD AND SYSTEM FOR DIMENSIONAL UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask process correction or forming a pattern on a resist-coated reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle, and where the pattern exposure information is modified to lower the calculated sensitivity. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a resist-coated reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle. | 05-08-2014 |
20140129997 | METHOD AND SYSTEM FOR DIMENSIONAL UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern. | 05-08-2014 |
20140157212 | Distinguishable IC Patterns with Encoded Information - A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used. | 06-05-2014 |
20140195992 | Determining a Position of Inspection System Output in Design Data Space - Systems and methods for determining a position of output of an inspection system in design data space are provided. One method includes merging more than one feature in design data for a wafer into a single feature that has a periphery that encompasses all of the features that are merged. The method also includes storing information for the single feature without the design data for the features that are merged. The information includes a position of the single feature in design data space. The method further includes aligning output of an inspection system for the wafer to the information for the single feature such that positions of the output in the design data space can be determined based on the design data space position of the single feature. | 07-10-2014 |
20140195993 | THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION - A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image. | 07-10-2014 |
20140237434 | PHOTOLITHOGRAPHY MASK DESIGN SIMPLIFICATION - A photolithography mask design in simplified. In one example, a target mask design is optimized for a photolithography mask. Medial axes of the design and assist features on the optimized mask are identified. These are simplified to lines. Lines that are distant from a respective design feature are pruned. The remaining lines are simplified and then thickened to form assist features. | 08-21-2014 |
20140245237 | HYBRID EVOLUTIONARY ALGORITHM FOR TRIPLE-PATTERNING - According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using a hybrid evolutionary algorithm to form a colored graph. | 08-28-2014 |
20140282286 | ETCH FAILURE PREDICTION BASED ON WAFER RESIST TOP LOSS - An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features. | 09-18-2014 |
20140282287 | REUSABLE CUT MASK FOR MULTIPLE LAYERS - The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication. | 09-18-2014 |
20140282288 | DESIGN-FOR-MANUFACTURING - DESIGN-ENABLED-MANUFACTURING (DFM-DEM) PROACTIVE INTEGRATED MANUFACTURING FLOW - System and methods for design-for-manufacturing and design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flow are presented. A method includes receiving design data related to layout of an integrated circuit (IC); extracting information from the design data; and performing analysis on the extracted information. The method also enables DFM-DEM aware manufacturing applications using information stored in a knowledge database. The method further updates the knowledge database with new information learned from at least the extracted information and the analysis. | 09-18-2014 |
20140282289 | CELL BOUNDARIES FOR SELF ALIGNED MULTIPLE PATTERNING ABUTMENTS - A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern. | 09-18-2014 |
20140282290 | SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION USING SHOT OPTIMIZATION - A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape. | 09-18-2014 |
20140351772 | METHOD AND APPARATUS FOR MODEL BASED FLEXIBLE MRC - Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement. | 11-27-2014 |
20140380255 | PRINTING PROCESS CALIBRATION AND CORRECTION - Various embodiments include approaches for calibrating a model for a lithographic printing process. Some embodiments include a computer-implemented method for calibrating a model for a lithographic printing process. Some approaches include: identifying parameters for a model of the lithographic printing process; assembling a population of design content including potentially printable features that can be printed by the lithographic printing process; preparing at least one matrix expressing a similarity between the potentially printable features in terms of the parameters for the model; determining a manifold of smaller dimensionality than the parameters for the model which exhibit maximum variation in similarity within the at least one matrix; and selecting a sample dataset of the potentially printable features from the manifold. | 12-25-2014 |
20150040077 | MULTI-PATTERNING MASK DECOMPOSITION METHOD AND SYSTEM - A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost. | 02-05-2015 |
20150074618 | DESIGN LAYOUT CORRECTING METHOD, RECORDING MEDIUM AND DESIGN LAYOUT CORRECTING APPARATUS - In a design layout correcting method of an embodiment, a design layout of a circuit pattern is divided to a first mask pattern and a second mask pattern. The mask pattern of the pattern defect area of the first or second mask pattern is set as the correcting target pattern. A correcting target region and a verifying region are set within the first or second mask pattern. The correcting target pattern is corrected within the correcting target region, and the first and second mask patterns are verified within the verifying region. | 03-12-2015 |
20150106771 | METHOD OF LITHOGRAPHIC PROCESS EVALUATION - Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model. | 04-16-2015 |
20150310160 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING HIGH DENSITY REGISTRATION MAPS FOR MASKS - A method and system for generating high density registration maps for masks is disclosed. A data preparation module generates a plurality of anchor points of the mask. Additionally, the data preparation module generates a plurality of sample points. Weights are generated as well in the data preparation module and the weights are used later on in the data fusion module. The positions of anchor points are measured with a registration tool in a mask coordinate system according to a generated recipe. The positions of sample points are determined with an inspection tool in a mask coordinate system according to a generated recipe. The measured positions of the anchor points and the measured positions of the sample points are passed to a data fusion module where a registration map is determined. | 10-29-2015 |
20150363540 | LAYOUT MODIFICATION METHOD AND SYSTEM - A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout. | 12-17-2015 |
20150363542 | Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication - Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures. | 12-17-2015 |
20160042118 | SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION WITH SHOT OPTIMIZATION - A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape. | 02-11-2016 |
20160078166 | PROCESS ARTEFACT COMPENSATION UPON TRANSFER OF A MASK LAYOUT ONTO A MASK SUBSTRATE - The present disclosure relates to beam writing technologies. In detail, a technique for compensating process artifacts of a mask layout transfer process is described. A method implementation of that technique comprises modeling, for a target mask layout, an intensity profile resulting from exposing a resist on a masking layer by beam writing. Further, a contour and a profile of the exposed resist after development are modeled from the intensity profile. Then, a geometry of the masking layer after etching is modeled from the resist contour and the resist profile. For any deviation of the modeled geometry from the target mask layout, an adjustment compensating the deviation can thus be determined. | 03-17-2016 |
20160103946 | FOCUS MEASUREMENTS USING SCATTEROMETRY METROLOGY - Target designs and methods are provided, which relate to periodic structures having elements recurring with a first pitch in a first direction. The elements are periodic with a second pitch along a second direction that is perpendicular to the first direction and are characterized in the second direction by alternating, focus-sensitive and focus-insensitive patterns with the second pitch. In the produced targets, the first pitch may be about the device pitch and the second pitch may be several times larger. The first, focus-insensitive pattern may be produced to yield a first critical dimension and the second, focus-sensitive pattern may be produced to yield a second critical dimension that may be equal to the first critical dimension only when specified focus requirements are satisfied, or provide scatterometry measurements of zeroth as well as first diffraction orders, based on the longer pitch along the perpendicular direction. | 04-14-2016 |
20160162623 | METHOD, COMPUTER READABLE STORAGE MEDIUM AND COMPUTER SYSTEM FOR CREATING A LAYOUT OF A PHOTOMASK - A method includes providing a layout of a portion of a photomask. The layout includes a plurality of target features having a shape in accordance with a corresponding one of a target shape. For each of the target shapes, a local map specifying a respective value of a local sub-resolution assist feature (SRAF) usefulness for each of a plurality of positions relative to the target shape is provided. For each of the target features, an assignment of a part of the values of the local SRAF usefulness of the local map for the target shape corresponding to a target feature to a position relative to the portion of the photomask is provided. A global map specifying a global SRAF usefulness for each of the positions relative to the portion of the photomask is provided on the basis of the assignment of the values of the local SRAF usefulness. | 06-09-2016 |
20160162626 | LITHOGRAPHY PROCESS WINDOW PREDICTION BASED ON DESIGN DATA - A method of manufacturing a semiconductor device, comprising providing design data, producing lithography masks based on the design data, predicting a product process window and producing a wafer including semiconductor structures by means of the lithography masks and observing conditions defined by the product process window. | 06-09-2016 |
20160178999 | METHOD OF DESIGNING LITHOGRAPHY FEATURES BY SELF-ASSEMBLY OF BLOCK COPOLYMER | 06-23-2016 |
20160180003 | DIVIDING LITHOGRAPHY EXPOSURE FIELDS TO IMPROVE SEMICONDUCTOR FABRICATION | 06-23-2016 |
20160378899 | SEMICONDUCTOR AREA OPTIMIZATION - Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region. | 12-29-2016 |
20160378904 | EARLY OVERLAY PREDICTION AND OVERLAY-AWARE MASK DESIGN - Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer. | 12-29-2016 |