Class / Patent application number | Description | Number of patent applications / Date published |
716054000 | Manufacturing optimizations | 61 |
20100325591 | Generation and Placement Of Sub-Resolution Assist Features - Sub-resolution assist features (SRAFs) are placed in a template form and in series adjacent to main features in a layout design. After each SRAF template is placed, a clean-up process is conducted according to clean-up rules if necessary. Both SRAF templates and clean-up rules may be derived by using a model-based method or an optimization approach. Methods according to various embodiments of the invention may be used to place SRAFs near some two-dimensional main features such as contact features. | 12-23-2010 |
20110099526 | Pattern Selection for Full-Chip Source and Mask Optimization - The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result. | 04-28-2011 |
20110138343 | Pattern Transfer Modeling for Optical Lithographic Processes - Various implementations of the invention provide for the optimization of etch induced pattern transfer across a significant portion of a design. In various implementations, an entire design, that is a “full-chip” may be optimized. With some implementations, the invention may be employed to detect etch hotspots. Further implementations may be employed in either or both a mask data preparation process (“MDP”) or to determine the etch effects of including various patterns in a design. | 06-09-2011 |
20110231804 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
20120011479 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 01-12-2012 |
20120036487 | FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS - A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected from a set of points on an edge in the continuous mask. A first end point is identified on the edge such that a separation metric between the first origin point and the first end point is at least equal to a threshold value. Several alternatives are determined for fracturing using the first origin point and the first end point. A cost associated with each of the several alternatives is computed and one of the alternatives is selected as a preferred fracturing. Several pairs of origin points and end points are formed from the set of points. Each pair has a cost of a preferred fracturing between the pair. The continuous mask is fractured using a subset of the several pairs. | 02-09-2012 |
20120102441 | MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS - A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site. | 04-26-2012 |
20120117521 | Pattern-Dependent Proximity Matching/Tuning Including Light Manipulation By Projection Optics - Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs). | 05-10-2012 |
20120117522 | Optimization of Source, Mask and Projection Optics - Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a source, a mask, and the projection optics. The projection optics is sometimes broadly referred to as “lens”, and therefore the joint optimization process may be termed source mask lens optimization (SMLO). SMLO is desirable over existing source mask optimization process (SMO), partially because including the projection optics in the optimization can lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics. The projection optics can be used to shape wavefront in the lithographic projection apparatus, enabling aberration control of the overall imaging process. According to the embodiments herein, the optimization can be accelerated by iteratively using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs). | 05-10-2012 |
20120124529 | Pattern-Independent and Hybrid Matching/Tuning Including Light Manipulation by Projection Optics - Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing illumination source and projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs). | 05-17-2012 |
20120151422 | ROBUST DESIGN USING MANUFACTURABILITY MODELS - The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products. | 06-14-2012 |
20120159405 | METHOD OF FORMING PHOTOMASK USING CALIBRATION PATTERN, AND PHOTOMASK HAVING CALIBRATION PATTERN - A method of forming a photomask using a calibration pattern that may exactly transfer a desired pattern to a substrate. The method includes providing one-dimensional calibration design patterns each having first design measures and providing two-dimensional calibration design patterns each having second design measures; obtaining one-dimensional calibration measured patterns using the one-dimensional calibration design patterns and obtaining two-dimensional calibration measured patterns using the two-dimensional calibration design patterns; obtaining first measured measures of the one-dimensional calibration measured patterns and obtaining second measured measures of the two-dimensional calibration measured patterns; establishing a correlation between the first measured measures and the second measured measures; and converting a main measured measure of a main pattern into a corresponding one of the first measured measures using the correlation. | 06-21-2012 |
20120192124 | OPTICAL PROXIMITY CORRECTION VERIFICATION ACCOUNTING FOR MASK DEVIATIONS - Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure. | 07-26-2012 |
20120198396 | METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus. | 08-02-2012 |
20120210281 | FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS - A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected from a set of points on an edge in the continuous mask. A first end point is identified on the edge such that a separation metric between the first origin point and the first end point is at least equal to a threshold value. Several alternatives are determined for fracturing using the first origin point and the first end point. A cost associated with each of the several alternatives is computed and one of the alternatives is selected as a preferred fracturing. Several pairs of origin points and end points are formed from the set of points. Each pair has a cost of a preferred fracturing between the pair. The continuous mask is fractured using a subset of the several pairs. | 08-16-2012 |
20120221984 | METHOD OF OPTIMIZATION OF A MANUFACTURING PROCESS OF AN INTEGRATED CIRCUIT LAYOUT - A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns. | 08-30-2012 |
20120254813 | Integration of Lithography Apparatus and Mask Optimization Process with Multiple Patterning Process - The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow. | 10-04-2012 |
20120260223 | Retargeting for Electrical Yield Enhancement - A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting. | 10-11-2012 |
20120324406 | METHOD OF OPTIMIZATION OF A MANUFACTURING PROCESS OF AN INTEGRATED CIRCUIT LAYOUT - A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns. | 12-20-2012 |
20120331429 | CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT - Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor. | 12-27-2012 |
20120331430 | CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT - Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor. | 12-27-2012 |
20130036390 | Layout Content Analysis for Source Mask Optimization Acceleration - The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign. In further implementations, the difficult-to-print sections may be subjected to a source mask optimization process. Subsequently, the entire layout design may receive a conventional resolution enhancement treatment using the optimized source. | 02-07-2013 |
20130042212 | Multivariable Solver for Optical Proximity Correction - The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout. | 02-14-2013 |
20130091475 | Polarization Monitoring Reticle Design for High Numerical Aperture Lithography Systems - This invention relates to the manufacture of semiconductor substrates such as wafers and to a method for monitoring the state of polarization incident on a photomask in projection printing using a specially designed polarization monitoring reticle for high numerical aperture lithographic scanners. The reticle measures 25 locations across the slit and is designed for numerical apertures above 0.85. The monitors provide a large polarization dependent signal which is more sensitive to polarization. A double exposure method is also provided using two reticles where the first reticle contains the polarization monitors, clear field reference regions and low dose alignment marks. The second reticle contains the standard alignment marks and labels. For a single exposure method, a tri-PSF low dose alignment mark is used. The reticles also provide for electromagnetic bias wherein each edge is biased depending on that edge's etch depth. | 04-11-2013 |
20130174103 | MANDREL MODIFICATION FOR ACHIEVING SINGLE FIN FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE - Methods for forming a single fin fin-like field effect transistor (FinFET) device are disclosed. An exemplary method includes providing a main mask layout and a trim mask layout to form fins of a fin-like field effect transistor (FinFET) device, wherein the main mask layout includes a first masking feature and the trim mask layout includes a second masking feature that defines at least two fins, the first masking feature and the second masking feature having a spatial relationship; and modifying the main mask layout based on the spatial relationship between the first masking feature and the second masking feature, wherein the modifying the main mask layout includes modifying the first masking feature such that a single fin FinFET device is formed using the modified main mask layout and the trim mask layout. | 07-04-2013 |
20130174104 | PLACEMENT AWARE CLOCK GATE CLONING AND FANOUT OPTIMIZATION - Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design. | 07-04-2013 |
20130174105 | METHOD AND APPARATUS FOR PLASMA PROCESSING - A plasma processing apparatus is disclosed for minimizing the non-uniformity of potential distribution around wafer circumference. The apparatus includes a focus ring formed of a dielectric, and a conductor or a semiconductor having RF applied thereto. A surface voltage of the focus ring is determined to be not less than a minimum voltage for preventing reaction products caused by wafer processing from depositing thereon. The surface height, surface voltage, material, and structure of the focus ring are optimized so that the height of an ion sheath formed on the focus ring surface is either equal or has a height difference within an appropriate tolerance range to the height of the ion sheath formed on the wafer surface. | 07-04-2013 |
20130179847 | Source Mask Optimization to Reduce Stochastic Effects - Disclosed herein is a computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method comprising defining a multi-variable cost function, the multi-variable cost function being a function of a stochastic effect of the lithographic process. | 07-11-2013 |
20130219350 | REDUCE MASK OVERLAY ERROR BY REMOVING FILM DEPOSITED ON BLANK OF MASK - A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and a frame area outside the die area. Fiducial features within the frame area are identified, and from the fiducial features, an idle frame area is identified. A reference mask design, which corresponds to a reference mask configured to be aligned with the mask, is used to determine a reference density for the idle frame area. The idle frame area of the mask design database is modified to correspond to the reference density. The modified mask design database is then available for further use including manufacturing the mask. | 08-22-2013 |
20130227498 | PATTERN BASED METHOD FOR IDENTIFYING DESIGN FOR MANUFACTURING IMPROVEMENT IN A SEMICONDUCTOR DEVICE - A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. Outer markers are generated in the computing apparatus for at least a subset of the features based on the proximity of the features to one another and spacing requirements. Features are identified in the computing apparatus where the associated outer marker has at least one dimension greater than the dimensions specified for the feature. | 08-29-2013 |
20130263063 | MASK DESIGN METHOD, PROGRAM, AND MASK DESIGN SYSTEM - A method, an article of manufacture, and a system for designing a mask. The method for designing a mask is implemented by a computer device having a memory, a processor device communicatively coupled to the memory, and a module configured to carry out the method including the steps of: generating an optical domain representation from a design pattern and an imaging light; and optimizing the optical domain representation under a constraint that values of negative excursions at predetermined evaluation points must be greater than or equal to predetermined negative threshold values assigned to the predetermined evaluation points; where: the optical domain representation is a variable representation of a wavefront; the imaging light is light that is transmitted through the mask; the negative excursions are in an object domain representation of the optical domain representation; and the predetermined evaluation points are in the object domain representation. | 10-03-2013 |
20130263064 | METHODS AND SYSTEM FOR MODEL-BASED GENERIC MATCHING AND TUNING - The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time. | 10-03-2013 |
20130326437 | GRADIENT-BASED PATTERN AND EVALUATION POINT SELECTION - Described herein is a method for a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic imaging apparatus, the lithographic process having a plurality of design variables, the method comprising: calculating a gradient of each of a plurality of evaluation points or patterns of the lithographic process, with respect to at least one of the design variables; and selecting a subset of evaluation points from the plurality of evaluation points or patterns based on the gradient. | 12-05-2013 |
20140033145 | PATTERN-DEPENDENT PROXIMITY MATCHING/TUNING INCLUDING LIGHT MANIPULATION BY PROJECTION OPTICS - Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs). | 01-30-2014 |
20140068529 | SOLUTIONS FOR RETARGETING INTEGRATED CIRCUIT LAYOUTS BASED ON DIFFRACTION PATTERN ANALYSIS - A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function. | 03-06-2014 |
20140068530 | FAST FREEFORM SOURCE AND MASK CO-OPTIMIZATION METHOD - The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present invention allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present invention allows for free-form optimization, without the constraints required by conventional optimization techniques. | 03-06-2014 |
20140089870 | Inspection Method and Apparatus and Lithographic Processing Cell - A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of the process signature for the lithographic tool; and using the process signature model to calculate the process corrections for the lithographic tool. | 03-27-2014 |
20140101625 | DESIGN RULE OPTIMIZATION IN LITHOGRAPHIC IMAGING BASED ON CORRELATION OF FUNCTIONS REPRESENTING MASK AND PREDEFINED OPTICAL CONDITIONS - Methods, computer program products and apparatuses for optimizing design rules for producing a mask are disclosed, while keeping the optical conditions (including but not limited to illumination shape, projection optics numerical aperture (NA) etc.) fixed. A cross-correlation function is created by multiplying the diffraction order functions of the mask patterns with the eigenfunctions from singular value decomposition (SVD) of a TCC matrix. The diffraction order functions are calculated for the original design rule set, i.e., using the unperturbed condition. ILS is calculated at an edge of a calculated image of a critical polygon using the cross-correlation results and using translation properties of a Fourier transform. Once an optimum separation is calculated, it is incorporated into the design rule to optimize the mask layout for improved ILS throughout the mask. | 04-10-2014 |
20140143742 | Design, Layout, and Manufacturing Techniques for Multivariant Integrated Circuits - An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout. | 05-22-2014 |
20140223394 | METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE - A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line. | 08-07-2014 |
20140223395 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 08-07-2014 |
20140282301 | STITCH INSERTION FOR REDUCING COLOR DENSITY DIFFERENCES IN DOUBLE PATTERNING TECHNOLOGY (DPT) - Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density. | 09-18-2014 |
20140282302 | Multi-etch process using material-specific behavioral parameters in 3-D virtual fabrication environment - A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior. | 09-18-2014 |
20140282303 | PATTERN-INDEPENDENT AND HYBRID MATCHING/TUNING INCLUDING LIGHT MANIPULATION BY PROJECTION OPTICS - Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing illumination source and projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs). | 09-18-2014 |
20140331192 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME USING SEMICONDUCTOR FIN DENSITY DESIGN RULES - A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion. | 11-06-2014 |
20140365984 | VERIFICATION SUPPORT METHOD, RECORDING MEDIUM HAVING STORED VERIFICATION SUPPORT PROGRAM THEREIN, AND VERIFICATION SUPPORT APPARATUS - A verification support apparatus for an integrated circuit. The apparatus includes; a combination acquisition unit configured to acquire different combinations of a variable value regarding variation in an integrated circuit manufacturing process and a performance value obtained from a simulation of a circuit; a function acquisition unit configured to acquire a functional relationship from which a performance value of a circuit is obtained by giving a parameter value; a difference calculation unit configured to calculate a difference between the performance value obtained by the functional relationship and the performance value included in the combination; an expected value calculation unit configured to determine a probability based on random numbers and execute a calculation process in which an expected value of the difference is calculated based on the determined probability and the difference calculated by the difference calculation unit a predetermined number of times; and a goodness of fit calculation unit configured to calculate a goodness of fit (GF) between the simulation and the functional relationship. | 12-11-2014 |
20150058816 | METHOD FOR INTEGRATED CIRCUIT DESIGN LAYOUT SUPPORT BY COMPUTER AND APPARATUS OF INTEGRATED CIRCUIT DESIGN LAYOUT SUPPORT BY COMPUTER - According to one embodiment, a method is disclosed for designing an integrated circuit by a computer including an input unit, a memory unit, a calculating unit, and an output unit. The method can include storing a design model in the memory unit. The design model has parameters of physical quantities of active elements, passive elements, and an interconnection pattern included in the integrated circuit. The design model has an algorithm generating a circuit layout from values of the parameters. The method can include inputting the values of the parameters based on a first design specification of the integrated circuit by the input unit, generating a first circuit layout of the active elements, the passive elements, and the interconnection pattern by the calculating unit using the design model from the values of the parameters received by the input unit, and outputting the first circuit layout by the output unit. | 02-26-2015 |
20150074621 | METHOD OF OBTAINING POSITION, EXPOSURE METHOD, AND METHOD OF MANUFACTURING ARTICLE - The present invention provides a method of obtaining a position of a second shot region next to a first shot region, out of a plurality of shot regions formed on a substrate, comprising a first detection step of detecting a position of a first mark arranged in the first shot region, a second detection step of detecting a position of a mark more distant from the first mark, out of a second mark and a third mark arranged in the second shot region, and a determination step of determining the position of the second shot region based on a detection result in the first detection step and a detection result in the second detection step. | 03-12-2015 |
20150074622 | OPTIMIZATION OF SOURCE, MASK AND PROJECTION OPTICS - Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a source, a mask, and the projection optics. The projection optics is sometimes broadly referred to as “lens”, and therefore the joint optimization process may be termed source mask lens optimization (SMLO). SMLO is desirable over existing source mask optimization process (SMO), partially because including the projection optics in the optimization can lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics. The projection optics can be used to shape wavefront in the lithographic projection apparatus, enabling aberration control of the overall imaging process. According to the embodiments herein, the optimization can be accelerated by iteratively using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs). | 03-12-2015 |
20150082259 | LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN - A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern. | 03-19-2015 |
20150082260 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 03-19-2015 |
20150143305 | RETICLE DATA DECOMPOSITION FOR FOCAL PLANE DETERMINATION IN LITHOGRAPHIC PROCESSES - A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions. | 05-21-2015 |
20150149970 | SIMULATION METHOD, SIMULATION PROGRAM, PROCESS CONTROL SYSTEM, SIMULATOR, PROCESS DESIGN METHOD, AND MASK DESIGN METHOD - A simulation method includes acquiring processing conditions for performing an etching process using plasma on a surface of a wafer covered by a mask having a predetermined mask thickness and aperture ratio, calculating, based on the conditions, a flux amount of a reaction product that enters the surface, calculating, based on mask information including the thickness and the aperture ratio and the flux amount, an etching rate of the wafer, calculating, based on the conditions and the etching rate, a dissociation fraction of the product, calculating, based on the information and the etching rate, a solid angle at a predetermined evaluation point set on the surface, the solid angle corresponding to a view area in which plasma space can be seen from the evaluation point, and calculating, based on the etching rate, the dissociation fraction, the solid angle, and the aperture ratio, a control index for evaluating a surface shape. | 05-28-2015 |
20150294056 | Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity - The present disclosure provides an IC method that includes receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks; calculating main pattern density PD | 10-15-2015 |
20150294057 | Method of Fabricating an Integrated Circuit with Block Dummy for Optimized Pattern Density Uniformity - The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication. | 10-15-2015 |
20150363532 | OPTIMIZATION OF INTEGRATED CIRCUITS FOR A RETICLE TRANSMISSION PROCESS WINDOW USING MULTIPLE FILL CELLS - Embodiments of the present invention include systems and methods of controlling reticle transmission. A process window for reticle transmission is received. For a given design, default fill cells of a default fill pattern are inserted in unused areas of an integrated circuit (IC). A pattern density is computed for each tile of an IC at each appropriate level, such as metallization levels and contact levels. An IC reticle transmission (RT) is computed for an area corresponding to an entire (or area of) IC or reticle. If the integrated circuit RT is outside of the process window, then the tiles that have an individual tile RT that is outside of the process window are identified and ranked into groups. Default fill cells in one group of tiles are replaced with replacement fill cells having an appropriate pattern and pattern density, and an updated IC RT parameter is computed until the updated IC RT parameter is within the process window. | 12-17-2015 |
20150370942 | Method of Fabricating an Integrated Circuit with Non-Printable Dummy Features - The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r | 12-24-2015 |
20160110488 | SOURCE MASK OPTIMIZATION TO REDUCE STOCHASTIC EFFECTS - Disclosed herein is a computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method comprising defining a multi-variable cost function, the multi-variable cost function being a function of a stochastic effect of the lithographic process. | 04-21-2016 |
20160140278 | Modeling Photoresist Shrinkage Effects In Lithography - Aspects of the disclosed techniques relate to techniques for resist simulation in lithography. Local light power values are determined for a plurality of sample points in boundary regions of an aerial image of a feature to be printed on a resist coating, wherein each of the local light power values represents a light power value for an area surrounding one of the plurality of sample points. Based on the local light power values, a vertical shrinkage function is constructed. Resist contour data of the feature are then computed based at least on resist shrinkage effects modeled using the local light power values and the vertical shrinkage function. | 05-19-2016 |
20160171142 | LITHOGRAPHY MASK FUNCTIONAL OPTIMIZATION AND SPATIAL FREQUENCY ANALYSIS | 06-16-2016 |
20160252820 | METHOD AND APPARATUS FOR DESIGN OF A METROLOGY TARGET | 09-01-2016 |