Entries |
Document | Title | Date |
20110010679 | METHOD FOR MULTI-CYCLE CLOCK GATING - An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle clock gater generates multi-cycle gating groups of data latching devices of a circuit design. The circuit design updater updates the circuit design with selected multi-cycle gating groups. Each gating group is associated with a single gating function. For each gating group, data latching devices of 0 | 01-13-2011 |
20110088005 | METHOD AND APPARATUS FOR CONFIGURING A CONTENT-ADDRESSABLE MEMORY (CAM) DESIGN AS BINARY CAM OR TERNARY CAM - A method for producing a configurable content-addressable memory (CAM) cell design, in which the method includes: inputting the configurable CAM cell design to a computer, the configurable CAM cell design capable of being configured as one of a binary CAM design and a ternary CAM design, depending on connections of a metal overlay; selecting one of a first metal overlay design for the binary CAM design and a second metal overlay design for a ternary CAM design; if the first metal overlay design is selected, then combining the first metal overlay design with the configurable CAM cell design to produce a binary CAM design including two binary CAM cells with a single search port, and outputting the binary CAM design; and if the second metal overlay design is selected, then combining the second metal overly design with the configurable CAM cell design to produce a ternary CAM design including a single ternary CAM cell with two search ports, and outputting the ternary CAM design by the computer. | 04-14-2011 |
20110099527 | DYNAMICALLY RECONFIGURABLE SELF-MONITORING CIRCUIT - A method configures a plurality of circuit elements for execution of an application in a first configuration. The method monitors the execution of the application on the plurality of circuit elements to produce monitoring information, using a computerized device, and stores the monitoring information in a storage structure. The method selectively communicates the monitoring information to an external element separate from the computerized device. The external element transforms the first configuration into a second configuration based on the monitoring information. The computerized device receives the second configuration from the external element and reconfigures the plurality of elements into the second configuration. | 04-28-2011 |
20110126162 | Design Structure for a Duty Cycle Correction Circuit - A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal. | 05-26-2011 |
20110131539 | REWIRING USING IRREDUNDANCY REMOVAL AND ADDITION - This invention proposes a new restructuring technique, Rewiring Using IRredundancy Removal and Addition (IRRA) used in the synthesis and optimization of logic designs. This method successfully removes any desired target wire by constructing a corresponding rectification network which exactly corrects the error of the circuit caused by the removal of the target wire. The rectification network can be further simplified to achieve excellent area optimization. | 06-02-2011 |
20110154275 | METHOD AND SYSTEM FOR DEFINING GENERIC TOPOLOGIES FOR USE IN TOPOLOGY MATCHING ENGINES - Circuit analysis software packages are a significant tool used today in the design of integrated circuits (ICs). Many of the conventional and commercially available simulation or analysis packages, however, are limited to performing static design “checks” using topology based search algorithms to find potential problems in a subject design. Here, a system is provided that allows a user to define parameters that comport with the subject design to generate a set of specific topologies from a set of generic topologies. These generated topologies can then be used to perform a more thorough analysis of the subject design. | 06-23-2011 |
20110154276 | METHOD AND SYSTEM FOR OPTIMALLY PLACING AND ASSIGNING INTERFACES IN A CROSS-FABRIC DESIGN ENVIRONMENT - A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface. | 06-23-2011 |
20110173579 | Rectilinear Covering Method With Bounded Number of Rectangles for Designing a VLSI Chip - A method for creating a rectilinear non-convex polygonal output representative of a component used to build a VLSI circuit chip from a plurality of points corresponding to a plurality of components of the chip includes: covering the plurality of points with a set of rectangles; creating a Voronoi diagram for the set of rectangles; forming a nearest neighbor tree for the Voronoi diagram; connecting a selected set of the rectangles corresponding to the nearest neighbor tree into a non-convex rectilinear polygon; and applying the non-convex rectilinear polygon to build the VLSI chip. | 07-14-2011 |
20110302540 | SEMICONDUCTOR DEVICE COMPRISING SHIELD TREE AND RELATED LAYOUT METHOD - A semiconductor device comprises a plurality of flip-flops, a clock tree for transferring an externally input clock signal to the flip-flops, and a shield tree configured to shield the clock tree. The shield tree transmits a control signal to activate the flip-flops in a test operation mode of the semiconductor device. | 12-08-2011 |
20120221986 | SYSTEM AND PROCESS FOR AUTOMATED CIRCUITING AND BRANCH CIRCUIT WIRING - A system or process for providing complete electrical designs through: computer-automated circuiting; computer automated service device selection, placement, and interconnection; and computer-automated branch circuit wiring, wherein the complete electrical design complies with regulatory, industry standard practice, and client criteria. | 08-30-2012 |
20150058818 | PROGRAMMABLE PATTERN AWARE VOLTAGE ANALYSIS - This application discloses a voltage analysis tool to perform a static power aware analysis on a circuit design without having to simulate the circuit design. The voltage analysis tool can determine a set of components in the circuit design corresponds to a design pattern representing a voltage-transition device, and set an output voltage for the set of components based, at least in part, on characteristics of the voltage-transition device. The voltage analysis tool can propagate the output voltage to other portions of the circuit design, and determine whether the portions of the circuit design receiving the output voltage have a rule violation. | 02-26-2015 |
20220138380 | TRAINING DATA GENERATING METHOD AND COMPUTING SYSTEM - An information processing apparatus specifies a first pattern indicating a first layer included in first circuit data. The information processing apparatus generates, based on first wiring included in a second pattern indicating a second layer that is adjacent to the first layer and a slit included in the first pattern, second circuit data by changing the first pattern to a third pattern including second wiring corresponding to the first wiring. The information processing apparatus generates, based on the second circuit data, training data for machine learning. | 05-05-2022 |
20220138611 | QUANTUM PROCESSOR UNIT ARCHITECTURE FOR QUANTUM COMPUTING VIA AN ARBITRARILY PROGRAMMABLE INTERACTION CONNECTIVITY GRAPH - A superconducting quantum processor unit for quantum computing is provided. The processor unit is formed from the union of a qubit chip and a wiring chip with superconducting bonding bumps and spacers. The bumps may be densely distributed around active elements between the two chips and effectively form a Faraday-Cage around the qubits, control signal waveguides etc. The qubit chip has strategically spaced qubits and an inductively coupled probe line and the wiring chip has a bus coupling resonator with a number of voltage nodes and anti-nodes, a resonator pump and at least one SQUID. Magnetic flux applied through the SQUIDs changes their impedances and modifies the microwave boundary conditions of the bus. This allows in-situ shifting of electric field distributions of the resonance modes of the bus along the length of the bus. This tunes the coupling rates of the bus to all qubits simultaneously. | 05-05-2022 |