01st week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090001403 | INDUCTIVELY EXCITED QUANTUM DOT LIGHT EMITTING DEVICE - A method and apparatus is provided for activating a layer ( | 2009-01-01 |
20090001404 | SEMICONDUCTOR LIGHT EMITTING DEVICE, PROCESS FOR PRODUCING THE SAME, AND LED ILLUMINATING APPARATUS USING THE SAME - The present invention provides a semiconductor light emitting device comprising: a wiring substrate in which a pair of positive and negative electrodes are formed on a front surface of an insulating substrate, an LED arranged over one of the electrodes, or arranged to stretch over both of the electrodes and connected electrically to the positive and negative electrode pair, and a metal frame having, at the inner circumferential side thereof, a tapered face and arranged around the electrode pair on the front surface of wiring substrate, wherein the metal frame is jointed to the front surface of the wiring substrate through an adhesive layer, and a plating layer is formed on a surface of the metal frame and surfaces of the electrode pair. | 2009-01-01 |
20090001405 | LIGHT EMITTING DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - Provided is a light emitting device package. The light emitting device package comprises a base substrate, a frame, and a light emitting device. The base substrate comprises a plurality of electrode pads. The frame is formed of silicon, attached on the base substrate, and has an opening. The light emitting device is electrically connected to the electrode pad in the opening. | 2009-01-01 |
20090001406 | Light-emitting device and method for fabricating same - An LED chip is mounted on a submount, and submount electrodes are formed to constitute a submount member. A light-emitting unit is configured by mounting the submount member on a flat substrate. A lead frame member having a lead frame electrode is configured using a lead frame and a resin mold. A light-emitting device is obtained by overlapping the light-emitting unit and the lead frame member, so that the electrodes contact each other. There is accordingly obtained a light-emitting device that is highly reliable with respect to vibration, shock, and other external forces; that efficiently dissipates generated heat; and that is readily fabricated; and a method for fabricating same. | 2009-01-01 |
20090001407 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF, AND LAMP - There is provided a semiconductor light-emitting device having excellent light extraction efficiency, a manufacturing method thereof, and a lamp. A semiconductor light-emitting device | 2009-01-01 |
20090001408 | Method for forming a semiconductor light-emitting device and a semiconductor light-emitting device - A semiconductor light-emitting device with a new layer structure is disclosed, where the current leaking path is not caused to enhance the current injection efficiency within the active layer. The device provides a mesa structure containing active layer and a p-type lower cladding layer on a p-type substrate and a burying layer doped with iron (Fe) to bury the mesa structure, where the burying layer shows a semi-insulating characteristic. The device also provides an n-type blocking layer arranged so as to cover at least a portion of the p-type buffer lower within the mesa structure. The n-type blocking layer prevents the current leaking from the burying layer to the p-type buffer layer, and the semi-insulating burying layer that covers the rest portion of the mesa structure not covered by the n-type blocking layer prevents the current leaking from the n-type blocking layer to the n-type cladding layer within the mesa structure. | 2009-01-01 |
20090001409 | Semiconductor Light Emitting Device And Illuminating Device Using It - The semiconductor light emitting device of the present invention comprises an n-type nitride semiconductor layer | 2009-01-01 |
20090001410 | Driver Circuit and Electrical Power Conversion Device - An electrical power conversion device includes: a switching element in which a principal electrical current flows in a direction from a second electrode towards a first electrode based upon a voltage being applied to a control electrode; a voltage control circuit that controls the voltage that is applied to the control electrode; and a continuity control circuit that is connected between the second electrode and the control electrode and controls continuity between the second electrode and the control electrode. | 2009-01-01 |
20090001411 | Semiconductor device - A semiconductor device includes a spaced-channel IGBT and an antiparalell diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region. | 2009-01-01 |
20090001412 | PHOTODETECTOR AND PRODUCTION METHOD THEREOF - The invention offers a photodetector that has an N-containing InGaAs-based absorption layer having a sensitivity in the near-infrared region and that suppresses the dark current and a production method thereof. The photodetector is provided with an InP substrate | 2009-01-01 |
20090001413 | METHOD OF DOPING FIELD-EFFECT-TRANSISTORS (FETs) WITH REDUCED STRESS/STRAIN RELAXATION AND RESULTING FET DEVICES - A method for fabricating a FET transistor for an integrated circuit by the steps of forming recesses in a substrate on both sides of a gate on the substrate, halo/extension ion implanting into the recesses, and filling the recesses with embedded strained layers comprising dopants for in-situ doping of the source and drain of the transistor. The stress/strain relaxation of the resulting transistor is reduced. | 2009-01-01 |
20090001414 | STRUCTURES AND METHODS OF FORMING SIGE AND SIGEC BURIED LAYER FOR SOI/SIGE TECHNOLOGY - Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. | 2009-01-01 |
20090001415 | MULTI-GATE TRANSISTOR WITH STRAINED BODY - A semiconductor device comprises a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate, wherein the semiconductor body comprises a silicon alloy core having a top surface and laterally opposite sidewalls formed on a silicon fin structure, and a silicon shell layer formed on the top surface and the laterally opposite sidewalls of the silicon alloy core, wherein the silicon alloy core imparts a strain on the silicon shell layer. The semiconductor device further comprises a gate dielectric layer formed on the top surface and the laterally opposite sidewalls of the semiconductor body and a gate electrode formed on the gate dielectric layer. | 2009-01-01 |
20090001416 | Growth of indium gallium nitride (InGaN) on porous gallium nitride (GaN) template by metal-organic chemical vapor deposition (MOCVD) - Si-doped porous GaN is fabricated by UV-enhanced Pt-assisted electrochemical etching and together with a low-temperature grown buffer layer are utilized as the template for InGaN growth. The porous network in GaN shows nanostructures formed on the surface. Subsequent growth of InGaN shows that it is relaxed on these nanostructures as the area on which the growth takes place is very small. The strain relaxation favors higher indium incorporation. Besides, this porous network creates a relatively rough surface of GaN to modify the surface energy which can enhance the nucleation of impinging indium atoms thereby increasing indium incorporation. It shifts the luminescence from 445 nm for a conventionally grown InGaN structure to 575 nm and enhances the intensity by more than two-fold for the growth technique in the present invention under the same growth conditions. There is also a spectral broadening of the output extending from 480 nm to 720 nm. | 2009-01-01 |
20090001417 | STRUCTURES AND METHODS OF FORMING SIGE AND SIGEC BURIED LAYER FOR SOI/SIGE TECHNOLOGY - Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. The invention is also directed to a design structure on which a circuit resides. | 2009-01-01 |
20090001418 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a transistor, the method includes forming a gate over a substrate to form a first resultant structure, forming a gate spacer at first and second sidewalls of the gate, etching portions of the substrate proximate to the gate spacer to form a recess in a source/drain region of the substrate, forming a first epitaxial layer including germanium to fill the recess, and performing a high temperature oxidation process to form a second epitaxial layer including germanium over an interfacial layer between the substrate and the first epitaxial layer, the second epitaxial layer having a germanium concentration that is higher than a germanium concentration of the first epitaxial SiGe layer, thereby forming a second resultant structure. | 2009-01-01 |
20090001419 | Non-Volatile Memory Devices and Methods of Fabricating the Same - Provided are non-volatile memory devices that may realize high integration and have high reliability. A plurality of first semiconductor layers are stacked on a substrate. A plurality of second semiconductor layers are interposed between the plurality of first semiconductor layers, respectively, and are recessed from one end of each of the plurality of first semiconductor layers to define a plurality of first trenches between the plurality of first semiconductor layers. A plurality of first storage nodes are provided on surfaces of the second semiconductor layers inside the plurality of first trenches. Devices may include a plurality of first control gate electrodes that are formed on the plurality of first storage nodes to fill the plurality of first trenches. | 2009-01-01 |
20090001420 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate. | 2009-01-01 |
20090001421 | NANOTUBE TRANSISTOR INTEGRATED CIRCUIT LAYOUT - An integrated circuit layout of a carbon nanotube transistor device includes a first and second conductive material. The first conductive material is connected to ends of single-walled carbon nanotubes below (or above) the first conductive material. The second conductive material is not electrically connected to the nanotubes below (or above) the second conductive material. The first conductive material may be metal, and the second conductive material may be polysilicon or metal. The nanotubes are perpendicular to the first conductive material. In one implementation, the first and second conductive materials form interdigitated fingers. In another implementation, the first conductive material forms a serpentine track. | 2009-01-01 |
20090001422 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - There is provided a manufacturing method of a semiconductor apparatus, including forming an InGaP layer on a substrate, forming a gate electrode having a Ti layer and an Au layer by vapor deposition on an upper surface of the InGaP layer, further forming a GaAs layer on the upper surface of the InGaP layer in a region different from a region in which the gate electrode is formed, and further forming a source electrode and a drain electrode on an upper surface of the GaAs layer. When the gate electrode having the Ti and Au layers is formed on the upper surface of the InGaP layer, the Ti and Au layers are formed with a substrate temperature being set equal to or lower than 180° C. | 2009-01-01 |
20090001423 | Field-effect transistor and method of making same - A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode. The electron supply layer has a substantially flat surface between the source electrode and the gate electrode and between the drain electrode and the gate electrode. | 2009-01-01 |
20090001424 | III-nitride power device - A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device. | 2009-01-01 |
20090001425 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film. | 2009-01-01 |
20090001426 | Integrated Fin-Local Interconnect Structure - Embodiments of the invention generally relate to semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits. | 2009-01-01 |
20090001427 | CHARGE CARRIER BARRIER FOR IMAGE SENSOR - A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell. | 2009-01-01 |
20090001428 | Optimized transistor for imager device - An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e. one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a V | 2009-01-01 |
20090001429 | HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES - A semiconductor structure. The structure includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The structure further includes a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation. | 2009-01-01 |
20090001430 | ELIMINATE NOTCHING IN SI POST SI-RECESS RIE TO IMPROVE EMBEDDED DOPED AND INSTRINSIC SI EPITAZIAL PROCESS - A dielectric element, and method of manufacturing the same, is disclosed for a semiconductor structure which comprises a substrate having a gate formed on a top surface of the substrate. The substrate and gate define a gap in a region between the gate and the substrate. A specified amount of dielectric on the substrate, at least a portion of which is in the gap, forms the dielectric element which substantially prevents unwanted electrical connectivity between the gate and the substrate. | 2009-01-01 |
20090001431 | Method for forming semiconductor contacts - In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension. | 2009-01-01 |
20090001432 | Channel layer for a thin film transistor, thin film transistor including the same, and methods of manufacturing the same - Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer. | 2009-01-01 |
20090001433 | Image Sensor and Method for Manufacturing the Same - Provided are an image sensor and a method of fabricating the same. The image sensor includes a substrate having an active area and a device isolation area; a well implantation area in the active area; a threshold voltage implantation area in the well implantation area; and a transistor gate on the threshold voltage implantation area, wherein the threshold voltage implantation has a width greater than a width of the transistor gate. | 2009-01-01 |
20090001434 | Vertical Pin or Nip Photodiode and Method for the Production which is Compatible with a Conventional Cmos-Process - The invention relates to a fast photodiode and to a method for the production thereof in CMOS technology. The integrated PIN photodiode, which is formed or can be formed by CMOS technology, consists of an anode corresponding to a highly doped p-type substrate with a specific electric resistance of less than 50 mOhm*cm, a lightly p-doped l-region which is adjacent to the anode, and an n-type cathode which corresponds to the doping in the n-well region. The lightly doped l-region has a doping concentration of less than 10 | 2009-01-01 |
20090001435 | Visible Light Detecting Semiconductor Radiation Detector - A semiconductor radiation detector device, comprising a bulk layer ( | 2009-01-01 |
20090001436 | Memory device - Disclosed is a memory device having a transistor, the transistor including a substrate; a gate electrode formed on the substrate; an insulation layer formed on the gate electrode, the gate electrode and the insulation layer forming a convex portion; a conductive layer formed at a top of the convex portion; a source electrode formed on one side of the convex portion on the substrate; a drain electrode formed on the other side of the convex portion on the substrate where the source electrode is not formed; and a semiconductor layer formed on the insulation layer existing between the conductive layer and the source electrode and between the conductive layer and the drain electrode. | 2009-01-01 |
20090001437 | Integrated Circuit Devices Including Recessed Conductive Layers and Related Methods - An integrated circuit device may include a first insulating layer on a substrate with an opening through the first insulating layer. A conductive layer may be on the first insulating layer with the first insulating layer between the conductive layer and the substrate and with the conductive layer set back from the opening. A second insulating layer may be on the conductive layer with the conductive layer between the first and second insulating layers. The second insulating layer may be set back from the opening, and a sidewall of the conductive layer adjacent the opening may be recessed relative to a sidewall of the second insulating layer adjacent the opening. An insulating spacer on portions of the first insulating layer may surround the opening, and the insulating spacer may be on the sidewall of the second insulating layer adjacent the opening so that the insulating spacer is between the sidewall of the second conductive layer and the opening. A conductive contact may be in the opening through the first insulating layer and on portions of the insulating spacer so that the insulating spacer is between the conductive contact and the conductive layer. Related methods are also discussed. | 2009-01-01 |
20090001438 | Isolation of MIM FIN DRAM capacitor - In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a silicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulating layer. | 2009-01-01 |
20090001439 | Flash Memory Device and Method of Manufacturing the Same - Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region. | 2009-01-01 |
20090001440 | Semiconductor device with buried source rail - In one embodiment of the invention, a NOR Flash memory includes a buried source rail that directly connects to a source strap. Furthermore, a drain plug connects directly to a bit line. | 2009-01-01 |
20090001441 | Three dimensional quantum dot array - In one embodiment of the invention, oxidation of silicon in a silicon germanium/silicon lattice may convert a two dimensional array of silicon germanium pillars into a structured three dimensional quantum dot array. The array may be included in, for example, flash memory floating gate, optical detector, or quantum computing device. | 2009-01-01 |
20090001442 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material. | 2009-01-01 |
20090001443 | NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC - Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed. | 2009-01-01 |
20090001444 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor memory device comprising a plurality of gate electrodes extending to a first direction; a reinforced insulation film extending to a second direction crossing the first direction, and connected to the adjacent gate electrodes; and an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside. | 2009-01-01 |
20090001445 | Non-Volatile Memory Device and Method of Fabricating the Same - Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with second impurities; an electron injection region formed by doping the semiconductor substrate with first impurities, where a top surface of the electron injection region includes a tip portion at an edge; a floating gate electrode covering at least a portion of the control gate region and the tip portion of the electron injection region; a first tunnel oxide layer interposed between the floating gate electrode and the control gate region; a second tunnel oxide layer interposed between the floating gate electrode and the electron injection region; a trench surrounding the electron injection region in the semiconductor substrate; and a device isolation layer pattern filled in the trench. | 2009-01-01 |
20090001446 | FLASH MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A method of fabricating a flash memory device includes forming a stack electrode on a semiconductor substrate; forming a side spacer on a side wall of the stack electrode; forming a photo-resist film pattern with a predetermined thickness on the side wall of the side spacer; and forming a source/drain junction on the semiconductor substrate through ion implant using the photo-resist film as a mask for ion implant. | 2009-01-01 |
20090001447 | SEMICONDUCTOR DEVICE WITH DUMMY ELECTRODE - A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed. | 2009-01-01 |
20090001448 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a cell size of 60 nm or less includes a tunnel insulation film formed in a channel region of a silicon substrate containing a burying insulation film, a first conductive layer formed on the tunnel insulation film, an inter-electrode insulation film formed on the burying insulation film and the first conductive layer, a second conductive layer formed on the inter-electrode insulation film, a side wall insulation film formed on the side walls of the first conductive layer, the second conductive layer, and the inter-electrode insulation film, and an inter-layer insulation film formed on the side wall insulation film. The tunnel insulation film or the inter-electrode insulation film contains a high-dielectric insulation film. The side wall insulation film contains a predetermined concentration of carbon and nitrogen as well as chlorine having a concentration of 1×10 | 2009-01-01 |
20090001449 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area. | 2009-01-01 |
20090001450 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a lower semiconductor substrate, an upper semiconductor pattern on the lower semiconductor substrate, a device isolation pattern defining an active region in the lower semiconductor substrate and the upper semiconductor pattern, a lower charge storage layer between the upper semiconductor pattern and the lower semiconductor substrate, a gate conductive structure crossing over the upper semiconductor pattern, a first upper charge storage layer and a second upper charge storage layer spaced apart from each other between the gate conductive structure and the upper semiconductor pattern, and a source/drain region in the upper semiconductor pattern on both sides of the gate conductive structure. | 2009-01-01 |
20090001451 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed. | 2009-01-01 |
20090001452 | Semiconductor device and manufacturing method thereof - The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process. | 2009-01-01 |
20090001453 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION - A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection. | 2009-01-01 |
20090001454 | SEMICONDUCTOR DEVICE AND TRANSISTOR - A semiconductor device includes active areas which are insulatedly separated from each other by element-separation insulating films; a gate insulating film formed on each active area; a gate electrode which extends across the active area via the gate insulating film; a source area and a drain area formed in the active area so as to interpose the gate electrode; and a fin-channel structure in which at the intersection between the active area and the gate electrode, trenches are provided at both sides of the active area, and part of the gate electrode is embedded in each trench via the gate insulating film, so that the gate electrode extends across a fin which rises between the trenches. In the gate insulating film, the film thickness of a part which contacts the bottom surface of each trench is larger than that of a part which contacts the upper surface of the fin. | 2009-01-01 |
20090001455 | ACCUFET WITH SCHOTTKY SOURCE CONTACT - An accumulation mode FET (ACCUFET) having a source contact that makes Schottky contact with the base region thereof. | 2009-01-01 |
20090001456 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area. | 2009-01-01 |
20090001457 | Semiconductor structure - The present invention discloses a semiconductor structure comprising a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer on the U-shape trench, a U-shape gate region on the U-shape gate dielectric layer, a conducting matter in the U-shape gate region, and a cover dielectric layer on the conducting matter. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect. | 2009-01-01 |
20090001458 | SEMICONDUCTOR DEVICE WITH SUBSTANTIAL DRIVING CURRENT AND DECREASED JUNCTION LEAKAGE CURRENT - The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the stepped recess channel region. The gate structure is disposed over the stepped recess channel region of the gate region. | 2009-01-01 |
20090001459 | High power semiconductor device capable of preventing parasitical bipolar transistor from turning on - A high power semiconductor device capable of preventing parasitical bipolar transistor from turning on comprises a first conduction type drain region, a first conduction type epitaxial region formed on the first conduction type drain region, a plurality of second conduction type body regions formed on the surface of the epitaxial region, at least a first conduction type source region formed on the surface of the body regions, a source electrode contact region formed on the surface of the body regions and overlapping the source region and having at least one end longer than one end of the source region, and a plurality of gate electrodes staggered with the source electrode contact region and formed on the body regions and the epitaxial region. | 2009-01-01 |
20090001460 | PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions. | 2009-01-01 |
20090001461 | LATERAL DMOS DEVICE AND METHOD FOR FABRICATING THE SAME - An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance. | 2009-01-01 |
20090001462 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region. | 2009-01-01 |
20090001463 | FINFET FIELD EFFECT TRANSISTOR INSULTATED FROM THE SUBSTRATE - A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates. | 2009-01-01 |
20090001464 | FINFET WITH TOP BODY CONTACT - FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin. | 2009-01-01 |
20090001465 | METHOD OF FORMING A GUARD RING OR CONTACT TO AN SOI SUBSTRATE - A method is provided of forming a conductive via in contact with a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region. The trench isolation region may share an edge with an SOI layer of the substrate. Desirably, a dielectric layer is deposited over a top surface of the conformal layer and the trench isolation region. A second opening can then be formed which extends through the dielectric layer and the first opening in the conformal layer. Desirably, portions of the bulk semiconductor region and the top surface of the conformal layer are exposed within the second opening. The second opening can then be filled with at least one of a metal or a semiconductor to form a conductive element contacting the exposed portions of the bulk semiconductor region and the top surface of the conformal layer. | 2009-01-01 |
20090001466 | METHOD OF FORMING AN SOI SUBSTRATE CONTACT - A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening. | 2009-01-01 |
20090001467 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPLIANCE - To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist. | 2009-01-01 |
20090001468 | METHOD OF FABRICATING TRANSISTOR INCLUDING BURIED INSULATING LAYER AND TRANSISTOR FABRICATED USING THE SAME - In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed. A buried insulating layer is formed to fill a region from which the sacrificial layer is removed. A buried semiconductor layer is grown in the recess. An extending recess extends from the recess and is formed to expose the semiconductor substrate. The extending recess separates the buried insulating layer into a first buried insulating layer pattern and a second buried insulating layer pattern, which are self-aligned to the first and second top semiconductor layer patterns, respectively. | 2009-01-01 |
20090001469 | Display device and method for manufacturing the same - A semiconductor substrate is formed into a regular hexagon or a shape similar to the regular hexagon. The semiconductor substrate is bonded to and separated from a large-area substrate. Moreover, layout is designed so that a boundary of bonded semiconductors is located in a region which is removed by etching when patterning is performed by photolithography or the like. | 2009-01-01 |
20090001470 | METHOD FOR FORMING ACUTE-ANGLE SPACER FOR NON-ORTHOGONAL FINFET AND THE RESULTING STRUCTURE - In a method of fabricating a semiconductor finFET transistor for an integrated circuit chip comprising 1) the formation of at least one fin body on the surface of a substrate and 2) the formation of a gate on said fin body in a non-orthogonal orientation relative to the body thereby creating acute angle regions at the crossover of the gate on the body, and 3) the formation of a protective material in the acute angle regions so as to prevent damage to the gate during subsequent fabrication steps. The structure of the finFET transistor comprises such a transistor with protective material in the acute angle regions at the crossover of the gate on the body. | 2009-01-01 |
20090001471 | Semiconductor Device - For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. | 2009-01-01 |
20090001472 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES INCLUDING THE SAME - A method for fabricating a semiconductor device is provided. According to this method, a first gate electrode and a second gate electrode are formed overlying a first portion of a silicon substrate, and ions of a first conductivity-type are implanted into a second portion of the silicon substrate to define a first conductivity-type diode region within the silicon substrate. Ions of a second conductivity-type are implanted into a third portion of the silicon substrate to define a second conductivity-type diode region within the silicon substrate. During one of the steps of implanting ions of the first conductivity-type and implanting ions of the second conductivity-type, ions are also implanted into at least part of the first portion to define a separation region within the first portion. The separation region splits the first portion into a first well device region and a second well device region. The separation region is formed in series between the first well device region and the second well device region. | 2009-01-01 |
20090001473 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - At least a laminate of a gate insulating film | 2009-01-01 |
20090001474 | Semiconductor device with reduced fringe capacitance - In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top. | 2009-01-01 |
20090001475 | Semiconductor Device and Method of Fabricating the Same - This patent relates to a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an insulating layer formed in a semiconductor substrate, trenches formed within the insulating layer, silicon layers formed within the trenches, gates formed on the silicon layers, and junctions formed in the silicon layers at both sides of the gates. | 2009-01-01 |
20090001476 | STRESS ENHANCED MOS CIRCUITS - A stress enhanced MOS circuit is provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode. | 2009-01-01 |
20090001477 | Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures - Embodiments of the invention generally relate to semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers. | 2009-01-01 |
20090001478 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A GaN layer and an n-type AlGaN layer are formed over an insulating substrate, and thereafter, a gate electrode, a source electrode and a drain electrode are formed on them. Next, an opening reaching at least a surface of the insulating substrate is formed in the source electrode, the GaN layer and the n-type AlGaN layer. Then, a nickel (Ni) layer is formed in the opening. Thereafter, by conducting dry etching from the back side while making the nickel (Ni) layer serve as an etching stopper, a via hole reaching the nickel (Ni) layer is formed in the insulating substrate. Then, a via wiring is formed extending from an inside the via hole to the back surface of the insulating substrate. | 2009-01-01 |
20090001479 | TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME - By removing an upper portion of a complex spacer structure, such as a triple spacer structure, an upper surface of an intermediate spacer element may be exposed, thereby enabling the removal of the outermost spacer and a material reduction of the intermediate spacer in a well-controllable common etch process. Consequently, sidewall portions of the gate electrode may be efficiently exposed for a subsequent silicidation process, while the residual reduced spacer provides sufficient process margins. Thereafter, highly stressed material may be deposited, thereby providing an enhanced stress transfer mechanism. | 2009-01-01 |
20090001480 | HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE - The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) | 2009-01-01 |
20090001481 | DIGITAL CIRCUITS HAVING ADDITIONAL CAPACITORS FOR ADDITIONAL STABILITY - A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity. | 2009-01-01 |
20090001482 | Transistor of Semiconductor Device and Method for Fabricating the Same - Provided is a transistor of a semiconductor device and a method for fabricating the same. A transistor of a semiconductor device may include: a semiconductor substrate having an active region defined by an isolation layer; a recess trench formed in the active region and disposed to cross the semiconductor substrate in one direction; and a gate line formed in a straight line pattern, overlapping the recess trench and disposed to cross the recess trench at approximately right angles. | 2009-01-01 |
20090001483 | Method for Forming a Nickelsilicide FUSI Gate | 2009-01-01 |
20090001484 | REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS - By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions. | 2009-01-01 |
20090001485 | Semiconductor Device and Manufacturing Method Thereof - Disclosed is a semiconductor device that can be used as a high voltage transistor. The semiconductor device can include a gate electrode on a semiconductor substrate, drift regions in the substrate at opposite sides of the gate electrode, a source region in one of the drift regions and a drain region in the other of the drift regions, and a shallow trench isolation (STI) region in a portion of the drift region between the gate electrode and the drain region. The portion of the drift region below the STI region can have a doping profile in which the concentration of impurities decreases from the concentration at the lower surface of the STI region, and then increases, and then again decreases. | 2009-01-01 |
20090001486 | Forming a cantilever assembly for verticle and lateral movement - In one embodiment, the present invention includes a method for forming a sacrificial oxide layer on a base layer of a microelectromechanical systems (MEMS) probe, patterning the sacrificial oxide layer to provide a first trench pattern having a substantially rectangular form and a second trench pattern having a substantially rectangular portion and a lateral portion extending from the substantially rectangular portion, and depositing a conductive layer on the patterned sacrificial oxide layer to fill the first and second trench patterns to form a support structure for the MEMS probe and a cantilever portion of the MEMS probe. Other embodiments are described and claimed. | 2009-01-01 |
20090001487 | PACKAGED DEVICE AND METHOD OF MANUFACTURING THE SAME - A packaged device includes a package having an inner surface defining a closed internal space, a device chip fixed to the package in the internal space, and a parylene film covering at least a part of the inner surface of the package and/or at least a part of a surface of the device chip. | 2009-01-01 |
20090001488 | Cantilever with integral probe tip - In one embodiment, a metallic micro-cantilever, comprises a silicon substrate, at least one via plug extending from a surface of the silicon substrate, a metallic layer cantilevered from the at least one via plug, and a metallic probe tip extending from a surface of the metallic layer. | 2009-01-01 |
20090001489 | SILICON PHOTODETECTOR AND METHOD FOR FORMING THE SAME - A structure of a silicon photodetector and a method for forming the same by using the conventional CMOS semiconductor manufacturing process and micro-electromechanical system manufacturing process, in which the micro-electromechanical system manufacturing process (lateral etching process) is applied for elimination of effect and interference caused by a substrate of the silicon photodetector after optical absorption thereof, thereby greatly improving the response speed of the silicon photodetector. This can be done only by applying the lateral etching process onto a portion of the substrate of the silicon photodetector after the semiconductor manufacturing process is finished, through which slow diffusion carriers produced from the optical absorption of the substrate can be effectively reduced and the response speed is thus enhanced. | 2009-01-01 |
20090001490 | Optoelectronic Component that Emits Electromagnetic Radiation and Illumination Module - An optoelectronic component emitting electromagnetic radiation, comprising a housing body which has a cavity, the cavity being fashioned trenchlike and in the cavity a plurality of semiconductor chips being arranged in a linear arrangement. Two neighboring semiconductor chips have a distance from one another which is less than or equal to one-and-a-half lateral edge lengths of the semiconductor chips and greater than or equal to 0 μm. In addition, an illumination module comprising such a component is disclosed. | 2009-01-01 |
20090001491 | Method for producing a microchip that is able to detect infrared light with a semiconductor at room temperature - The inventions relate to a method for producing a microchip that is able to detect infrared light with a semiconductor, the basic infrared light is absorber by the semiconductor surrounded, attached or embedded in a polymer which is brought in a thin layer on the surface of the semiconductor and which is grown by polymer around the semiconductor in an acid fluid. | 2009-01-01 |
20090001492 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. The image sensor can comprise a substrate, a metal pad, and a sulfur layer. The substrate can include a pixel region and a pad region. The metal pad can be formed of a material containing sulfur and can be diposed in the pad region of the substrate. The sulfur layer can be formed from the sulfur of the metal pad and provided on a top surface of the metal pad. | 2009-01-01 |
20090001493 | ELECTRONIC IMAGING DEVICE - An electronic imaging device includes a base layer containing electrical functional circuitry, the base layer having a first side for interconnection of the circuitry and a second side which serves as a photo-detection side. The second side has exposed photosensitive electrical elements arranged in the base layer. Spacers of a predetermined height are provided adjacent to said second side. The spacers can advantageously be used for gaining control over the tolerance of a desired distance between a lens of a lens system and said photo-detection side. Thus, individual focusing of the lens system of each imager device after completion of production is no longer needed. Moreover, an air gap that improves the performance of the micro-lenses may be formed. | 2009-01-01 |
20090001494 | Backside illuminated image sensor - A backside illuminated image sensor includes a photodiode, formed below the top surface of a semiconductor substrate, for receiving light illuminated from the backside of the semiconductor substrate to generate photoelectric charges, a reflecting gate, formed on the photodiode over the front upper surface of the semiconductor substrate, for reflecting light illuminated from the backside of the substrate and receiving a bias to control a depletion region of the photodiode, and a transfer gate for transferring photoelectric charges from the photodiode to a sensing node of a pixel. | 2009-01-01 |
20090001495 | Image sensor package and fabrication method thereof - The invention provides an image sensor package and method for fabricating the same. The image sensor package comprises a first substrate comprising a sensor device thereon and a hole therein. A bonding pad comprising a first opening is formed on an upper surface of the first substrate. A second substrate comprising a spacer element with a second opening therein is disposed on the first substrate. A conductive plug is formed in the hole and passes through the first and second openings to the second substrate to electrically contact with the bonding pad. A conductive layer is formed on a lower surface of the first substrate and electrically connects to the conductive plug. A solder ball is formed on the conductive layer and electrically connects to the bonding pad by the conductive plug. The image sensor package further comprises a second substrate bonding to the first substrate. The image sensor package is relatively less thick, thus, the dimensions thereof are relatively reduced. | 2009-01-01 |
20090001496 | PHOTODIODE, SOLID STATE IMAGE SENSOR, AND METHOD OF MANUFACTURING THE SAME - A photodiode formed over a silicon substrate is disclosed. The photodiode includes a light-receiving region formed of a diffusion region of a first conduction type at the surface of the silicon substrate and forming a pn junction; an intermediate region formed of a diffusion region of the first conduction type at the surface of the silicon substrate so as to be included in the light-receiving region; a contact region formed of a diffusion region of the first conduction type at the surface of the silicon substrate so as to be included in the intermediate region; a shield layer formed of a diffusion region of a second conduction type in a part of the surface of the silicon substrate outside the intermediate region; and an electrode in contact with the contact region. The shield layer faces the side end part of the diffusion region forming the intermediate region. | 2009-01-01 |
20090001497 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM. | 2009-01-01 |
20090001498 | Nanowire photodiodes and methods of making nanowire photodiodes - Nanowire-based photodiodes are disclosed. The photodiodes include a first optical waveguide having a tapered first end, a second optical waveguide having a tapered second end, and at least one nanowire comprising at least one semiconductor material connecting the first and second ends in a bridging configuration. Methods of making the photodiodes are also disclosed. | 2009-01-01 |
20090001499 | THICK ACTIVE LAYER FOR MEMS DEVICE USING WAFER DISSOLVE PROCESS - Methods for producing MEMS (microelectromechanical systems) devices with a thick active layer and devices produced by the method. An example method includes heavily doping a first surface of a first silicon wafer with P-type impurities, and heavily doping a first surface of a second silicon wafer with N-type impurities. The heavily doped first surfaces are then bonded together, and a second side of the first wafer opposing the first side of the first wafer is thinned to a desired thickness, which may be greater than about 30 micrometers. The second side is then patterned and etched, and the etched surface is then heavily doped with P-type impurities. A cover is then bonded to the second side of the first wafer, and the second wafer is thinned. | 2009-01-01 |
20090001500 | Method and structure for implanting bonded substrates for electrical conductivity - A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material is joined to the second face region of the second substrate. The substrate has an interface region formed between the first face region of the thickness of material and the second face region of the second substrate. A plurality of particles are implanted within a portion of the thickness of the material and a portion of the interface region to electrically couple a portion of the thickness of material to a portion of the second substrate. | 2009-01-01 |
20090001501 | Fiber Soi Substrate, Semiconductor Device Using Same and Method for Manufacturing Same - The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. | 2009-01-01 |
20090001502 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer. | 2009-01-01 |