01st week of 2009 patent applcation highlights part 49 |
Patent application number | Title | Published |
20090004808 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed upper portions of the storage nodes, removing the sacrificial layer under the supporters, and removing the supporters. | 2009-01-01 |
20090004809 | Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material - A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers. | 2009-01-01 |
20090004810 | Method of Fabricating Memory Device - Disclosed herein is a method of fabricating a memory device. The method includes forming an etch stop layer, bit lines, and a first hard mask pattern over a semiconductor substrate. A first SNC plug is formed between the bit lines, and an etch process is performed to reduce the height of the first hard mask pattern and the first SNC plug, to increase a top width of the first hard mask pattern, and to reduce a top width of the first SNC plug. The method also includes forming a second hard mask pattern on the first hard mask pattern, and forming a second SNC plug between the second hard mask patterns. | 2009-01-01 |
20090004811 | Semiconductor composite device, method for manufacturing the semiconductor composite device, led head that employs the semiconductor composite device, and image forming apparatus that employs the led head - A semiconductor composite apparatus includes a semiconductor thin film and a metal layer formed on a substrate. The semiconductor thin film is bonded to the metal layer formed on the substrate. A region is formed between the semiconductor thin film and the metal surface, and contains an oxide of a metal that forms the metal surface. The metal surface is a surface of a metal layer provided on the substrate. The metal surface contains an element selected from the group consisting of Pd, Ni, Ge, Pt, Ti, Cr, and Au. The metal surface is coated with either a Pd layer or an Ni layer. | 2009-01-01 |
20090004812 | METHOD FOR PRODUCING SHALLOW TRENCH ISOLATION - The present invention provides a method for producing a shallow trench isolation, comprises: forming a plurality of first grooves on a silicon substrate with a mask etching method, wherein the silicon substrate comprises a silicon layer, an oxide layer and a first polysilicon layer; conducting oxidation process on an inner peripheral portion of the second grooves to form an insulting layer. The depth of the insulating layer on the periphery of the first polysilicon layer formed by the oxidation process is larger than the depths of the insulating layers that are formed on the silicon layer and on the oxidation layer through the oxidation process; filling high density plasma oxide layer into the second grooves to form a plurality of high density plasma oxide layer fillers; removing the first polysilicon layer by etching; covering the silicon substrate with a second polysilicon layer by deposition; and polishing the second polysilicon layer to form a plurality of self-aligned floating gate. | 2009-01-01 |
20090004813 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - A method and system are provided for fabricating a semiconductor device that includes a vertical channel transistor. An area of a buried bit line is uniformly formed by an isolation trench. The width of the isolation trench is adjusted by controlling the thickness of spacers. Consequently, the area of the buried bit line is relatively large compared with that of a typical buried bit line. The resistance characteristics of the buried bit line are improved and stability and reliability of the semiconductor device are ensured. | 2009-01-01 |
20090004814 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved. | 2009-01-01 |
20090004815 | Method for Manufacturing Semiconductor Device - Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to prevent generation of a void when a device isolation structure is formed by a Shallow Trench Isolation (STI) method, and to prevent formation of stress between the semiconductor substrate and the FOX. | 2009-01-01 |
20090004816 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method of forming an isolation layer in a semiconductor device using rapid vapor deposition to fill in a trench of the semiconductor device comprises forming a hydrophilic layer on the trench and forming a hydrophobic layer on a region other than the trench, and selectively forming a buried insulating layer in the trench using a catalytic reaction of the hydrophilic layer. | 2009-01-01 |
20090004817 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench. | 2009-01-01 |
20090004818 | Method of Fabricating Flash Memory Device - Disclosed herein is a method of fabricating a semiconductor flash memory device, which method avoids and prevents damage to the conductive layer of a floating gate. The disclosed method can prevent a reduction in the charge trap density characteristics and improve the yield of the device. | 2009-01-01 |
20090004819 | Method of Fabricating Flash Memory Device - In one aspect of the inventive method, a tunnel insulating film, a first conductive layer, and an isolation mask pattern are formed over a semiconductor substrate. The first conductive layer and the tunnel insulating film are patterned along the isolation mask pattern. A trench is formed in the semiconductor substrate. The trench is gap filled with a first insulating film. A polishing process is performed in order to expose the first conductive layer. A height of the first insulating film is lowered. The first conductive layer on the first insulating film is gap-filled with a second insulating film. | 2009-01-01 |
20090004820 | Method of Forming Isolation Layer in Flash Memory Device - The invention relates to a method of forming an isolation layer in a flash memory device and comprises providing a semiconductor substrate in which a tunnel insulating layer and a conductive layer are formed on an active region and a trench is formed on an isolation region; forming a first insulating layer in a lower portion of the trench; forming a second insulating layer on the semiconductor substrate and the first insulating layer including the trench to protect a side wall of the conductive layer; forming a third insulating layer in the trench to form an isolation layer; and adjusting an effective field height (EFH) of the isolation layer through a first etching process. | 2009-01-01 |
20090004821 | MANUFACTURING METHOD OF SOI SUBSTRATE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor substrate, so that an SOI substrate is manufactured. A gettering site layer is formed of a semiconductor containing a Group 18 element such as Ar, over a semiconductor layer of the SOI substrate. Heat treatment is performed thereon to perform gettering of a metal element in the semiconductor layer with the gettering site layer. By removing the gettering site layer by etching, thinning of the semiconductor layer can be performed. | 2009-01-01 |
20090004822 | Semiconductor substrate, manufacturing method of semiconductor substrate, and semiconductor device and electronic device using the same - A method of manufacturing a semiconductor substrate is demonstrated, which enables the formation of a single crystal semiconductor layer on a substrate having an insulating surface. The manufacturing method includes the steps of: ion irradiation of a surface of a single-crystal semiconductor substrate to form a damaged region; laser light irradiation of the single-crystal semiconductor substrate; formation of an insulating layer on the surface of the single-crystal semiconductor substrate; bonding the insulating layer with a substrate having an insulating surface; separation of the single-crystal semiconductor substrate at the damaged region, resulting in a thin single-crystal semiconductor layer on the surface of the substrate having the insulating surface; and laser light irradiation of the surface of the single-crystal semiconductor layer which is formed on the substrate having the insulating surface. This method allows the production of a thin layer of a single-crystal semiconductor with uniformed characteristics on an insulating surface. | 2009-01-01 |
20090004823 | Manufacturing method of semiconductor - A manufacturing method of a semiconductor device in which a space between semiconductor films transferred to a plurality of places can be made small. Transfer of a semiconductor film from a bond substrate to a base substrate is carried out a plurality of times. In the case where a semiconductor film transferred first and a semiconductor film transferred later are provided adjacently, the latter transfer is carried out using a bond substrate with its end portion partially removed. The width in a perpendicular direction to the bond substrate used for the later transfer, of the region of the bond substrate corresponding to the removed end portion is larger than the thickness of the semiconductor film which is transferred first. | 2009-01-01 |
20090004824 | METHOD, APPARATUS FOR HOLDING AND TREATMENT OF A SUBSTRATE - Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area. | 2009-01-01 |
20090004825 | METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE - A method of manufacturing a semiconductor substrate having a DSB structure that enables simplification of a manufacturing process by optimizing a total thickness of oxides on surfaces of two wafers before being bonded together is provided. The method comprises a process of preparing a first semiconductor wafer and a second semiconductor wafer, a process of bonding the first semiconductor wafer and second semiconductor wafer when a total of thickness of an oxide on the surface of the first semiconductor wafer and that of an oxide on the surface of the second semiconductor wafer is 0.4 nm or more and 1.0 nm or less, and a process of providing heat treatment to a semiconductor substrate after the process of the bonding and before a process of thinning one of the wafers. | 2009-01-01 |
20090004826 | Method of manufacturing a semiconductor device - In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process. | 2009-01-01 |
20090004827 | LEAD CUTTER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die | 2009-01-01 |
20090004828 | LASER BEAM MACHINING METHOD FOR WAFER - A laser beam machining method for a wafer, wherein an operation of irradiating the inside of a wafer with a laser beam L along each of planned dividing lines is repeated a plural number of times from a position proximate to a back-side surface of the wafer toward a face-side surface of the wafer so that a plurality of composite layers each including a denatured layer and a cracked layer extending from the denatured layer toward the face-side surface are formed stepwise at intervals (first laser beam irradiation step). Subsequently, each of some of non-cracked layers between the composite layers is irradiated with the laser beam L so as to extend the cracked layer of a given one of the composite layers and to cause the cracked layer to reach the denatured layer of the composite layer which is adjacent to the given one composite layer. The denatured layers and the cracked layers which are sufficient for enabling the wafer to be split are formed by a reduced number of laser beam irradiation operations. | 2009-01-01 |
20090004829 | Adhesive Composition, Adhesive Sheet and Production Process for Semiconductor Device - An adhesive sheet which can actualize a high package reliability wherein there is no separation at the adhesive interface and no package cracking, in a package in which a semiconductor chip being reduced in thickness is mounted under severe reflow conditions after exposure to a hot and humid environment. The adhesive sheet includes a base material and, formed thereon, an adhesive layer having an adhesive composition including an acrylic copolymer (A) containing 20 to 95% by weight of a structural unit derived from a benzyl(meth)acrylate, an epoxy thermosetting resin (B), and a thermosetting agent (C). | 2009-01-01 |
20090004830 | Device and method for depositing especially doped layers by means of OVPD or the like - The invention relates to a method for producing especially doped layers for electronic, luminescent or photovoltaic components, especially OLEDs, where one or more liquid or solid starting materials evaporate in a source ( | 2009-01-01 |
20090004831 | METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES - A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same. | 2009-01-01 |
20090004832 | Thick Film Semiconducting Inks - A method of producing a printable composition comprises mixing a quantity of particulate semiconductor material with a quantity of a binder. The semiconductor material is typically nanoparticulate silicon with a particle size in the range from 5 nanometres to 10 microns. The binder is a self-polymerising material comprising a natural oil, or a derivative or synthetic analogue thereof. Preferably the binder comprises a natural polymer formed by auto-polymerisation of a precursor consisting of a natural oil, or its derivatives including pure unsaturated fatty acids, mono- and di-glycerides, or methyl and ethyl esters of the corresponding fatty acids. The method may include applying the printable composition to a substrate, in single or multiple layers, and allowing the printable composition to cure to define the component or conductor on the substrate. | 2009-01-01 |
20090004833 | METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE - A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer. | 2009-01-01 |
20090004834 | SUBSTRATES AND METHODS FOR FABRICATING THE SAME - An embodiment of the invention provides a substrate. The substrate comprises a single crystal substrate. An epitaxial buffer film is on the single crystal substrate. An epitaxial ZnGa | 2009-01-01 |
20090004835 | Method for producing semi-conducting material wafers by moulding and directional crystallization - Wafers of semi-conducting material are formed by moulding and directional crystallization from a liquid mass of this material. A seed, situated at the bottom of the crucible, presents an orientation along non-dense crystallographic planes. The mould is filled with the molten semi-conducting material by means of a piston or by creation of a pressure difference in the device. The mould is preferably coated with a non-wettable anti-adhesive deposit. | 2009-01-01 |
20090004836 | PLASMA DOPING WITH ENHANCED CHARGE NEUTRALIZATION - A plasma doping apparatus includes a pulsed power supply that generates a pulsed waveform having a first period with a first power level and a second period with a second power level. A plasma source generates a pulsed plasma with the first power level during the first period and with the second power level during the second period. A bias voltage power supply generates a bias voltage waveform at an output that is electrically connected to a platen which supports a substrate. The bias voltage waveform having a first voltage during a first period and second voltage with a negative potential that attract ions in the plasma to the substrate for plasma doping during a second period. At least one of the first and second power levels of the RF waveform is chosen to at least partially neutralize charge accumulating on the substrate. | 2009-01-01 |
20090004837 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device having an impurity region with an impurity concentration of a first dose in a substrate. In the method, first impurity ions of a first conductivity type are implanted into the substrate, and a rapid thermal processing (RTP) is performed on the substrate to activate the first impurity ions. Second impurity ions of the first conductivity type are implanted into the substrate having the activated first impurity ions. | 2009-01-01 |
20090004838 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: forming an etching layer ( | 2009-01-01 |
20090004839 | METHOD FOR FABRICATING AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR DEVICE - In a method for fabricating an interlayer dielectric in a semiconductor device, conductive patterns are formed on a semiconductor substrate. A fluid dielectric is formed to cover the conductive patterns. The fluid dielectric is recessed. A buried dielectric is deposited on the conductive patterns exposed by the recessing process. The buried dielectric is denser than the fluid dielectric, thereby forming an interlayer dielectric including the fluid dielectric and the buried dielectric. | 2009-01-01 |
20090004840 | Method of Creating Molds of Variable Solder Volumes for Flip Attach - A method for fabricating a solder transfer mold includes masking a substrate with a masking agent. A pattern is transferred to the substrate mask. The masked substrate is etched until cavities of a first volume are formed. The cavities of the first volume are selectively coated. The masked substrate is etched until cavities of a second volume are formed. | 2009-01-01 |
20090004841 | Forming vias using sacrificial material - In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed. | 2009-01-01 |
20090004842 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a method of fabricating a semiconductor device. According to the method, a first insulating layer having a contact hole formed therein is formed over a semiconductor substrate. A second insulating layer is gap filled within the contact hole. A third insulating layer having a trench formed therein is formed over the semiconductor substrate including the contact hole. The second insulating layer gap filled within the contact hole is removed. A contact plug and a bit line are formed within the contact hole and the trench. | 2009-01-01 |
20090004843 | METHOD FOR FORMING DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY - Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer. | 2009-01-01 |
20090004844 | Forming Complimentary Metal Features Using Conformal Insulator Layer - A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface. | 2009-01-01 |
20090004845 | Method for Making Semiconductor Structures Implementing Sacrificial Material - Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional. | 2009-01-01 |
20090004846 | WIRING BOARD, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention provides a semiconductor device in which a display device is integrated with such high-performance functional circuit on the same substrate. According to the invention, first to third wirings, first and second interlayer insulating films and first and second contact holes are formed over a substrate having an insulating surface. The second wiring is wider than the first wiring, or the third wiring is wider than the first wiring or the second wiring. The second contact hole has a larger diameter than the first contact hole. | 2009-01-01 |
20090004847 | Method of manufacturing semiconductor device - Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. | 2009-01-01 |
20090004848 | METHOD FOR FABRICATING INTERCONNECTION IN SEMICONDUCTOR DEVICE - A method for fabricating an interconnection in a semiconductor device includes forming a hydrogenated tungsten nucleation layer on a semiconductor substrate, and forming a bulk tungsten layer on the tungsten nucleation layer. Boron ions react with a hydrogen gas supplied together with a diborane gas to be restored to a diborane again, thereby preventing a boron layer from being formed on an interface of the tungsten nucleation layer. | 2009-01-01 |
20090004849 | METHOD FOR FABRICATING AN INTER DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE - In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located. | 2009-01-01 |
20090004850 | PROCESS FOR FORMING COBALT AND COBALT SILICIDE MATERIALS IN TUNGSTEN CONTACT APPLICATIONS - Embodiments of the invention described herein generally provide methods for forming cobalt silicide layers and metallic cobalt layers by using various deposition processes and annealing processes. In one embodiment, a method for forming a metallic silicide containing material on a substrate is provided which includes forming a metallic silicide material over a silicon-containing surface during a vapor deposition process by sequentially depositing a plurality of metallic silicide layers and silyl layers on the substrate, depositing a metallic capping layer over the metallic silicide material, heating the substrate during an annealing process, and depositing a metallic contact material over the barrier material. In one example, the metallic silicide layers and the metallic capping layer both contain cobalt. The cobalt silicide material may contain a silicon/cobalt atomic ratio of about 1.9 or greater, such as greater than about 2.0, or about 2.2 or greater. | 2009-01-01 |
20090004851 | SALICIDATION PROCESS USING ELECTROLESS PLATING TO DEPOSIT METAL AND INTRODUCE DOPANT IMPURITIES - A selective electroless plating operation provides for the selective deposition of a metal film only on exposed silicon surfaces of a semiconductor substrate and not on other surfaces such as dielectric surfaces. The plating solution includes metal ions and advantageously also includes dopant impurity ions. The pure metal or metal alloy film formed on the exposed silicon surfaces is then heat treated to form a metal silicide on the exposed silicon surfaces and to drive the dopant impurities to the interface formed between the exposed silicon surfaces and the metal silicide film. | 2009-01-01 |
20090004852 | Nanostructures Containing Metal Semiconductor Compounds - A network element ( | 2009-01-01 |
20090004853 | METHOD FOR FORMING A METAL SILICIDE - The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less. | 2009-01-01 |
20090004854 | Method of Fabricating Flash Memory Device - The present invention relates to a method of fabricating a flash memory device. The method may include forming a first and a second interlayer insulating film on a semiconductor substrate having a cell region, etching the second and first interlayer insulating films, thus forming a contact hole through which a junction region of the cell region is exposed, forming a contact plug within the contact hole, the contact plug having a height lower than that of an interface of the first and second interlayer insulating films, and forming a spacer on sidewalls of the contact hole over the contact plug. | 2009-01-01 |
20090004855 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching the gate spacer layer at a bottom of the recess, and forming a plug on the recess, thereby forming a second resulting structure including the plug. | 2009-01-01 |
20090004856 | METHOD OF FORMING CONTACT PLUG IN SEMICONDUCTOR DEVICE - A method of forming a contact plug in a semiconductor device comprising etching an interlayer insulating layer to form a patterned interlayer insulating layer having contact holes such that a distance between upper portions of the contact holes is minimized; forming a first insulating layer including a overhang portion for wrapping an upper portion of the patterned interlayer insulating layer; forming a liner-shaped second insulating layer on the patterned interlayer insulating layer including the first insulating layer, the second insulating layer being formed from material having a selectivity which differs from that of the first insulating layer; and at least partially removing the second insulating layer to increase a bottom critical dimension of the contact hole and removing the overhang portion of the first insulating layer. The invention can secure the bottom critical dimension of the contact hole as well as a distance between the upper portions of the contact holes when the contact plug is formed in a trench in a subsequent process so that the subsequent process margin can be secured. Also, the invention can inhibit an overhang or seam from being formed on the contact plug to enhance contact gap-fill capability and improve contact resistance. | 2009-01-01 |
20090004857 | Method of manufacturing a semiconductor device using the self aligned contact (SAC) process flow for semiconductor devices with aluminum metal gates - In one embodiment, a method, comprises forming a diffusion layer on a semiconductor substrate, forming a selectively deposited metal or metal alloy on an aluminum gate structure by removing an aluminum oxide layer from the aluminum gate structure and depositing a zinc layer on the aluminum gate structure by a zincating process, and selectively depositing a sacrificial metal or metal alloy cap on the aluminum gate layer by displacing the zinc layer. This embodiment enables the SAC process flow on devices with Aluminum gates. | 2009-01-01 |
20090004858 | TANTALUM AMIDE COMPLEXES FOR DEPOSITING TANTALUM-CONTAINING FILMS, AND METHOD OF MAKING SAME - Tantalum precursors useful in depositing tantalum nitride or tantalum oxides materials on substrates, by processes such as chemical vapor deposition and atomic layer deposition. The precursors are useful in forming tantalum-based diffusion barrier layers on microelectronic device structures featuring copper metallization and/or ferroelectric thin films. | 2009-01-01 |
20090004859 | METHOD OF MACHINING WAFER - A method of machining a wafer in which, at the time of grinding the back-side surface of the wafer, only a back-side surface region corresponding to a device formation region where semiconductor chips are formed is thinned by grinding, to form a recessed part on the back side of the wafer. An annular projected part surrounding the recessed part is utilized to secure rigidity of the wafer. Next, the recessed part is etched to cause metallic electrodes to project from the bottom surface of the recessed part, thereby forming a back-side electrode parts, then an insulating film is formed in the recessed part, and the insulating film and end surfaces of the back-side electrode parts are cut. | 2009-01-01 |
20090004860 | ATOMIC LAYER VOLATILIZATION PROCESS FOR METAL LAYERS - A two-stage method to remove a metal layer from a substrate surface comprises using a CMP process to remove a first portion of the metal layer from the substrate surface, and using an ALV process to remove a second portion of the copper layer from the substrate surface. The ALV process comprises pulsing a co-reactant into a reactor housing the substrate, wherein the co-reactant reacts with the metal layer to form a volatile metal-containing product, and then evacuating the reactor to volatize and remove the metal-containing product. | 2009-01-01 |
20090004861 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL - A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask pattern and the insulation layer until the pillars are exposed, and forming a storage electrode over the exposed pillars. | 2009-01-01 |
20090004862 | Method for forming fine patterns in semiconductor device - A method for forming fine patterns in a semiconductor device includes forming an etch stop layer and a sacrificial layer over an etch target layer, forming photoresist patterns over the sacrificial layer, etching the sacrificial layer by using the photoresist patterns as an etch barrier to form sacrificial patterns, forming spacers on both sidewalls of the sacrificial patterns, removing the sacrificial patterns, and etching the etch stop layer and the etch target layer by using the spacer as an etch barrier. | 2009-01-01 |
20090004863 | POLISHING LIQUID AND POLISHING METHOD USING THE SAME - The present invention provides a polishing liquid for polishing a ruthenium-containing barrier layer, the polishing liquid being used in chemical mechanical polishing for a semi-conductor device having a ruthenium-containing barrier layer and conductive metal wiring lines on a surface thereof, the polishing liquid comprising an oxidizing agent; and a polishing particulate having hardness of 5 or higher on the Mohs scale and having a composition in which a main component is other than silicon dioxide (SiO | 2009-01-01 |
20090004864 | CMP METHOD OF SEMICONDUCTOR DEVICE - The present invention relates to a Chemical Mechanical Polishing (CMP) method of a semiconductor device. According to the method, a metal layer is formed over a semiconductor substrate in which an edge region define. A passivation layer is formed on the metal layer. The passivation layer formed in the edge region is etched in order to expose the metal layer. The exposed metal layer is removed through etching. The metal layer is polished by performing a CMP process, thus forming a metal line. | 2009-01-01 |
20090004865 | METHOD FOR TREATING A WAFER EDGE - A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized to effectuate a cleaning of an edge portion of a wafer. | 2009-01-01 |
20090004866 | METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a target etch layer over a substrate, a first auxiliary layer over the target etch layer, an isolation layer over the first auxiliary layer, and a second auxiliary layer over the isolation layer. A first exposure process is performed, where the first auxiliary layer is in focus and the second auxiliary layer is out of focus. A second exposure process is performed, where the second auxiliary layer in focus and the first auxiliary layer is out of focus. The second auxiliary layer is developed to form first mask patterns. The isolation layer and the first auxiliary layer are etched by using the first mask patterns to form second mask patterns. The second mask patterns are developed to form third mask patterns that are used to facilitate subsequent etching of the target etch layer. | 2009-01-01 |
20090004867 | Method of Fabricating Pattern in Semiconductor Device Using Spacer - A method of fabricating patterns of a semiconductor device includes the steps of forming first sacrificial layer patterns over a pattern target layer; forming first spacers on sidewalls of the first sacrificial layer patterns; forming a second sacrificial layer pattern over the first sacrificial layer patterns and the first spacers such that at least one of the first spacers is exposed by the second sacrificial layer pattern; forming a dual spacer by forming a second spacer on the exposed first spacer; removing the second sacrificial layer pattern and the first sacrificial layer patterns; and forming a first pattern having a first pitch defined by the first spacers and a second pattern having a second pitch defined by the dual spacer by etching an exposed portion of the pattern target layer using the first spacers and the dual spacer as etching masks. | 2009-01-01 |
20090004868 | Amorphous silicon oxidation patterning - In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor substrate between the oxide structures. | 2009-01-01 |
20090004869 | MASK FORMING AND IMPLANTING METHODS USING IMPLANT STOPPING LAYER - Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks. | 2009-01-01 |
20090004870 | METHODS FOR HIGH TEMPERATURE ETCHING A HIGH-K MATERIAL GATE STRUCTURE - Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma. | 2009-01-01 |
20090004871 | PROCESSING METHOD AND PLASMA PROCESSING DEVICE - A plasma processing method using plasma includes steps of applying current to a coil and introducing gas into a processing chamber, applying a bias power that does not generate plasma, applying a source power to generate plasma so that a plasma density distribution is high above an outer circumference of a semiconductor wafer and low above a center of the semiconductor wafer, and forming a shape of a sheath layer having a positive ion space charge directly above the semiconductor wafer so as to be convex in an upper direction from the semiconductor wafer, thereby eliminating foreign particles trapped in a boundary of the sheath layer having a positive ion space charge directly above the semiconductor wafer, generating plasma for processing the semiconductor wafer under a condition different from the conditions of the previous steps. | 2009-01-01 |
20090004872 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting of one step or two steps is applied to the formation of the gate electrode. | 2009-01-01 |
20090004873 | HYBRID ETCH CHAMBER WITH DECOUPLED PLASMA CONTROLS - A dielectric etch chamber and method for improved control of plasma parameters. The plasma chamber comprises dual-frequency bias source that capacitively couples the RF energy to the plasma, and a single or dual frequency source that inductively couples the RF energy to the plasma. The inductive source may be modulated for improved etch uniformity. | 2009-01-01 |
20090004874 | Inductively coupled dual zone processing chamber with single planar antenna - A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the processing chamber. One or more gas sources in fluid communication with one or more gas distribution members supply process gas to a first zone adjacent to the first substrate support and a second zone adjacent to the second substrate support. A radio-frequency (RF) antenna adapted to inductively couple RF energy into the interior of the processing chamber and energize the process gas into a plasma state in the first and second zones. The antenna is located between the first substrate support and the second substrate support. | 2009-01-01 |
20090004875 | METHODS OF TRIMMING AMORPHOUS CARBON FILM FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE - Methods for forming an ultra thin structure using a method that includes trimming a mask layer during an etching process are provided. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on an underlying layer, trimming the photoresist layer to a first predetermined critical dimension, etching the hardmask layer through openings defined by the trimmed photoresist layer, trimming the hardmask layer to a second predetermined critical dimension, and etching the underlying layer through openings defined by the trimmed hardmask layer. | 2009-01-01 |
20090004876 | Method for Etching Single Wafer - An object of the present invention is to provide a method for etching a single wafer, which effectively realizes a high flatness of wafer and an increase in productivity thereof. In a method for etching a single wafer, a single thin disk-like wafer sliced from a silicon single crystal ingot is spun, and a front surface of the wafer is etched with an etching solution supplied thereto. In the method, a plurality of supply nozzles are disposed above and opposite to the front surface of the wafer at different portions in the radial direction of the wafer, respectively; and then one or more conditions selected from the group consisting of temperatures, kinds, and supply flow rates of etching solutions from the plurality of supply nozzles are changed. | 2009-01-01 |
20090004877 | SUBSTRATE PROCESSING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Disclosed is a substrate processing apparatus which includes: a processing chamber to process a substrate; an exhaust path to exhaust the processing chamber; an exhaust device; an exhaust valve to open and close the exhaust path; a raw material gas supply member to supply raw material gas which contributes to film forming into the processing chamber; a cleaning gas supply member to supply cleaning gas which removes an accretion which adheres to an inside of the processing chamber with the raw material gas being supplied, the cleaning gas supply member comprising a supply path to supply the cleaning gas to the processing chamber and a supply valve to open and close the supply path; and a control section which controls the exhaust valve and the supply valve to supply the cleaning gas from the supply path to the processing chamber with exhaustion of the processing chamber being stopped. | 2009-01-01 |
20090004878 | Method of manufacturing an SOI substrate and method of manufacturing a semiconductor device - It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment. | 2009-01-01 |
20090004879 | TEST STRUCTURE FORMATION IN SEMICONDUCTOR PROCESSING - Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices. | 2009-01-01 |
20090004880 | MASK REUSE IN SEMICONDUCTOR PROCESSING - A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers. | 2009-01-01 |
20090004881 | HYBRID HIGH-K GATE DIELECTRIC FILM - The present invention discloses a method of forming a gate dielectric film including: providing a channel region in a transistor, the channel region including multiple segments having different sizes, some of which belong to a first surface portion while others belong to a second surface portion wherein the first surface portion and the second surface portion are adjacent; forming a hybrid high-k gate dielectric film over the channel region including: forming a first dielectric material over the first surface portion, the first dielectric material having a sub-monolayer thickness; forming a second dielectric material over the second surface portion, the second dielectric material having a sub-monolayer thickness, and forming a third dielectric film over the first dielectric film and the second dielectric film wherein the third dielectric film is high-k. | 2009-01-01 |
20090004882 | Method of forming high-k dual dielectric stack - The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer. | 2009-01-01 |
20090004883 | Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen - Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen. | 2009-01-01 |
20090004884 | OXIDIZING METHOD AND OXIDIZING APPARATUS - An oxidizing method and oxidizing apparatus in which a plasma generating chamber having an oxidizing gas supply port and a substrate processing chamber having an exhaust port and internally having a substrate susceptor are connected via a partition having a number of through holes, a plasma of an oxidizing gas supplied into the plasma generating chamber is generated, and an oxide layer is formed on a substrate surface by supplying the generated active species onto a substrate are characterized in that the partition is connected to a power supply via a switching mechanism such that a positive, negative, or zero voltage is applied to the partition, and an oxidation process is performed by changing the ratio of radicals, positive ions, and negative ions in the active species supplied onto the substrate by switching the voltages at least once during the oxidation process. | 2009-01-01 |
20090004885 | Method for fabricating semiconductor device - An object of the present invention is to provide a method for fabricating a semiconductor device capable of implementing planarization of an insulating film formed on a semiconductor substrate formed thereon with a circuit pattern and inhibiting unevenness of a film thickness of the insulating film, and a device thereof. | 2009-01-01 |
20090004886 | METHOD OF MANUFACTURING AN INSULATING FILM CONTAINING HAFNIUM - A stacked film has an insulating film containing hafnium formed above a silicon layer and a polysilicon layer formed on the insulating film. The stacked film is heated in an atmosphere containing oxygen and nitrogen and having the total pressure approximately equal to a partial pressure of the nitrogen. | 2009-01-01 |
20090004887 | APPARATUS AND METHOD FOR DEPOSITION OF PROTECTIVE FILM FOR ORGANIC ELECTROLUMINESCENCE - In a film deposition apparatus which deposition a film through SWP-CVD, a substrate holder on which a substrate is to be placed is provided with cooling means, thereby inhibiting occurrence of an increase in the temperature of the substrate, which would otherwise be caused during deposition of a film. A coolant passage is formed in the substrate holder, and coolant delivered from a chiller is circulated through the coolant passage, thereby cooling the substrate holder. Further, grooves are formed in the surface of a cooling holder where a substrate is to be placed, and the substrate is cooled by a helium gas by causing the helium gas to flow through the grooves. | 2009-01-01 |
20090004888 | WIRING BOARD AND BUS BAR SEGMENTS TO BE USED THEREFOR - A wiring board formed with electric circuits is provided, wherein said electric circuits are formed by comprising straight bus bar segments, each of the straight bus bar segments having contact portions at opposite ends thereof, said wiring board having means for bringing the respective contact portions into electrical contact | 2009-01-01 |
20090004889 | Board-connecting connector - A board-connecting connector including a pair of inner housings opposed to each other for receiving elastic contact terminals with respect to a circuit board, a guiding plate having a sloped guiding part for engaging inner housing-driven projections and guiding the inner housings close to each other, and an outer housing for receiving the inner housings and the guide plate, and holding the guide plate. When the circuit board is fully inserted into the pair of inner housings, the circuit board abuts on the inner housings, and pushes to move the inner housings along the guiding plate. | 2009-01-01 |
20090004890 | SKIVED ELECTRICAL CONTACT FOR CONNECTING AN IC DEVICE TO A CIRCUIT BOARD AND METHOD OF MAKING A CONTACT BY SKIVING - The disclosed embodiments relate to the formation of an electrical contact using a skiving technique. The electrical contact includes a spring structure that has been skived away from an underlying metal body, but the spring remains coupled with the metal body which provides a base for the spring structure. The skived spring portion of the electrical contact may comprise a cantilever-like spring, a coil-like spring, or any other suitable type of spring. Such a spring contact may be used to form an electrical connection between an integrated circuit device and a circuit board (or other substrate). Other embodiments are described and claimed. | 2009-01-01 |
20090004891 | TEST ACCESS FOR HIGH DENSITY INTERCONNECT BOARDS - A novel HDI board that enables test probe access comprises a stack of insulating layers having a first surface and a second surface, wherein the first surface includes at least two devices and the second surface includes a test probe accessible solder bead. The two devices are electrically coupled by at least one metal interconnect formed within the plurality of insulating layers. The HDI board also includes a backside μVia electrically coupling the solder bead to the metal interconnect. Testing of the device may be carried out by way of the solder bead and the backside μVia. | 2009-01-01 |
20090004892 | Board Connector Module For Mezzanine Circuit Board Assemblies - The invention relates to a board connector module including a frame accommodating an array of substantially-parallel signal leads (S) and ground leads (G) extending in a longitudinal direction (L). The said frame includes edges extending substantially parallel to said leads and one or more transverse bars extending between said edges. The transverse bars of the frame may resist deflection or buckling of these leads and consequently allow for higher stack heights in mezzanine circuit board assemblies. | 2009-01-01 |
20090004893 | Electrical connector assembly - An electrical connector assembly ( | 2009-01-01 |
20090004894 | CONNECTOR FIXING STRUCTURE AND ELECTRONIC APPARATUS - According to one embodiment, a connector fixing structure includes a printed circuit board assembly, and a base to which the printed circuit board assembly is attached. The printed circuit board assembly has a connector mounted on a printed circuit board, and a connector panel attached to the printed circuit board. The connector has a connector main body, a front flange projecting from the connector main body, and a rear flange projecting from the connector main body. The connector panel has a provisional fixing portion which is inserted between the front flange and the rear flange and provisionally fixes the connector to the connector panel. The base has a fixing portion which is inserted between the rear flange and the connector panel, thereby brings the front flange into contact with the connector panel and fixes the connector to the base, when the printed circuit board assembly is attached to the base. | 2009-01-01 |
20090004895 | Bus bar system, method, and kit - A replacement bus system having one or more conductive shafts supporting wire attachment lugs and spacers that ride along the conductive shaft; the spacers are conductive and separate the attachment lugs. The lugs and spacers may be secured onto the shaft by a locking mechanism. By providing a shaft on which the lugs may ride, the wires are configured transversely to conventional approaches, enabling a greater number of wires to be connected over a given length and a wider variety of relative orientation of wires. This configuration also enables much of the structure to be manufactured from stainless steel or other non cuprous metal, except for the spacers, which may be manufactured from tinned copper. | 2009-01-01 |
20090004896 | Sheilded sub-miniature connection assembly and process for equipping such a connection - A shielded sub-miniature connection assembly having two sub-miniature connectors with housings provided with means of locking, two molded thermoplastic half-shells having a high contact density miniature sub-assembly with a molded thermoplastic insulating body provided with contact cavities for the positioning and retention of contacts, a back plate provided with a contact-retaining clip and whose sidewalls comprise projecting dimples, a molded thermoplastic receptacle shell including a flange provided with oblong apertures into which the projecting dimples of the back plate are locked. The disclosed embodiments also concern the process of forming the connection assembly. | 2009-01-01 |
20090004897 | RETRACTABLE MEMORY DRIVE - A retractable memory drive in accordance with the present invention comprises a top casing, a middle carrier, an electronic device such as a USB thumb drive, and a bottom casing. A positioning device on the middle carrier has a portion that protrudes outside the casing and operates like a button. The location of the positioning device where the button is located has two key attributes. First, there is a protrusion that acts as a lock with the casing. Second, the area below the button is not rigid and so it gives way when pressure is applied to the button. The top and bottom casings provide a casing structure which includes two detents. One detent is for locking the device with the connector in the extended position, and one detent for locking the device with the connector retracted in the in position. This allows for just one press of the extended portion of the positioning device to unlock it from its present position. When the device reaches its new position it will automatically lock. There are also guide rails that allow the middle carrier to remain in an appropriate position. | 2009-01-01 |
20090004898 | WIRELESS NETWORK CARD AND USB INTERFACE PROTECTION STRUCTURE THEREOF - A universal serial bus (USB) interface protection structure for protecting a universal serial bus interface wrapped with a metal layer protruding from an electronic device. The USB interface protection structure includes a detachable cap having an open end and a close end, a cavity located on the close end, a magnet contained in the cavity, and a cap cover covering the detachable cap. The magnet has a magnetic force to attract the metal layer of the USB interface for retaining the USB interface in the detachable cap when the USB interface inserts into the detachable cap through the open end. A wireless network card utilizing the USB interface protection structure is also disclosed. | 2009-01-01 |
20090004899 | METHOD AND APPARATUS FOR ELECTROSTATIC DISCHARGE OF CONNECTORS - A port (such as, but not limited to, an RJ45 port) may comprise a cavity having a plurality of pins and an electrostatic discharge element coupled to a system ground. As the plug is inserted into the cavity, the electrostatic discharge element contacts the plug prior to the plug coming into electrical contact with the port pins and provides a discharge path to the system ground during a cable discharge event. Once the plug is fully inserted within the port, the electrostatic discharge element does not electrically contact the plug or the port pins and therefore has substantially no affect on the normal connection between the port and the plug. | 2009-01-01 |
20090004900 | Low profile shorting bar for electrical connector - Disclosed herein is an electrical connector. The electrical connector includes a housing, at least two male contacts, and a shorting member. The at least two male contacts are mounted within the housing. The shorting member is connected to the housing. The shorting member includes a single loop section and an aperture. The single loop section is adapted to contact the at least two male contacts when the electrical connector is disengaged from a mating electrical connector. The single loop section is adapted to be spaced from the at least two male contacts when the electrical connector is engaged with the mating electrical connector. The at least two male contacts extend through the aperture. | 2009-01-01 |
20090004901 | Connector having a stopper mechanism defining a movable range of a housing receiving a connection object - In a connector adapted to be connected to and disconnected from a connection object in connecting and disconnecting directions, the connector includes a first housing for receiving the connection object and a second housing holding the first housing so that the first housing is three-dimensionally movable. A contact is held by the first and the second housings. The second housing includes a stopper mechanism three-dimensionally defining a movable range of the first housing. | 2009-01-01 |
20090004902 | LAND GRID ARRAY (LGA) SOCKET LOADING MECHANISM FOR MOBILE PLATFORMS - Techniques for a land grid array (LGA) socket loaded mechanism for mobile platforms are described. An apparatus includes a LGA socket mounted to a printed circuit board, and a LGA package seated in the LGA socket. The LGA package includes an LGA package substrate and a semiconductor die mounted on the LGA package substrate, and a heat pipe attached to the semiconductor die, wherein the heat pipe is to apply a compressive load to the semiconductor die. The heat pipe includes at least two leaf springs to apply a compressive load to the LGA package substrate. Other embodiments are described and claimed. | 2009-01-01 |
20090004903 | Electrical connector having hybrid standoff - The present invention provides an electrical connector for establishing electrical connection between an IC module and a PCB. The electrical connector comprises an insulative housing and a set of electrical contacts received in the housing. The insullative housing has a mating surface and a mounting surface opposite thereto. The mating surface defines a supporting block extending upwardly thereof for supporting an IC module when said IC module is mated with the electrical connector. A reinforced element is defined in the supporting block, so as to reinforce said supporting block. | 2009-01-01 |
20090004904 | Plug Locking Assembly - A plug locking assembly comprises a housing comprising a top surface, a bottom surface and opposing sidewalls defining an open space therebetween, the open space for receiving and carrying a plug comprising a spring member. The plug locking assembly is adapted to prevent unwanted access to modular plugs engaged in associated jacks. In one embodiment, the plug locking assembly comprises a plug protection member comprising a surface spaced apart from the open space and positioned to overlie at least a portion of the spring member with the plug engaged within the housing. The plug locking assembly may further comprise a locking clip releasably securable within the housing. | 2009-01-01 |
20090004905 | Electrical connector having locking mechanism - An electrical connector ( | 2009-01-01 |
20090004906 | Electrical Connector Having Cam Locking Features - An electrical connector including a jack including an external peripheral groove, a jack center conductor and a jack outer conductor; and a plug configured to receive the jack, the plug including a locking member, a plug center conductor and a plug outer conductor. The external peripheral groove is configured to receive the locking member and the locking member is configured to engage the peripheral groove. The jack center conductor and the plug center conductor are in electrical contact with each other and the jack outer conductor and the plug outer conductor are in contact with each other when the locking member is in engagement with the peripheral groove. | 2009-01-01 |
20090004907 | Connector converters for portable electronic device power adapters - A system is provided for selectively connecting a plurality of diverse power adapters ( | 2009-01-01 |